1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/mm/fault.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Copyright (C) 1995-2004 Russell King 7 * Copyright (C) 2012 ARM Ltd. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitfield.h> 12 #include <linux/extable.h> 13 #include <linux/signal.h> 14 #include <linux/mm.h> 15 #include <linux/hardirq.h> 16 #include <linux/init.h> 17 #include <linux/kprobes.h> 18 #include <linux/uaccess.h> 19 #include <linux/page-flags.h> 20 #include <linux/sched/signal.h> 21 #include <linux/sched/debug.h> 22 #include <linux/highmem.h> 23 #include <linux/perf_event.h> 24 #include <linux/preempt.h> 25 #include <linux/hugetlb.h> 26 27 #include <asm/acpi.h> 28 #include <asm/bug.h> 29 #include <asm/cmpxchg.h> 30 #include <asm/cpufeature.h> 31 #include <asm/exception.h> 32 #include <asm/daifflags.h> 33 #include <asm/debug-monitors.h> 34 #include <asm/esr.h> 35 #include <asm/kasan.h> 36 #include <asm/sysreg.h> 37 #include <asm/system_misc.h> 38 #include <asm/pgtable.h> 39 #include <asm/tlbflush.h> 40 #include <asm/traps.h> 41 42 struct fault_info { 43 int (*fn)(unsigned long addr, unsigned int esr, 44 struct pt_regs *regs); 45 int sig; 46 int code; 47 const char *name; 48 }; 49 50 static const struct fault_info fault_info[]; 51 static struct fault_info debug_fault_info[]; 52 53 static inline const struct fault_info *esr_to_fault_info(unsigned int esr) 54 { 55 return fault_info + (esr & ESR_ELx_FSC); 56 } 57 58 static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr) 59 { 60 return debug_fault_info + DBG_ESR_EVT(esr); 61 } 62 63 static void data_abort_decode(unsigned int esr) 64 { 65 pr_alert("Data abort info:\n"); 66 67 if (esr & ESR_ELx_ISV) { 68 pr_alert(" Access size = %u byte(s)\n", 69 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); 70 pr_alert(" SSE = %lu, SRT = %lu\n", 71 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, 72 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); 73 pr_alert(" SF = %lu, AR = %lu\n", 74 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, 75 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); 76 } else { 77 pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK); 78 } 79 80 pr_alert(" CM = %lu, WnR = %lu\n", 81 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, 82 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT); 83 } 84 85 static void mem_abort_decode(unsigned int esr) 86 { 87 pr_alert("Mem abort info:\n"); 88 89 pr_alert(" ESR = 0x%08x\n", esr); 90 pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n", 91 ESR_ELx_EC(esr), esr_get_class_string(esr), 92 (esr & ESR_ELx_IL) ? 32 : 16); 93 pr_alert(" SET = %lu, FnV = %lu\n", 94 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, 95 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); 96 pr_alert(" EA = %lu, S1PTW = %lu\n", 97 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, 98 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); 99 100 if (esr_is_data_abort(esr)) 101 data_abort_decode(esr); 102 } 103 104 static inline bool is_ttbr0_addr(unsigned long addr) 105 { 106 /* entry assembly clears tags for TTBR0 addrs */ 107 return addr < TASK_SIZE; 108 } 109 110 static inline bool is_ttbr1_addr(unsigned long addr) 111 { 112 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */ 113 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET; 114 } 115 116 /* 117 * Dump out the page tables associated with 'addr' in the currently active mm. 118 */ 119 static void show_pte(unsigned long addr) 120 { 121 struct mm_struct *mm; 122 pgd_t *pgdp; 123 pgd_t pgd; 124 125 if (is_ttbr0_addr(addr)) { 126 /* TTBR0 */ 127 mm = current->active_mm; 128 if (mm == &init_mm) { 129 pr_alert("[%016lx] user address but active_mm is swapper\n", 130 addr); 131 return; 132 } 133 } else if (is_ttbr1_addr(addr)) { 134 /* TTBR1 */ 135 mm = &init_mm; 136 } else { 137 pr_alert("[%016lx] address between user and kernel address ranges\n", 138 addr); 139 return; 140 } 141 142 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n", 143 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, 144 vabits_actual, (unsigned long)virt_to_phys(mm->pgd)); 145 pgdp = pgd_offset(mm, addr); 146 pgd = READ_ONCE(*pgdp); 147 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); 148 149 do { 150 pud_t *pudp, pud; 151 pmd_t *pmdp, pmd; 152 pte_t *ptep, pte; 153 154 if (pgd_none(pgd) || pgd_bad(pgd)) 155 break; 156 157 pudp = pud_offset(pgdp, addr); 158 pud = READ_ONCE(*pudp); 159 pr_cont(", pud=%016llx", pud_val(pud)); 160 if (pud_none(pud) || pud_bad(pud)) 161 break; 162 163 pmdp = pmd_offset(pudp, addr); 164 pmd = READ_ONCE(*pmdp); 165 pr_cont(", pmd=%016llx", pmd_val(pmd)); 166 if (pmd_none(pmd) || pmd_bad(pmd)) 167 break; 168 169 ptep = pte_offset_map(pmdp, addr); 170 pte = READ_ONCE(*ptep); 171 pr_cont(", pte=%016llx", pte_val(pte)); 172 pte_unmap(ptep); 173 } while(0); 174 175 pr_cont("\n"); 176 } 177 178 /* 179 * This function sets the access flags (dirty, accessed), as well as write 180 * permission, and only to a more permissive setting. 181 * 182 * It needs to cope with hardware update of the accessed/dirty state by other 183 * agents in the system and can safely skip the __sync_icache_dcache() call as, 184 * like set_pte_at(), the PTE is never changed from no-exec to exec here. 185 * 186 * Returns whether or not the PTE actually changed. 187 */ 188 int ptep_set_access_flags(struct vm_area_struct *vma, 189 unsigned long address, pte_t *ptep, 190 pte_t entry, int dirty) 191 { 192 pteval_t old_pteval, pteval; 193 pte_t pte = READ_ONCE(*ptep); 194 195 if (pte_same(pte, entry)) 196 return 0; 197 198 /* only preserve the access flags and write permission */ 199 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; 200 201 /* 202 * Setting the flags must be done atomically to avoid racing with the 203 * hardware update of the access/dirty state. The PTE_RDONLY bit must 204 * be set to the most permissive (lowest value) of *ptep and entry 205 * (calculated as: a & b == ~(~a | ~b)). 206 */ 207 pte_val(entry) ^= PTE_RDONLY; 208 pteval = pte_val(pte); 209 do { 210 old_pteval = pteval; 211 pteval ^= PTE_RDONLY; 212 pteval |= pte_val(entry); 213 pteval ^= PTE_RDONLY; 214 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); 215 } while (pteval != old_pteval); 216 217 flush_tlb_fix_spurious_fault(vma, address); 218 return 1; 219 } 220 221 static bool is_el1_instruction_abort(unsigned int esr) 222 { 223 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; 224 } 225 226 static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr, 227 struct pt_regs *regs) 228 { 229 unsigned int ec = ESR_ELx_EC(esr); 230 unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; 231 232 if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR) 233 return false; 234 235 if (fsc_type == ESR_ELx_FSC_PERM) 236 return true; 237 238 if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan()) 239 return fsc_type == ESR_ELx_FSC_FAULT && 240 (regs->pstate & PSR_PAN_BIT); 241 242 return false; 243 } 244 245 static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr, 246 unsigned int esr, 247 struct pt_regs *regs) 248 { 249 unsigned long flags; 250 u64 par, dfsc; 251 252 if (ESR_ELx_EC(esr) != ESR_ELx_EC_DABT_CUR || 253 (esr & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT) 254 return false; 255 256 local_irq_save(flags); 257 asm volatile("at s1e1r, %0" :: "r" (addr)); 258 isb(); 259 par = read_sysreg(par_el1); 260 local_irq_restore(flags); 261 262 if (!(par & SYS_PAR_EL1_F)) 263 return false; 264 265 /* 266 * If we got a different type of fault from the AT instruction, 267 * treat the translation fault as spurious. 268 */ 269 dfsc = FIELD_PREP(SYS_PAR_EL1_FST, par); 270 return (dfsc & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT; 271 } 272 273 static void die_kernel_fault(const char *msg, unsigned long addr, 274 unsigned int esr, struct pt_regs *regs) 275 { 276 bust_spinlocks(1); 277 278 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, 279 addr); 280 281 mem_abort_decode(esr); 282 283 show_pte(addr); 284 die("Oops", regs, esr); 285 bust_spinlocks(0); 286 do_exit(SIGKILL); 287 } 288 289 static void __do_kernel_fault(unsigned long addr, unsigned int esr, 290 struct pt_regs *regs) 291 { 292 const char *msg; 293 294 /* 295 * Are we prepared to handle this kernel fault? 296 * We are almost certainly not prepared to handle instruction faults. 297 */ 298 if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) 299 return; 300 301 if (WARN_RATELIMIT(is_spurious_el1_translation_fault(addr, esr, regs), 302 "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr)) 303 return; 304 305 if (is_el1_permission_fault(addr, esr, regs)) { 306 if (esr & ESR_ELx_WNR) 307 msg = "write to read-only memory"; 308 else 309 msg = "read from unreadable memory"; 310 } else if (addr < PAGE_SIZE) { 311 msg = "NULL pointer dereference"; 312 } else { 313 msg = "paging request"; 314 } 315 316 die_kernel_fault(msg, addr, esr, regs); 317 } 318 319 static void set_thread_esr(unsigned long address, unsigned int esr) 320 { 321 current->thread.fault_address = address; 322 323 /* 324 * If the faulting address is in the kernel, we must sanitize the ESR. 325 * From userspace's point of view, kernel-only mappings don't exist 326 * at all, so we report them as level 0 translation faults. 327 * (This is not quite the way that "no mapping there at all" behaves: 328 * an alignment fault not caused by the memory type would take 329 * precedence over translation fault for a real access to empty 330 * space. Unfortunately we can't easily distinguish "alignment fault 331 * not caused by memory type" from "alignment fault caused by memory 332 * type", so we ignore this wrinkle and just return the translation 333 * fault.) 334 */ 335 if (!is_ttbr0_addr(current->thread.fault_address)) { 336 switch (ESR_ELx_EC(esr)) { 337 case ESR_ELx_EC_DABT_LOW: 338 /* 339 * These bits provide only information about the 340 * faulting instruction, which userspace knows already. 341 * We explicitly clear bits which are architecturally 342 * RES0 in case they are given meanings in future. 343 * We always report the ESR as if the fault was taken 344 * to EL1 and so ISV and the bits in ISS[23:14] are 345 * clear. (In fact it always will be a fault to EL1.) 346 */ 347 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | 348 ESR_ELx_CM | ESR_ELx_WNR; 349 esr |= ESR_ELx_FSC_FAULT; 350 break; 351 case ESR_ELx_EC_IABT_LOW: 352 /* 353 * Claim a level 0 translation fault. 354 * All other bits are architecturally RES0 for faults 355 * reported with that DFSC value, so we clear them. 356 */ 357 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; 358 esr |= ESR_ELx_FSC_FAULT; 359 break; 360 default: 361 /* 362 * This should never happen (entry.S only brings us 363 * into this code for insn and data aborts from a lower 364 * exception level). Fail safe by not providing an ESR 365 * context record at all. 366 */ 367 WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr); 368 esr = 0; 369 break; 370 } 371 } 372 373 current->thread.fault_code = esr; 374 } 375 376 static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs) 377 { 378 /* 379 * If we are in kernel mode at this point, we have no context to 380 * handle this fault with. 381 */ 382 if (user_mode(regs)) { 383 const struct fault_info *inf = esr_to_fault_info(esr); 384 385 set_thread_esr(addr, esr); 386 arm64_force_sig_fault(inf->sig, inf->code, (void __user *)addr, 387 inf->name); 388 } else { 389 __do_kernel_fault(addr, esr, regs); 390 } 391 } 392 393 #define VM_FAULT_BADMAP 0x010000 394 #define VM_FAULT_BADACCESS 0x020000 395 396 static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr, 397 unsigned int mm_flags, unsigned long vm_flags) 398 { 399 struct vm_area_struct *vma = find_vma(mm, addr); 400 401 if (unlikely(!vma)) 402 return VM_FAULT_BADMAP; 403 404 /* 405 * Ok, we have a good vm_area for this memory access, so we can handle 406 * it. 407 */ 408 if (unlikely(vma->vm_start > addr)) { 409 if (!(vma->vm_flags & VM_GROWSDOWN)) 410 return VM_FAULT_BADMAP; 411 if (expand_stack(vma, addr)) 412 return VM_FAULT_BADMAP; 413 } 414 415 /* 416 * Check that the permissions on the VMA allow for the fault which 417 * occurred. 418 */ 419 if (!(vma->vm_flags & vm_flags)) 420 return VM_FAULT_BADACCESS; 421 return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags); 422 } 423 424 static bool is_el0_instruction_abort(unsigned int esr) 425 { 426 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; 427 } 428 429 /* 430 * Note: not valid for EL1 DC IVAC, but we never use that such that it 431 * should fault. EL0 cannot issue DC IVAC (undef). 432 */ 433 static bool is_write_abort(unsigned int esr) 434 { 435 return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM); 436 } 437 438 static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, 439 struct pt_regs *regs) 440 { 441 const struct fault_info *inf; 442 struct mm_struct *mm = current->mm; 443 vm_fault_t fault, major = 0; 444 unsigned long vm_flags = VM_READ | VM_WRITE; 445 unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; 446 447 if (kprobe_page_fault(regs, esr)) 448 return 0; 449 450 /* 451 * If we're in an interrupt or have no user context, we must not take 452 * the fault. 453 */ 454 if (faulthandler_disabled() || !mm) 455 goto no_context; 456 457 if (user_mode(regs)) 458 mm_flags |= FAULT_FLAG_USER; 459 460 if (is_el0_instruction_abort(esr)) { 461 vm_flags = VM_EXEC; 462 mm_flags |= FAULT_FLAG_INSTRUCTION; 463 } else if (is_write_abort(esr)) { 464 vm_flags = VM_WRITE; 465 mm_flags |= FAULT_FLAG_WRITE; 466 } 467 468 if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { 469 /* regs->orig_addr_limit may be 0 if we entered from EL0 */ 470 if (regs->orig_addr_limit == KERNEL_DS) 471 die_kernel_fault("access to user memory with fs=KERNEL_DS", 472 addr, esr, regs); 473 474 if (is_el1_instruction_abort(esr)) 475 die_kernel_fault("execution of user memory", 476 addr, esr, regs); 477 478 if (!search_exception_tables(regs->pc)) 479 die_kernel_fault("access to user memory outside uaccess routines", 480 addr, esr, regs); 481 } 482 483 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); 484 485 /* 486 * As per x86, we may deadlock here. However, since the kernel only 487 * validly references user space from well defined areas of the code, 488 * we can bug out early if this is from code which shouldn't. 489 */ 490 if (!down_read_trylock(&mm->mmap_sem)) { 491 if (!user_mode(regs) && !search_exception_tables(regs->pc)) 492 goto no_context; 493 retry: 494 down_read(&mm->mmap_sem); 495 } else { 496 /* 497 * The above down_read_trylock() might have succeeded in which 498 * case, we'll have missed the might_sleep() from down_read(). 499 */ 500 might_sleep(); 501 #ifdef CONFIG_DEBUG_VM 502 if (!user_mode(regs) && !search_exception_tables(regs->pc)) { 503 up_read(&mm->mmap_sem); 504 goto no_context; 505 } 506 #endif 507 } 508 509 fault = __do_page_fault(mm, addr, mm_flags, vm_flags); 510 major |= fault & VM_FAULT_MAJOR; 511 512 if (fault & VM_FAULT_RETRY) { 513 /* 514 * If we need to retry but a fatal signal is pending, 515 * handle the signal first. We do not need to release 516 * the mmap_sem because it would already be released 517 * in __lock_page_or_retry in mm/filemap.c. 518 */ 519 if (fatal_signal_pending(current)) { 520 if (!user_mode(regs)) 521 goto no_context; 522 return 0; 523 } 524 525 /* 526 * Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk of 527 * starvation. 528 */ 529 if (mm_flags & FAULT_FLAG_ALLOW_RETRY) { 530 mm_flags &= ~FAULT_FLAG_ALLOW_RETRY; 531 mm_flags |= FAULT_FLAG_TRIED; 532 goto retry; 533 } 534 } 535 up_read(&mm->mmap_sem); 536 537 /* 538 * Handle the "normal" (no error) case first. 539 */ 540 if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP | 541 VM_FAULT_BADACCESS)))) { 542 /* 543 * Major/minor page fault accounting is only done 544 * once. If we go through a retry, it is extremely 545 * likely that the page will be found in page cache at 546 * that point. 547 */ 548 if (major) { 549 current->maj_flt++; 550 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, 551 addr); 552 } else { 553 current->min_flt++; 554 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, 555 addr); 556 } 557 558 return 0; 559 } 560 561 /* 562 * If we are in kernel mode at this point, we have no context to 563 * handle this fault with. 564 */ 565 if (!user_mode(regs)) 566 goto no_context; 567 568 if (fault & VM_FAULT_OOM) { 569 /* 570 * We ran out of memory, call the OOM killer, and return to 571 * userspace (which will retry the fault, or kill us if we got 572 * oom-killed). 573 */ 574 pagefault_out_of_memory(); 575 return 0; 576 } 577 578 inf = esr_to_fault_info(esr); 579 set_thread_esr(addr, esr); 580 if (fault & VM_FAULT_SIGBUS) { 581 /* 582 * We had some memory, but were unable to successfully fix up 583 * this page fault. 584 */ 585 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)addr, 586 inf->name); 587 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { 588 unsigned int lsb; 589 590 lsb = PAGE_SHIFT; 591 if (fault & VM_FAULT_HWPOISON_LARGE) 592 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); 593 594 arm64_force_sig_mceerr(BUS_MCEERR_AR, (void __user *)addr, lsb, 595 inf->name); 596 } else { 597 /* 598 * Something tried to access memory that isn't in our memory 599 * map. 600 */ 601 arm64_force_sig_fault(SIGSEGV, 602 fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR, 603 (void __user *)addr, 604 inf->name); 605 } 606 607 return 0; 608 609 no_context: 610 __do_kernel_fault(addr, esr, regs); 611 return 0; 612 } 613 614 static int __kprobes do_translation_fault(unsigned long addr, 615 unsigned int esr, 616 struct pt_regs *regs) 617 { 618 if (is_ttbr0_addr(addr)) 619 return do_page_fault(addr, esr, regs); 620 621 do_bad_area(addr, esr, regs); 622 return 0; 623 } 624 625 static int do_alignment_fault(unsigned long addr, unsigned int esr, 626 struct pt_regs *regs) 627 { 628 do_bad_area(addr, esr, regs); 629 return 0; 630 } 631 632 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) 633 { 634 return 1; /* "fault" */ 635 } 636 637 static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) 638 { 639 const struct fault_info *inf; 640 void __user *siaddr; 641 642 inf = esr_to_fault_info(esr); 643 644 /* 645 * Return value ignored as we rely on signal merging. 646 * Future patches will make this more robust. 647 */ 648 apei_claim_sea(regs); 649 650 if (esr & ESR_ELx_FnV) 651 siaddr = NULL; 652 else 653 siaddr = (void __user *)addr; 654 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); 655 656 return 0; 657 } 658 659 static const struct fault_info fault_info[] = { 660 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, 661 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, 662 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, 663 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, 664 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, 665 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, 666 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, 667 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, 668 { do_bad, SIGKILL, SI_KERNEL, "unknown 8" }, 669 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, 670 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, 671 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, 672 { do_bad, SIGKILL, SI_KERNEL, "unknown 12" }, 673 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, 674 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, 675 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, 676 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, 677 { do_bad, SIGKILL, SI_KERNEL, "unknown 17" }, 678 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, 679 { do_bad, SIGKILL, SI_KERNEL, "unknown 19" }, 680 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, 681 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, 682 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, 683 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, 684 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented 685 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, 686 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, 687 { do_bad, SIGKILL, SI_KERNEL, "unknown 27" }, 688 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 689 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 690 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 691 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 692 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, 693 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, 694 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, 695 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, 696 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, 697 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, 698 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, 699 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, 700 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, 701 { do_bad, SIGKILL, SI_KERNEL, "unknown 41" }, 702 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, 703 { do_bad, SIGKILL, SI_KERNEL, "unknown 43" }, 704 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, 705 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, 706 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, 707 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, 708 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, 709 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, 710 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, 711 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, 712 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, 713 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, 714 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, 715 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, 716 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, 717 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, 718 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, 719 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, 720 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, 721 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, 722 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, 723 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, 724 }; 725 726 asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, 727 struct pt_regs *regs) 728 { 729 const struct fault_info *inf = esr_to_fault_info(esr); 730 731 if (!inf->fn(addr, esr, regs)) 732 return; 733 734 if (!user_mode(regs)) { 735 pr_alert("Unhandled fault at 0x%016lx\n", addr); 736 mem_abort_decode(esr); 737 show_pte(addr); 738 } 739 740 arm64_notify_die(inf->name, regs, 741 inf->sig, inf->code, (void __user *)addr, esr); 742 } 743 744 asmlinkage void __exception do_el0_irq_bp_hardening(void) 745 { 746 /* PC has already been checked in entry.S */ 747 arm64_apply_bp_hardening(); 748 } 749 750 asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, 751 unsigned int esr, 752 struct pt_regs *regs) 753 { 754 /* 755 * We've taken an instruction abort from userspace and not yet 756 * re-enabled IRQs. If the address is a kernel address, apply 757 * BP hardening prior to enabling IRQs and pre-emption. 758 */ 759 if (!is_ttbr0_addr(addr)) 760 arm64_apply_bp_hardening(); 761 762 local_daif_restore(DAIF_PROCCTX); 763 do_mem_abort(addr, esr, regs); 764 } 765 766 767 asmlinkage void __exception do_sp_pc_abort(unsigned long addr, 768 unsigned int esr, 769 struct pt_regs *regs) 770 { 771 if (user_mode(regs)) { 772 if (!is_ttbr0_addr(instruction_pointer(regs))) 773 arm64_apply_bp_hardening(); 774 local_daif_restore(DAIF_PROCCTX); 775 } 776 777 arm64_notify_die("SP/PC alignment exception", regs, 778 SIGBUS, BUS_ADRALN, (void __user *)addr, esr); 779 } 780 781 int __init early_brk64(unsigned long addr, unsigned int esr, 782 struct pt_regs *regs); 783 784 /* 785 * __refdata because early_brk64 is __init, but the reference to it is 786 * clobbered at arch_initcall time. 787 * See traps.c and debug-monitors.c:debug_traps_init(). 788 */ 789 static struct fault_info __refdata debug_fault_info[] = { 790 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" }, 791 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" }, 792 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" }, 793 { do_bad, SIGKILL, SI_KERNEL, "unknown 3" }, 794 { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" }, 795 { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" }, 796 { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" }, 797 { do_bad, SIGKILL, SI_KERNEL, "unknown 7" }, 798 }; 799 800 void __init hook_debug_fault_code(int nr, 801 int (*fn)(unsigned long, unsigned int, struct pt_regs *), 802 int sig, int code, const char *name) 803 { 804 BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info)); 805 806 debug_fault_info[nr].fn = fn; 807 debug_fault_info[nr].sig = sig; 808 debug_fault_info[nr].code = code; 809 debug_fault_info[nr].name = name; 810 } 811 812 /* 813 * In debug exception context, we explicitly disable preemption despite 814 * having interrupts disabled. 815 * This serves two purposes: it makes it much less likely that we would 816 * accidentally schedule in exception context and it will force a warning 817 * if we somehow manage to schedule by accident. 818 */ 819 static void debug_exception_enter(struct pt_regs *regs) 820 { 821 /* 822 * Tell lockdep we disabled irqs in entry.S. Do nothing if they were 823 * already disabled to preserve the last enabled/disabled addresses. 824 */ 825 if (interrupts_enabled(regs)) 826 trace_hardirqs_off(); 827 828 if (user_mode(regs)) { 829 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); 830 } else { 831 /* 832 * We might have interrupted pretty much anything. In 833 * fact, if we're a debug exception, we can even interrupt 834 * NMI processing. We don't want this code makes in_nmi() 835 * to return true, but we need to notify RCU. 836 */ 837 rcu_nmi_enter(); 838 } 839 840 preempt_disable(); 841 842 /* This code is a bit fragile. Test it. */ 843 RCU_LOCKDEP_WARN(!rcu_is_watching(), "exception_enter didn't work"); 844 } 845 NOKPROBE_SYMBOL(debug_exception_enter); 846 847 static void debug_exception_exit(struct pt_regs *regs) 848 { 849 preempt_enable_no_resched(); 850 851 if (!user_mode(regs)) 852 rcu_nmi_exit(); 853 854 if (interrupts_enabled(regs)) 855 trace_hardirqs_on(); 856 } 857 NOKPROBE_SYMBOL(debug_exception_exit); 858 859 #ifdef CONFIG_ARM64_ERRATUM_1463225 860 DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); 861 862 static int __exception 863 cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) 864 { 865 if (user_mode(regs)) 866 return 0; 867 868 if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa)) 869 return 0; 870 871 /* 872 * We've taken a dummy step exception from the kernel to ensure 873 * that interrupts are re-enabled on the syscall path. Return back 874 * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions 875 * masked so that we can safely restore the mdscr and get on with 876 * handling the syscall. 877 */ 878 regs->pstate |= PSR_D_BIT; 879 return 1; 880 } 881 #else 882 static int __exception 883 cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) 884 { 885 return 0; 886 } 887 #endif /* CONFIG_ARM64_ERRATUM_1463225 */ 888 889 asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint, 890 unsigned int esr, 891 struct pt_regs *regs) 892 { 893 const struct fault_info *inf = esr_to_debug_fault_info(esr); 894 unsigned long pc = instruction_pointer(regs); 895 896 if (cortex_a76_erratum_1463225_debug_handler(regs)) 897 return; 898 899 debug_exception_enter(regs); 900 901 if (user_mode(regs) && !is_ttbr0_addr(pc)) 902 arm64_apply_bp_hardening(); 903 904 if (inf->fn(addr_if_watchpoint, esr, regs)) { 905 arm64_notify_die(inf->name, regs, 906 inf->sig, inf->code, (void __user *)pc, esr); 907 } 908 909 debug_exception_exit(regs); 910 } 911 NOKPROBE_SYMBOL(do_debug_exception); 912