xref: /openbmc/linux/arch/arm64/mm/fault.c (revision 5b4cb650)
1 /*
2  * Based on arch/arm/mm/fault.c
3  *
4  * Copyright (C) 1995  Linus Torvalds
5  * Copyright (C) 1995-2004 Russell King
6  * Copyright (C) 2012 ARM Ltd.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include <linux/extable.h>
22 #include <linux/signal.h>
23 #include <linux/mm.h>
24 #include <linux/hardirq.h>
25 #include <linux/init.h>
26 #include <linux/kprobes.h>
27 #include <linux/uaccess.h>
28 #include <linux/page-flags.h>
29 #include <linux/sched/signal.h>
30 #include <linux/sched/debug.h>
31 #include <linux/highmem.h>
32 #include <linux/perf_event.h>
33 #include <linux/preempt.h>
34 #include <linux/hugetlb.h>
35 
36 #include <asm/bug.h>
37 #include <asm/cmpxchg.h>
38 #include <asm/cpufeature.h>
39 #include <asm/exception.h>
40 #include <asm/daifflags.h>
41 #include <asm/debug-monitors.h>
42 #include <asm/esr.h>
43 #include <asm/kasan.h>
44 #include <asm/sysreg.h>
45 #include <asm/system_misc.h>
46 #include <asm/pgtable.h>
47 #include <asm/tlbflush.h>
48 #include <asm/traps.h>
49 
50 #include <acpi/ghes.h>
51 
52 struct fault_info {
53 	int	(*fn)(unsigned long addr, unsigned int esr,
54 		      struct pt_regs *regs);
55 	int	sig;
56 	int	code;
57 	const char *name;
58 };
59 
60 static const struct fault_info fault_info[];
61 static struct fault_info debug_fault_info[];
62 
63 static inline const struct fault_info *esr_to_fault_info(unsigned int esr)
64 {
65 	return fault_info + (esr & ESR_ELx_FSC);
66 }
67 
68 static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr)
69 {
70 	return debug_fault_info + DBG_ESR_EVT(esr);
71 }
72 
73 #ifdef CONFIG_KPROBES
74 static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr)
75 {
76 	int ret = 0;
77 
78 	/* kprobe_running() needs smp_processor_id() */
79 	if (!user_mode(regs)) {
80 		preempt_disable();
81 		if (kprobe_running() && kprobe_fault_handler(regs, esr))
82 			ret = 1;
83 		preempt_enable();
84 	}
85 
86 	return ret;
87 }
88 #else
89 static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr)
90 {
91 	return 0;
92 }
93 #endif
94 
95 static void data_abort_decode(unsigned int esr)
96 {
97 	pr_alert("Data abort info:\n");
98 
99 	if (esr & ESR_ELx_ISV) {
100 		pr_alert("  Access size = %u byte(s)\n",
101 			 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT));
102 		pr_alert("  SSE = %lu, SRT = %lu\n",
103 			 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT,
104 			 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT);
105 		pr_alert("  SF = %lu, AR = %lu\n",
106 			 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
107 			 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
108 	} else {
109 		pr_alert("  ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK);
110 	}
111 
112 	pr_alert("  CM = %lu, WnR = %lu\n",
113 		 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT,
114 		 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT);
115 }
116 
117 static void mem_abort_decode(unsigned int esr)
118 {
119 	pr_alert("Mem abort info:\n");
120 
121 	pr_alert("  ESR = 0x%08x\n", esr);
122 	pr_alert("  Exception class = %s, IL = %u bits\n",
123 		 esr_get_class_string(esr),
124 		 (esr & ESR_ELx_IL) ? 32 : 16);
125 	pr_alert("  SET = %lu, FnV = %lu\n",
126 		 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT,
127 		 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT);
128 	pr_alert("  EA = %lu, S1PTW = %lu\n",
129 		 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT,
130 		 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT);
131 
132 	if (esr_is_data_abort(esr))
133 		data_abort_decode(esr);
134 }
135 
136 static inline bool is_ttbr0_addr(unsigned long addr)
137 {
138 	/* entry assembly clears tags for TTBR0 addrs */
139 	return addr < TASK_SIZE;
140 }
141 
142 static inline bool is_ttbr1_addr(unsigned long addr)
143 {
144 	/* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */
145 	return arch_kasan_reset_tag(addr) >= VA_START;
146 }
147 
148 /*
149  * Dump out the page tables associated with 'addr' in the currently active mm.
150  */
151 void show_pte(unsigned long addr)
152 {
153 	struct mm_struct *mm;
154 	pgd_t *pgdp;
155 	pgd_t pgd;
156 
157 	if (is_ttbr0_addr(addr)) {
158 		/* TTBR0 */
159 		mm = current->active_mm;
160 		if (mm == &init_mm) {
161 			pr_alert("[%016lx] user address but active_mm is swapper\n",
162 				 addr);
163 			return;
164 		}
165 	} else if (is_ttbr1_addr(addr)) {
166 		/* TTBR1 */
167 		mm = &init_mm;
168 	} else {
169 		pr_alert("[%016lx] address between user and kernel address ranges\n",
170 			 addr);
171 		return;
172 	}
173 
174 	pr_alert("%s pgtable: %luk pages, %u-bit VAs, pgdp = %p\n",
175 		 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K,
176 		 mm == &init_mm ? VA_BITS : (int) vabits_user, mm->pgd);
177 	pgdp = pgd_offset(mm, addr);
178 	pgd = READ_ONCE(*pgdp);
179 	pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd));
180 
181 	do {
182 		pud_t *pudp, pud;
183 		pmd_t *pmdp, pmd;
184 		pte_t *ptep, pte;
185 
186 		if (pgd_none(pgd) || pgd_bad(pgd))
187 			break;
188 
189 		pudp = pud_offset(pgdp, addr);
190 		pud = READ_ONCE(*pudp);
191 		pr_cont(", pud=%016llx", pud_val(pud));
192 		if (pud_none(pud) || pud_bad(pud))
193 			break;
194 
195 		pmdp = pmd_offset(pudp, addr);
196 		pmd = READ_ONCE(*pmdp);
197 		pr_cont(", pmd=%016llx", pmd_val(pmd));
198 		if (pmd_none(pmd) || pmd_bad(pmd))
199 			break;
200 
201 		ptep = pte_offset_map(pmdp, addr);
202 		pte = READ_ONCE(*ptep);
203 		pr_cont(", pte=%016llx", pte_val(pte));
204 		pte_unmap(ptep);
205 	} while(0);
206 
207 	pr_cont("\n");
208 }
209 
210 /*
211  * This function sets the access flags (dirty, accessed), as well as write
212  * permission, and only to a more permissive setting.
213  *
214  * It needs to cope with hardware update of the accessed/dirty state by other
215  * agents in the system and can safely skip the __sync_icache_dcache() call as,
216  * like set_pte_at(), the PTE is never changed from no-exec to exec here.
217  *
218  * Returns whether or not the PTE actually changed.
219  */
220 int ptep_set_access_flags(struct vm_area_struct *vma,
221 			  unsigned long address, pte_t *ptep,
222 			  pte_t entry, int dirty)
223 {
224 	pteval_t old_pteval, pteval;
225 	pte_t pte = READ_ONCE(*ptep);
226 
227 	if (pte_same(pte, entry))
228 		return 0;
229 
230 	/* only preserve the access flags and write permission */
231 	pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY;
232 
233 	/*
234 	 * Setting the flags must be done atomically to avoid racing with the
235 	 * hardware update of the access/dirty state. The PTE_RDONLY bit must
236 	 * be set to the most permissive (lowest value) of *ptep and entry
237 	 * (calculated as: a & b == ~(~a | ~b)).
238 	 */
239 	pte_val(entry) ^= PTE_RDONLY;
240 	pteval = pte_val(pte);
241 	do {
242 		old_pteval = pteval;
243 		pteval ^= PTE_RDONLY;
244 		pteval |= pte_val(entry);
245 		pteval ^= PTE_RDONLY;
246 		pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval);
247 	} while (pteval != old_pteval);
248 
249 	flush_tlb_fix_spurious_fault(vma, address);
250 	return 1;
251 }
252 
253 static bool is_el1_instruction_abort(unsigned int esr)
254 {
255 	return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR;
256 }
257 
258 static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr,
259 					   struct pt_regs *regs)
260 {
261 	unsigned int ec       = ESR_ELx_EC(esr);
262 	unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE;
263 
264 	if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR)
265 		return false;
266 
267 	if (fsc_type == ESR_ELx_FSC_PERM)
268 		return true;
269 
270 	if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan())
271 		return fsc_type == ESR_ELx_FSC_FAULT &&
272 			(regs->pstate & PSR_PAN_BIT);
273 
274 	return false;
275 }
276 
277 static void die_kernel_fault(const char *msg, unsigned long addr,
278 			     unsigned int esr, struct pt_regs *regs)
279 {
280 	bust_spinlocks(1);
281 
282 	pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg,
283 		 addr);
284 
285 	mem_abort_decode(esr);
286 
287 	show_pte(addr);
288 	die("Oops", regs, esr);
289 	bust_spinlocks(0);
290 	do_exit(SIGKILL);
291 }
292 
293 static void __do_kernel_fault(unsigned long addr, unsigned int esr,
294 			      struct pt_regs *regs)
295 {
296 	const char *msg;
297 
298 	/*
299 	 * Are we prepared to handle this kernel fault?
300 	 * We are almost certainly not prepared to handle instruction faults.
301 	 */
302 	if (!is_el1_instruction_abort(esr) && fixup_exception(regs))
303 		return;
304 
305 	if (is_el1_permission_fault(addr, esr, regs)) {
306 		if (esr & ESR_ELx_WNR)
307 			msg = "write to read-only memory";
308 		else
309 			msg = "read from unreadable memory";
310 	} else if (addr < PAGE_SIZE) {
311 		msg = "NULL pointer dereference";
312 	} else {
313 		msg = "paging request";
314 	}
315 
316 	die_kernel_fault(msg, addr, esr, regs);
317 }
318 
319 static void set_thread_esr(unsigned long address, unsigned int esr)
320 {
321 	current->thread.fault_address = address;
322 
323 	/*
324 	 * If the faulting address is in the kernel, we must sanitize the ESR.
325 	 * From userspace's point of view, kernel-only mappings don't exist
326 	 * at all, so we report them as level 0 translation faults.
327 	 * (This is not quite the way that "no mapping there at all" behaves:
328 	 * an alignment fault not caused by the memory type would take
329 	 * precedence over translation fault for a real access to empty
330 	 * space. Unfortunately we can't easily distinguish "alignment fault
331 	 * not caused by memory type" from "alignment fault caused by memory
332 	 * type", so we ignore this wrinkle and just return the translation
333 	 * fault.)
334 	 */
335 	if (!is_ttbr0_addr(current->thread.fault_address)) {
336 		switch (ESR_ELx_EC(esr)) {
337 		case ESR_ELx_EC_DABT_LOW:
338 			/*
339 			 * These bits provide only information about the
340 			 * faulting instruction, which userspace knows already.
341 			 * We explicitly clear bits which are architecturally
342 			 * RES0 in case they are given meanings in future.
343 			 * We always report the ESR as if the fault was taken
344 			 * to EL1 and so ISV and the bits in ISS[23:14] are
345 			 * clear. (In fact it always will be a fault to EL1.)
346 			 */
347 			esr &= ESR_ELx_EC_MASK | ESR_ELx_IL |
348 				ESR_ELx_CM | ESR_ELx_WNR;
349 			esr |= ESR_ELx_FSC_FAULT;
350 			break;
351 		case ESR_ELx_EC_IABT_LOW:
352 			/*
353 			 * Claim a level 0 translation fault.
354 			 * All other bits are architecturally RES0 for faults
355 			 * reported with that DFSC value, so we clear them.
356 			 */
357 			esr &= ESR_ELx_EC_MASK | ESR_ELx_IL;
358 			esr |= ESR_ELx_FSC_FAULT;
359 			break;
360 		default:
361 			/*
362 			 * This should never happen (entry.S only brings us
363 			 * into this code for insn and data aborts from a lower
364 			 * exception level). Fail safe by not providing an ESR
365 			 * context record at all.
366 			 */
367 			WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr);
368 			esr = 0;
369 			break;
370 		}
371 	}
372 
373 	current->thread.fault_code = esr;
374 }
375 
376 static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs)
377 {
378 	/*
379 	 * If we are in kernel mode at this point, we have no context to
380 	 * handle this fault with.
381 	 */
382 	if (user_mode(regs)) {
383 		const struct fault_info *inf = esr_to_fault_info(esr);
384 
385 		set_thread_esr(addr, esr);
386 		arm64_force_sig_fault(inf->sig, inf->code, (void __user *)addr,
387 				      inf->name);
388 	} else {
389 		__do_kernel_fault(addr, esr, regs);
390 	}
391 }
392 
393 #define VM_FAULT_BADMAP		0x010000
394 #define VM_FAULT_BADACCESS	0x020000
395 
396 static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr,
397 			   unsigned int mm_flags, unsigned long vm_flags,
398 			   struct task_struct *tsk)
399 {
400 	struct vm_area_struct *vma;
401 	vm_fault_t fault;
402 
403 	vma = find_vma(mm, addr);
404 	fault = VM_FAULT_BADMAP;
405 	if (unlikely(!vma))
406 		goto out;
407 	if (unlikely(vma->vm_start > addr))
408 		goto check_stack;
409 
410 	/*
411 	 * Ok, we have a good vm_area for this memory access, so we can handle
412 	 * it.
413 	 */
414 good_area:
415 	/*
416 	 * Check that the permissions on the VMA allow for the fault which
417 	 * occurred.
418 	 */
419 	if (!(vma->vm_flags & vm_flags)) {
420 		fault = VM_FAULT_BADACCESS;
421 		goto out;
422 	}
423 
424 	return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags);
425 
426 check_stack:
427 	if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr))
428 		goto good_area;
429 out:
430 	return fault;
431 }
432 
433 static bool is_el0_instruction_abort(unsigned int esr)
434 {
435 	return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW;
436 }
437 
438 static int __kprobes do_page_fault(unsigned long addr, unsigned int esr,
439 				   struct pt_regs *regs)
440 {
441 	const struct fault_info *inf;
442 	struct task_struct *tsk;
443 	struct mm_struct *mm;
444 	vm_fault_t fault, major = 0;
445 	unsigned long vm_flags = VM_READ | VM_WRITE;
446 	unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
447 
448 	if (notify_page_fault(regs, esr))
449 		return 0;
450 
451 	tsk = current;
452 	mm  = tsk->mm;
453 
454 	/*
455 	 * If we're in an interrupt or have no user context, we must not take
456 	 * the fault.
457 	 */
458 	if (faulthandler_disabled() || !mm)
459 		goto no_context;
460 
461 	if (user_mode(regs))
462 		mm_flags |= FAULT_FLAG_USER;
463 
464 	if (is_el0_instruction_abort(esr)) {
465 		vm_flags = VM_EXEC;
466 	} else if ((esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM)) {
467 		vm_flags = VM_WRITE;
468 		mm_flags |= FAULT_FLAG_WRITE;
469 	}
470 
471 	if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) {
472 		/* regs->orig_addr_limit may be 0 if we entered from EL0 */
473 		if (regs->orig_addr_limit == KERNEL_DS)
474 			die_kernel_fault("access to user memory with fs=KERNEL_DS",
475 					 addr, esr, regs);
476 
477 		if (is_el1_instruction_abort(esr))
478 			die_kernel_fault("execution of user memory",
479 					 addr, esr, regs);
480 
481 		if (!search_exception_tables(regs->pc))
482 			die_kernel_fault("access to user memory outside uaccess routines",
483 					 addr, esr, regs);
484 	}
485 
486 	perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
487 
488 	/*
489 	 * As per x86, we may deadlock here. However, since the kernel only
490 	 * validly references user space from well defined areas of the code,
491 	 * we can bug out early if this is from code which shouldn't.
492 	 */
493 	if (!down_read_trylock(&mm->mmap_sem)) {
494 		if (!user_mode(regs) && !search_exception_tables(regs->pc))
495 			goto no_context;
496 retry:
497 		down_read(&mm->mmap_sem);
498 	} else {
499 		/*
500 		 * The above down_read_trylock() might have succeeded in which
501 		 * case, we'll have missed the might_sleep() from down_read().
502 		 */
503 		might_sleep();
504 #ifdef CONFIG_DEBUG_VM
505 		if (!user_mode(regs) && !search_exception_tables(regs->pc))
506 			goto no_context;
507 #endif
508 	}
509 
510 	fault = __do_page_fault(mm, addr, mm_flags, vm_flags, tsk);
511 	major |= fault & VM_FAULT_MAJOR;
512 
513 	if (fault & VM_FAULT_RETRY) {
514 		/*
515 		 * If we need to retry but a fatal signal is pending,
516 		 * handle the signal first. We do not need to release
517 		 * the mmap_sem because it would already be released
518 		 * in __lock_page_or_retry in mm/filemap.c.
519 		 */
520 		if (fatal_signal_pending(current)) {
521 			if (!user_mode(regs))
522 				goto no_context;
523 			return 0;
524 		}
525 
526 		/*
527 		 * Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk of
528 		 * starvation.
529 		 */
530 		if (mm_flags & FAULT_FLAG_ALLOW_RETRY) {
531 			mm_flags &= ~FAULT_FLAG_ALLOW_RETRY;
532 			mm_flags |= FAULT_FLAG_TRIED;
533 			goto retry;
534 		}
535 	}
536 	up_read(&mm->mmap_sem);
537 
538 	/*
539 	 * Handle the "normal" (no error) case first.
540 	 */
541 	if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP |
542 			      VM_FAULT_BADACCESS)))) {
543 		/*
544 		 * Major/minor page fault accounting is only done
545 		 * once. If we go through a retry, it is extremely
546 		 * likely that the page will be found in page cache at
547 		 * that point.
548 		 */
549 		if (major) {
550 			tsk->maj_flt++;
551 			perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs,
552 				      addr);
553 		} else {
554 			tsk->min_flt++;
555 			perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs,
556 				      addr);
557 		}
558 
559 		return 0;
560 	}
561 
562 	/*
563 	 * If we are in kernel mode at this point, we have no context to
564 	 * handle this fault with.
565 	 */
566 	if (!user_mode(regs))
567 		goto no_context;
568 
569 	if (fault & VM_FAULT_OOM) {
570 		/*
571 		 * We ran out of memory, call the OOM killer, and return to
572 		 * userspace (which will retry the fault, or kill us if we got
573 		 * oom-killed).
574 		 */
575 		pagefault_out_of_memory();
576 		return 0;
577 	}
578 
579 	inf = esr_to_fault_info(esr);
580 	set_thread_esr(addr, esr);
581 	if (fault & VM_FAULT_SIGBUS) {
582 		/*
583 		 * We had some memory, but were unable to successfully fix up
584 		 * this page fault.
585 		 */
586 		arm64_force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)addr,
587 				      inf->name);
588 	} else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) {
589 		unsigned int lsb;
590 
591 		lsb = PAGE_SHIFT;
592 		if (fault & VM_FAULT_HWPOISON_LARGE)
593 			lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
594 
595 		arm64_force_sig_mceerr(BUS_MCEERR_AR, (void __user *)addr, lsb,
596 				       inf->name);
597 	} else {
598 		/*
599 		 * Something tried to access memory that isn't in our memory
600 		 * map.
601 		 */
602 		arm64_force_sig_fault(SIGSEGV,
603 				      fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR,
604 				      (void __user *)addr,
605 				      inf->name);
606 	}
607 
608 	return 0;
609 
610 no_context:
611 	__do_kernel_fault(addr, esr, regs);
612 	return 0;
613 }
614 
615 static int __kprobes do_translation_fault(unsigned long addr,
616 					  unsigned int esr,
617 					  struct pt_regs *regs)
618 {
619 	if (is_ttbr0_addr(addr))
620 		return do_page_fault(addr, esr, regs);
621 
622 	do_bad_area(addr, esr, regs);
623 	return 0;
624 }
625 
626 static int do_alignment_fault(unsigned long addr, unsigned int esr,
627 			      struct pt_regs *regs)
628 {
629 	do_bad_area(addr, esr, regs);
630 	return 0;
631 }
632 
633 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
634 {
635 	return 1; /* "fault" */
636 }
637 
638 static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs)
639 {
640 	const struct fault_info *inf;
641 	void __user *siaddr;
642 
643 	inf = esr_to_fault_info(esr);
644 
645 	/*
646 	 * Synchronous aborts may interrupt code which had interrupts masked.
647 	 * Before calling out into the wider kernel tell the interested
648 	 * subsystems.
649 	 */
650 	if (IS_ENABLED(CONFIG_ACPI_APEI_SEA)) {
651 		if (interrupts_enabled(regs))
652 			nmi_enter();
653 
654 		ghes_notify_sea();
655 
656 		if (interrupts_enabled(regs))
657 			nmi_exit();
658 	}
659 
660 	if (esr & ESR_ELx_FnV)
661 		siaddr = NULL;
662 	else
663 		siaddr  = (void __user *)addr;
664 	arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr);
665 
666 	return 0;
667 }
668 
669 static const struct fault_info fault_info[] = {
670 	{ do_bad,		SIGKILL, SI_KERNEL,	"ttbr address size fault"	},
671 	{ do_bad,		SIGKILL, SI_KERNEL,	"level 1 address size fault"	},
672 	{ do_bad,		SIGKILL, SI_KERNEL,	"level 2 address size fault"	},
673 	{ do_bad,		SIGKILL, SI_KERNEL,	"level 3 address size fault"	},
674 	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 0 translation fault"	},
675 	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 1 translation fault"	},
676 	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 2 translation fault"	},
677 	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 3 translation fault"	},
678 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 8"			},
679 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 1 access flag fault"	},
680 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 access flag fault"	},
681 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 access flag fault"	},
682 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 12"			},
683 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 1 permission fault"	},
684 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 permission fault"	},
685 	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 permission fault"	},
686 	{ do_sea,		SIGBUS,  BUS_OBJERR,	"synchronous external abort"	},
687 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 17"			},
688 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 18"			},
689 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 19"			},
690 	{ do_sea,		SIGKILL, SI_KERNEL,	"level 0 (translation table walk)"	},
691 	{ do_sea,		SIGKILL, SI_KERNEL,	"level 1 (translation table walk)"	},
692 	{ do_sea,		SIGKILL, SI_KERNEL,	"level 2 (translation table walk)"	},
693 	{ do_sea,		SIGKILL, SI_KERNEL,	"level 3 (translation table walk)"	},
694 	{ do_sea,		SIGBUS,  BUS_OBJERR,	"synchronous parity or ECC error" },	// Reserved when RAS is implemented
695 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 25"			},
696 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 26"			},
697 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 27"			},
698 	{ do_sea,		SIGKILL, SI_KERNEL,	"level 0 synchronous parity error (translation table walk)"	},	// Reserved when RAS is implemented
699 	{ do_sea,		SIGKILL, SI_KERNEL,	"level 1 synchronous parity error (translation table walk)"	},	// Reserved when RAS is implemented
700 	{ do_sea,		SIGKILL, SI_KERNEL,	"level 2 synchronous parity error (translation table walk)"	},	// Reserved when RAS is implemented
701 	{ do_sea,		SIGKILL, SI_KERNEL,	"level 3 synchronous parity error (translation table walk)"	},	// Reserved when RAS is implemented
702 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 32"			},
703 	{ do_alignment_fault,	SIGBUS,  BUS_ADRALN,	"alignment fault"		},
704 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 34"			},
705 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 35"			},
706 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 36"			},
707 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 37"			},
708 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 38"			},
709 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 39"			},
710 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 40"			},
711 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 41"			},
712 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 42"			},
713 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 43"			},
714 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 44"			},
715 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 45"			},
716 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 46"			},
717 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 47"			},
718 	{ do_bad,		SIGKILL, SI_KERNEL,	"TLB conflict abort"		},
719 	{ do_bad,		SIGKILL, SI_KERNEL,	"Unsupported atomic hardware update fault"	},
720 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 50"			},
721 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 51"			},
722 	{ do_bad,		SIGKILL, SI_KERNEL,	"implementation fault (lockdown abort)" },
723 	{ do_bad,		SIGBUS,  BUS_OBJERR,	"implementation fault (unsupported exclusive)" },
724 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 54"			},
725 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 55"			},
726 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 56"			},
727 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 57"			},
728 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 58" 			},
729 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 59"			},
730 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 60"			},
731 	{ do_bad,		SIGKILL, SI_KERNEL,	"section domain fault"		},
732 	{ do_bad,		SIGKILL, SI_KERNEL,	"page domain fault"		},
733 	{ do_bad,		SIGKILL, SI_KERNEL,	"unknown 63"			},
734 };
735 
736 int handle_guest_sea(phys_addr_t addr, unsigned int esr)
737 {
738 	return ghes_notify_sea();
739 }
740 
741 asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr,
742 					 struct pt_regs *regs)
743 {
744 	const struct fault_info *inf = esr_to_fault_info(esr);
745 
746 	if (!inf->fn(addr, esr, regs))
747 		return;
748 
749 	if (!user_mode(regs)) {
750 		pr_alert("Unhandled fault at 0x%016lx\n", addr);
751 		mem_abort_decode(esr);
752 		show_pte(addr);
753 	}
754 
755 	arm64_notify_die(inf->name, regs,
756 			 inf->sig, inf->code, (void __user *)addr, esr);
757 }
758 
759 asmlinkage void __exception do_el0_irq_bp_hardening(void)
760 {
761 	/* PC has already been checked in entry.S */
762 	arm64_apply_bp_hardening();
763 }
764 
765 asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr,
766 						   unsigned int esr,
767 						   struct pt_regs *regs)
768 {
769 	/*
770 	 * We've taken an instruction abort from userspace and not yet
771 	 * re-enabled IRQs. If the address is a kernel address, apply
772 	 * BP hardening prior to enabling IRQs and pre-emption.
773 	 */
774 	if (!is_ttbr0_addr(addr))
775 		arm64_apply_bp_hardening();
776 
777 	local_daif_restore(DAIF_PROCCTX);
778 	do_mem_abort(addr, esr, regs);
779 }
780 
781 
782 asmlinkage void __exception do_sp_pc_abort(unsigned long addr,
783 					   unsigned int esr,
784 					   struct pt_regs *regs)
785 {
786 	if (user_mode(regs)) {
787 		if (!is_ttbr0_addr(instruction_pointer(regs)))
788 			arm64_apply_bp_hardening();
789 		local_daif_restore(DAIF_PROCCTX);
790 	}
791 
792 	arm64_notify_die("SP/PC alignment exception", regs,
793 			 SIGBUS, BUS_ADRALN, (void __user *)addr, esr);
794 }
795 
796 int __init early_brk64(unsigned long addr, unsigned int esr,
797 		       struct pt_regs *regs);
798 
799 /*
800  * __refdata because early_brk64 is __init, but the reference to it is
801  * clobbered at arch_initcall time.
802  * See traps.c and debug-monitors.c:debug_traps_init().
803  */
804 static struct fault_info __refdata debug_fault_info[] = {
805 	{ do_bad,	SIGTRAP,	TRAP_HWBKPT,	"hardware breakpoint"	},
806 	{ do_bad,	SIGTRAP,	TRAP_HWBKPT,	"hardware single-step"	},
807 	{ do_bad,	SIGTRAP,	TRAP_HWBKPT,	"hardware watchpoint"	},
808 	{ do_bad,	SIGKILL,	SI_KERNEL,	"unknown 3"		},
809 	{ do_bad,	SIGTRAP,	TRAP_BRKPT,	"aarch32 BKPT"		},
810 	{ do_bad,	SIGKILL,	SI_KERNEL,	"aarch32 vector catch"	},
811 	{ early_brk64,	SIGTRAP,	TRAP_BRKPT,	"aarch64 BRK"		},
812 	{ do_bad,	SIGKILL,	SI_KERNEL,	"unknown 7"		},
813 };
814 
815 void __init hook_debug_fault_code(int nr,
816 				  int (*fn)(unsigned long, unsigned int, struct pt_regs *),
817 				  int sig, int code, const char *name)
818 {
819 	BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info));
820 
821 	debug_fault_info[nr].fn		= fn;
822 	debug_fault_info[nr].sig	= sig;
823 	debug_fault_info[nr].code	= code;
824 	debug_fault_info[nr].name	= name;
825 }
826 
827 asmlinkage int __exception do_debug_exception(unsigned long addr,
828 					      unsigned int esr,
829 					      struct pt_regs *regs)
830 {
831 	const struct fault_info *inf = esr_to_debug_fault_info(esr);
832 	int rv;
833 
834 	/*
835 	 * Tell lockdep we disabled irqs in entry.S. Do nothing if they were
836 	 * already disabled to preserve the last enabled/disabled addresses.
837 	 */
838 	if (interrupts_enabled(regs))
839 		trace_hardirqs_off();
840 
841 	if (user_mode(regs) && !is_ttbr0_addr(instruction_pointer(regs)))
842 		arm64_apply_bp_hardening();
843 
844 	if (!inf->fn(addr, esr, regs)) {
845 		rv = 1;
846 	} else {
847 		arm64_notify_die(inf->name, regs,
848 				 inf->sig, inf->code, (void __user *)addr, esr);
849 		rv = 0;
850 	}
851 
852 	if (interrupts_enabled(regs))
853 		trace_hardirqs_on();
854 
855 	return rv;
856 }
857 NOKPROBE_SYMBOL(do_debug_exception);
858