1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/mm/fault.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Copyright (C) 1995-2004 Russell King 7 * Copyright (C) 2012 ARM Ltd. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitfield.h> 12 #include <linux/extable.h> 13 #include <linux/signal.h> 14 #include <linux/mm.h> 15 #include <linux/hardirq.h> 16 #include <linux/init.h> 17 #include <linux/kprobes.h> 18 #include <linux/uaccess.h> 19 #include <linux/page-flags.h> 20 #include <linux/sched/signal.h> 21 #include <linux/sched/debug.h> 22 #include <linux/highmem.h> 23 #include <linux/perf_event.h> 24 #include <linux/preempt.h> 25 #include <linux/hugetlb.h> 26 27 #include <asm/acpi.h> 28 #include <asm/bug.h> 29 #include <asm/cmpxchg.h> 30 #include <asm/cpufeature.h> 31 #include <asm/exception.h> 32 #include <asm/daifflags.h> 33 #include <asm/debug-monitors.h> 34 #include <asm/esr.h> 35 #include <asm/kprobes.h> 36 #include <asm/processor.h> 37 #include <asm/sysreg.h> 38 #include <asm/system_misc.h> 39 #include <asm/tlbflush.h> 40 #include <asm/traps.h> 41 42 struct fault_info { 43 int (*fn)(unsigned long addr, unsigned int esr, 44 struct pt_regs *regs); 45 int sig; 46 int code; 47 const char *name; 48 }; 49 50 static const struct fault_info fault_info[]; 51 static struct fault_info debug_fault_info[]; 52 53 static inline const struct fault_info *esr_to_fault_info(unsigned int esr) 54 { 55 return fault_info + (esr & ESR_ELx_FSC); 56 } 57 58 static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr) 59 { 60 return debug_fault_info + DBG_ESR_EVT(esr); 61 } 62 63 static void data_abort_decode(unsigned int esr) 64 { 65 pr_alert("Data abort info:\n"); 66 67 if (esr & ESR_ELx_ISV) { 68 pr_alert(" Access size = %u byte(s)\n", 69 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); 70 pr_alert(" SSE = %lu, SRT = %lu\n", 71 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, 72 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); 73 pr_alert(" SF = %lu, AR = %lu\n", 74 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, 75 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); 76 } else { 77 pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK); 78 } 79 80 pr_alert(" CM = %lu, WnR = %lu\n", 81 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, 82 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT); 83 } 84 85 static void mem_abort_decode(unsigned int esr) 86 { 87 pr_alert("Mem abort info:\n"); 88 89 pr_alert(" ESR = 0x%08x\n", esr); 90 pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n", 91 ESR_ELx_EC(esr), esr_get_class_string(esr), 92 (esr & ESR_ELx_IL) ? 32 : 16); 93 pr_alert(" SET = %lu, FnV = %lu\n", 94 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, 95 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); 96 pr_alert(" EA = %lu, S1PTW = %lu\n", 97 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, 98 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); 99 100 if (esr_is_data_abort(esr)) 101 data_abort_decode(esr); 102 } 103 104 static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm) 105 { 106 /* Either init_pg_dir or swapper_pg_dir */ 107 if (mm == &init_mm) 108 return __pa_symbol(mm->pgd); 109 110 return (unsigned long)virt_to_phys(mm->pgd); 111 } 112 113 /* 114 * Dump out the page tables associated with 'addr' in the currently active mm. 115 */ 116 static void show_pte(unsigned long addr) 117 { 118 struct mm_struct *mm; 119 pgd_t *pgdp; 120 pgd_t pgd; 121 122 if (is_ttbr0_addr(addr)) { 123 /* TTBR0 */ 124 mm = current->active_mm; 125 if (mm == &init_mm) { 126 pr_alert("[%016lx] user address but active_mm is swapper\n", 127 addr); 128 return; 129 } 130 } else if (is_ttbr1_addr(addr)) { 131 /* TTBR1 */ 132 mm = &init_mm; 133 } else { 134 pr_alert("[%016lx] address between user and kernel address ranges\n", 135 addr); 136 return; 137 } 138 139 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n", 140 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, 141 vabits_actual, mm_to_pgd_phys(mm)); 142 pgdp = pgd_offset(mm, addr); 143 pgd = READ_ONCE(*pgdp); 144 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); 145 146 do { 147 p4d_t *p4dp, p4d; 148 pud_t *pudp, pud; 149 pmd_t *pmdp, pmd; 150 pte_t *ptep, pte; 151 152 if (pgd_none(pgd) || pgd_bad(pgd)) 153 break; 154 155 p4dp = p4d_offset(pgdp, addr); 156 p4d = READ_ONCE(*p4dp); 157 pr_cont(", p4d=%016llx", p4d_val(p4d)); 158 if (p4d_none(p4d) || p4d_bad(p4d)) 159 break; 160 161 pudp = pud_offset(p4dp, addr); 162 pud = READ_ONCE(*pudp); 163 pr_cont(", pud=%016llx", pud_val(pud)); 164 if (pud_none(pud) || pud_bad(pud)) 165 break; 166 167 pmdp = pmd_offset(pudp, addr); 168 pmd = READ_ONCE(*pmdp); 169 pr_cont(", pmd=%016llx", pmd_val(pmd)); 170 if (pmd_none(pmd) || pmd_bad(pmd)) 171 break; 172 173 ptep = pte_offset_map(pmdp, addr); 174 pte = READ_ONCE(*ptep); 175 pr_cont(", pte=%016llx", pte_val(pte)); 176 pte_unmap(ptep); 177 } while(0); 178 179 pr_cont("\n"); 180 } 181 182 /* 183 * This function sets the access flags (dirty, accessed), as well as write 184 * permission, and only to a more permissive setting. 185 * 186 * It needs to cope with hardware update of the accessed/dirty state by other 187 * agents in the system and can safely skip the __sync_icache_dcache() call as, 188 * like set_pte_at(), the PTE is never changed from no-exec to exec here. 189 * 190 * Returns whether or not the PTE actually changed. 191 */ 192 int ptep_set_access_flags(struct vm_area_struct *vma, 193 unsigned long address, pte_t *ptep, 194 pte_t entry, int dirty) 195 { 196 pteval_t old_pteval, pteval; 197 pte_t pte = READ_ONCE(*ptep); 198 199 if (pte_same(pte, entry)) 200 return 0; 201 202 /* only preserve the access flags and write permission */ 203 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; 204 205 /* 206 * Setting the flags must be done atomically to avoid racing with the 207 * hardware update of the access/dirty state. The PTE_RDONLY bit must 208 * be set to the most permissive (lowest value) of *ptep and entry 209 * (calculated as: a & b == ~(~a | ~b)). 210 */ 211 pte_val(entry) ^= PTE_RDONLY; 212 pteval = pte_val(pte); 213 do { 214 old_pteval = pteval; 215 pteval ^= PTE_RDONLY; 216 pteval |= pte_val(entry); 217 pteval ^= PTE_RDONLY; 218 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); 219 } while (pteval != old_pteval); 220 221 flush_tlb_fix_spurious_fault(vma, address); 222 return 1; 223 } 224 225 static bool is_el1_instruction_abort(unsigned int esr) 226 { 227 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; 228 } 229 230 static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr, 231 struct pt_regs *regs) 232 { 233 unsigned int ec = ESR_ELx_EC(esr); 234 unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; 235 236 if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR) 237 return false; 238 239 if (fsc_type == ESR_ELx_FSC_PERM) 240 return true; 241 242 if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan()) 243 return fsc_type == ESR_ELx_FSC_FAULT && 244 (regs->pstate & PSR_PAN_BIT); 245 246 return false; 247 } 248 249 static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr, 250 unsigned int esr, 251 struct pt_regs *regs) 252 { 253 unsigned long flags; 254 u64 par, dfsc; 255 256 if (ESR_ELx_EC(esr) != ESR_ELx_EC_DABT_CUR || 257 (esr & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT) 258 return false; 259 260 local_irq_save(flags); 261 asm volatile("at s1e1r, %0" :: "r" (addr)); 262 isb(); 263 par = read_sysreg(par_el1); 264 local_irq_restore(flags); 265 266 /* 267 * If we now have a valid translation, treat the translation fault as 268 * spurious. 269 */ 270 if (!(par & SYS_PAR_EL1_F)) 271 return true; 272 273 /* 274 * If we got a different type of fault from the AT instruction, 275 * treat the translation fault as spurious. 276 */ 277 dfsc = FIELD_GET(SYS_PAR_EL1_FST, par); 278 return (dfsc & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT; 279 } 280 281 static void die_kernel_fault(const char *msg, unsigned long addr, 282 unsigned int esr, struct pt_regs *regs) 283 { 284 bust_spinlocks(1); 285 286 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, 287 addr); 288 289 mem_abort_decode(esr); 290 291 show_pte(addr); 292 die("Oops", regs, esr); 293 bust_spinlocks(0); 294 do_exit(SIGKILL); 295 } 296 297 static void __do_kernel_fault(unsigned long addr, unsigned int esr, 298 struct pt_regs *regs) 299 { 300 const char *msg; 301 302 /* 303 * Are we prepared to handle this kernel fault? 304 * We are almost certainly not prepared to handle instruction faults. 305 */ 306 if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) 307 return; 308 309 if (WARN_RATELIMIT(is_spurious_el1_translation_fault(addr, esr, regs), 310 "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr)) 311 return; 312 313 if (is_el1_permission_fault(addr, esr, regs)) { 314 if (esr & ESR_ELx_WNR) 315 msg = "write to read-only memory"; 316 else if (is_el1_instruction_abort(esr)) 317 msg = "execute from non-executable memory"; 318 else 319 msg = "read from unreadable memory"; 320 } else if (addr < PAGE_SIZE) { 321 msg = "NULL pointer dereference"; 322 } else { 323 msg = "paging request"; 324 } 325 326 die_kernel_fault(msg, addr, esr, regs); 327 } 328 329 static void set_thread_esr(unsigned long address, unsigned int esr) 330 { 331 current->thread.fault_address = address; 332 333 /* 334 * If the faulting address is in the kernel, we must sanitize the ESR. 335 * From userspace's point of view, kernel-only mappings don't exist 336 * at all, so we report them as level 0 translation faults. 337 * (This is not quite the way that "no mapping there at all" behaves: 338 * an alignment fault not caused by the memory type would take 339 * precedence over translation fault for a real access to empty 340 * space. Unfortunately we can't easily distinguish "alignment fault 341 * not caused by memory type" from "alignment fault caused by memory 342 * type", so we ignore this wrinkle and just return the translation 343 * fault.) 344 */ 345 if (!is_ttbr0_addr(current->thread.fault_address)) { 346 switch (ESR_ELx_EC(esr)) { 347 case ESR_ELx_EC_DABT_LOW: 348 /* 349 * These bits provide only information about the 350 * faulting instruction, which userspace knows already. 351 * We explicitly clear bits which are architecturally 352 * RES0 in case they are given meanings in future. 353 * We always report the ESR as if the fault was taken 354 * to EL1 and so ISV and the bits in ISS[23:14] are 355 * clear. (In fact it always will be a fault to EL1.) 356 */ 357 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | 358 ESR_ELx_CM | ESR_ELx_WNR; 359 esr |= ESR_ELx_FSC_FAULT; 360 break; 361 case ESR_ELx_EC_IABT_LOW: 362 /* 363 * Claim a level 0 translation fault. 364 * All other bits are architecturally RES0 for faults 365 * reported with that DFSC value, so we clear them. 366 */ 367 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; 368 esr |= ESR_ELx_FSC_FAULT; 369 break; 370 default: 371 /* 372 * This should never happen (entry.S only brings us 373 * into this code for insn and data aborts from a lower 374 * exception level). Fail safe by not providing an ESR 375 * context record at all. 376 */ 377 WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr); 378 esr = 0; 379 break; 380 } 381 } 382 383 current->thread.fault_code = esr; 384 } 385 386 static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs) 387 { 388 /* 389 * If we are in kernel mode at this point, we have no context to 390 * handle this fault with. 391 */ 392 if (user_mode(regs)) { 393 const struct fault_info *inf = esr_to_fault_info(esr); 394 395 set_thread_esr(addr, esr); 396 arm64_force_sig_fault(inf->sig, inf->code, (void __user *)addr, 397 inf->name); 398 } else { 399 __do_kernel_fault(addr, esr, regs); 400 } 401 } 402 403 #define VM_FAULT_BADMAP 0x010000 404 #define VM_FAULT_BADACCESS 0x020000 405 406 static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr, 407 unsigned int mm_flags, unsigned long vm_flags, 408 struct pt_regs *regs) 409 { 410 struct vm_area_struct *vma = find_vma(mm, addr); 411 412 if (unlikely(!vma)) 413 return VM_FAULT_BADMAP; 414 415 /* 416 * Ok, we have a good vm_area for this memory access, so we can handle 417 * it. 418 */ 419 if (unlikely(vma->vm_start > addr)) { 420 if (!(vma->vm_flags & VM_GROWSDOWN)) 421 return VM_FAULT_BADMAP; 422 if (expand_stack(vma, addr)) 423 return VM_FAULT_BADMAP; 424 } 425 426 /* 427 * Check that the permissions on the VMA allow for the fault which 428 * occurred. 429 */ 430 if (!(vma->vm_flags & vm_flags)) 431 return VM_FAULT_BADACCESS; 432 return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags, regs); 433 } 434 435 static bool is_el0_instruction_abort(unsigned int esr) 436 { 437 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; 438 } 439 440 /* 441 * Note: not valid for EL1 DC IVAC, but we never use that such that it 442 * should fault. EL0 cannot issue DC IVAC (undef). 443 */ 444 static bool is_write_abort(unsigned int esr) 445 { 446 return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM); 447 } 448 449 static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, 450 struct pt_regs *regs) 451 { 452 const struct fault_info *inf; 453 struct mm_struct *mm = current->mm; 454 vm_fault_t fault; 455 unsigned long vm_flags = VM_ACCESS_FLAGS; 456 unsigned int mm_flags = FAULT_FLAG_DEFAULT; 457 458 if (kprobe_page_fault(regs, esr)) 459 return 0; 460 461 /* 462 * If we're in an interrupt or have no user context, we must not take 463 * the fault. 464 */ 465 if (faulthandler_disabled() || !mm) 466 goto no_context; 467 468 if (user_mode(regs)) 469 mm_flags |= FAULT_FLAG_USER; 470 471 if (is_el0_instruction_abort(esr)) { 472 vm_flags = VM_EXEC; 473 mm_flags |= FAULT_FLAG_INSTRUCTION; 474 } else if (is_write_abort(esr)) { 475 vm_flags = VM_WRITE; 476 mm_flags |= FAULT_FLAG_WRITE; 477 } 478 479 if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { 480 /* regs->orig_addr_limit may be 0 if we entered from EL0 */ 481 if (regs->orig_addr_limit == KERNEL_DS) 482 die_kernel_fault("access to user memory with fs=KERNEL_DS", 483 addr, esr, regs); 484 485 if (is_el1_instruction_abort(esr)) 486 die_kernel_fault("execution of user memory", 487 addr, esr, regs); 488 489 if (!search_exception_tables(regs->pc)) 490 die_kernel_fault("access to user memory outside uaccess routines", 491 addr, esr, regs); 492 } 493 494 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); 495 496 /* 497 * As per x86, we may deadlock here. However, since the kernel only 498 * validly references user space from well defined areas of the code, 499 * we can bug out early if this is from code which shouldn't. 500 */ 501 if (!mmap_read_trylock(mm)) { 502 if (!user_mode(regs) && !search_exception_tables(regs->pc)) 503 goto no_context; 504 retry: 505 mmap_read_lock(mm); 506 } else { 507 /* 508 * The above down_read_trylock() might have succeeded in which 509 * case, we'll have missed the might_sleep() from down_read(). 510 */ 511 might_sleep(); 512 #ifdef CONFIG_DEBUG_VM 513 if (!user_mode(regs) && !search_exception_tables(regs->pc)) { 514 mmap_read_unlock(mm); 515 goto no_context; 516 } 517 #endif 518 } 519 520 fault = __do_page_fault(mm, addr, mm_flags, vm_flags, regs); 521 522 /* Quick path to respond to signals */ 523 if (fault_signal_pending(fault, regs)) { 524 if (!user_mode(regs)) 525 goto no_context; 526 return 0; 527 } 528 529 if (fault & VM_FAULT_RETRY) { 530 if (mm_flags & FAULT_FLAG_ALLOW_RETRY) { 531 mm_flags |= FAULT_FLAG_TRIED; 532 goto retry; 533 } 534 } 535 mmap_read_unlock(mm); 536 537 /* 538 * Handle the "normal" (no error) case first. 539 */ 540 if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP | 541 VM_FAULT_BADACCESS)))) 542 return 0; 543 544 /* 545 * If we are in kernel mode at this point, we have no context to 546 * handle this fault with. 547 */ 548 if (!user_mode(regs)) 549 goto no_context; 550 551 if (fault & VM_FAULT_OOM) { 552 /* 553 * We ran out of memory, call the OOM killer, and return to 554 * userspace (which will retry the fault, or kill us if we got 555 * oom-killed). 556 */ 557 pagefault_out_of_memory(); 558 return 0; 559 } 560 561 inf = esr_to_fault_info(esr); 562 set_thread_esr(addr, esr); 563 if (fault & VM_FAULT_SIGBUS) { 564 /* 565 * We had some memory, but were unable to successfully fix up 566 * this page fault. 567 */ 568 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)addr, 569 inf->name); 570 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { 571 unsigned int lsb; 572 573 lsb = PAGE_SHIFT; 574 if (fault & VM_FAULT_HWPOISON_LARGE) 575 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); 576 577 arm64_force_sig_mceerr(BUS_MCEERR_AR, (void __user *)addr, lsb, 578 inf->name); 579 } else { 580 /* 581 * Something tried to access memory that isn't in our memory 582 * map. 583 */ 584 arm64_force_sig_fault(SIGSEGV, 585 fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR, 586 (void __user *)addr, 587 inf->name); 588 } 589 590 return 0; 591 592 no_context: 593 __do_kernel_fault(addr, esr, regs); 594 return 0; 595 } 596 597 static int __kprobes do_translation_fault(unsigned long addr, 598 unsigned int esr, 599 struct pt_regs *regs) 600 { 601 if (is_ttbr0_addr(addr)) 602 return do_page_fault(addr, esr, regs); 603 604 do_bad_area(addr, esr, regs); 605 return 0; 606 } 607 608 static int do_alignment_fault(unsigned long addr, unsigned int esr, 609 struct pt_regs *regs) 610 { 611 do_bad_area(addr, esr, regs); 612 return 0; 613 } 614 615 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) 616 { 617 return 1; /* "fault" */ 618 } 619 620 static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) 621 { 622 const struct fault_info *inf; 623 void __user *siaddr; 624 625 inf = esr_to_fault_info(esr); 626 627 if (user_mode(regs) && apei_claim_sea(regs) == 0) { 628 /* 629 * APEI claimed this as a firmware-first notification. 630 * Some processing deferred to task_work before ret_to_user(). 631 */ 632 return 0; 633 } 634 635 if (esr & ESR_ELx_FnV) 636 siaddr = NULL; 637 else 638 siaddr = (void __user *)addr; 639 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); 640 641 return 0; 642 } 643 644 static const struct fault_info fault_info[] = { 645 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, 646 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, 647 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, 648 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, 649 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, 650 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, 651 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, 652 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, 653 { do_bad, SIGKILL, SI_KERNEL, "unknown 8" }, 654 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, 655 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, 656 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, 657 { do_bad, SIGKILL, SI_KERNEL, "unknown 12" }, 658 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, 659 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, 660 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, 661 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, 662 { do_bad, SIGKILL, SI_KERNEL, "unknown 17" }, 663 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, 664 { do_bad, SIGKILL, SI_KERNEL, "unknown 19" }, 665 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, 666 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, 667 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, 668 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, 669 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented 670 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, 671 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, 672 { do_bad, SIGKILL, SI_KERNEL, "unknown 27" }, 673 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 674 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 675 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 676 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 677 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, 678 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, 679 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, 680 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, 681 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, 682 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, 683 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, 684 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, 685 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, 686 { do_bad, SIGKILL, SI_KERNEL, "unknown 41" }, 687 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, 688 { do_bad, SIGKILL, SI_KERNEL, "unknown 43" }, 689 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, 690 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, 691 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, 692 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, 693 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, 694 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, 695 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, 696 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, 697 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, 698 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, 699 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, 700 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, 701 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, 702 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, 703 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, 704 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, 705 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, 706 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, 707 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, 708 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, 709 }; 710 711 void do_mem_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs) 712 { 713 const struct fault_info *inf = esr_to_fault_info(esr); 714 715 if (!inf->fn(addr, esr, regs)) 716 return; 717 718 if (!user_mode(regs)) { 719 pr_alert("Unhandled fault at 0x%016lx\n", addr); 720 mem_abort_decode(esr); 721 show_pte(addr); 722 } 723 724 arm64_notify_die(inf->name, regs, 725 inf->sig, inf->code, (void __user *)addr, esr); 726 } 727 NOKPROBE_SYMBOL(do_mem_abort); 728 729 void do_el0_irq_bp_hardening(void) 730 { 731 /* PC has already been checked in entry.S */ 732 arm64_apply_bp_hardening(); 733 } 734 NOKPROBE_SYMBOL(do_el0_irq_bp_hardening); 735 736 void do_sp_pc_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs) 737 { 738 arm64_notify_die("SP/PC alignment exception", regs, 739 SIGBUS, BUS_ADRALN, (void __user *)addr, esr); 740 } 741 NOKPROBE_SYMBOL(do_sp_pc_abort); 742 743 int __init early_brk64(unsigned long addr, unsigned int esr, 744 struct pt_regs *regs); 745 746 /* 747 * __refdata because early_brk64 is __init, but the reference to it is 748 * clobbered at arch_initcall time. 749 * See traps.c and debug-monitors.c:debug_traps_init(). 750 */ 751 static struct fault_info __refdata debug_fault_info[] = { 752 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" }, 753 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" }, 754 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" }, 755 { do_bad, SIGKILL, SI_KERNEL, "unknown 3" }, 756 { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" }, 757 { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" }, 758 { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" }, 759 { do_bad, SIGKILL, SI_KERNEL, "unknown 7" }, 760 }; 761 762 void __init hook_debug_fault_code(int nr, 763 int (*fn)(unsigned long, unsigned int, struct pt_regs *), 764 int sig, int code, const char *name) 765 { 766 BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info)); 767 768 debug_fault_info[nr].fn = fn; 769 debug_fault_info[nr].sig = sig; 770 debug_fault_info[nr].code = code; 771 debug_fault_info[nr].name = name; 772 } 773 774 /* 775 * In debug exception context, we explicitly disable preemption despite 776 * having interrupts disabled. 777 * This serves two purposes: it makes it much less likely that we would 778 * accidentally schedule in exception context and it will force a warning 779 * if we somehow manage to schedule by accident. 780 */ 781 static void debug_exception_enter(struct pt_regs *regs) 782 { 783 /* 784 * Tell lockdep we disabled irqs in entry.S. Do nothing if they were 785 * already disabled to preserve the last enabled/disabled addresses. 786 */ 787 if (interrupts_enabled(regs)) 788 trace_hardirqs_off(); 789 790 if (user_mode(regs)) { 791 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); 792 } else { 793 /* 794 * We might have interrupted pretty much anything. In 795 * fact, if we're a debug exception, we can even interrupt 796 * NMI processing. We don't want this code makes in_nmi() 797 * to return true, but we need to notify RCU. 798 */ 799 rcu_nmi_enter(); 800 } 801 802 preempt_disable(); 803 804 /* This code is a bit fragile. Test it. */ 805 RCU_LOCKDEP_WARN(!rcu_is_watching(), "exception_enter didn't work"); 806 } 807 NOKPROBE_SYMBOL(debug_exception_enter); 808 809 static void debug_exception_exit(struct pt_regs *regs) 810 { 811 preempt_enable_no_resched(); 812 813 if (!user_mode(regs)) 814 rcu_nmi_exit(); 815 816 if (interrupts_enabled(regs)) 817 trace_hardirqs_on(); 818 } 819 NOKPROBE_SYMBOL(debug_exception_exit); 820 821 #ifdef CONFIG_ARM64_ERRATUM_1463225 822 DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); 823 824 static int cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) 825 { 826 if (user_mode(regs)) 827 return 0; 828 829 if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa)) 830 return 0; 831 832 /* 833 * We've taken a dummy step exception from the kernel to ensure 834 * that interrupts are re-enabled on the syscall path. Return back 835 * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions 836 * masked so that we can safely restore the mdscr and get on with 837 * handling the syscall. 838 */ 839 regs->pstate |= PSR_D_BIT; 840 return 1; 841 } 842 #else 843 static int cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) 844 { 845 return 0; 846 } 847 #endif /* CONFIG_ARM64_ERRATUM_1463225 */ 848 NOKPROBE_SYMBOL(cortex_a76_erratum_1463225_debug_handler); 849 850 void do_debug_exception(unsigned long addr_if_watchpoint, unsigned int esr, 851 struct pt_regs *regs) 852 { 853 const struct fault_info *inf = esr_to_debug_fault_info(esr); 854 unsigned long pc = instruction_pointer(regs); 855 856 if (cortex_a76_erratum_1463225_debug_handler(regs)) 857 return; 858 859 debug_exception_enter(regs); 860 861 if (user_mode(regs) && !is_ttbr0_addr(pc)) 862 arm64_apply_bp_hardening(); 863 864 if (inf->fn(addr_if_watchpoint, esr, regs)) { 865 arm64_notify_die(inf->name, regs, 866 inf->sig, inf->code, (void __user *)pc, esr); 867 } 868 869 debug_exception_exit(regs); 870 } 871 NOKPROBE_SYMBOL(do_debug_exception); 872