1 /* 2 * Based on arch/arm/mm/fault.c 3 * 4 * Copyright (C) 1995 Linus Torvalds 5 * Copyright (C) 1995-2004 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <linux/extable.h> 22 #include <linux/signal.h> 23 #include <linux/mm.h> 24 #include <linux/hardirq.h> 25 #include <linux/init.h> 26 #include <linux/kprobes.h> 27 #include <linux/uaccess.h> 28 #include <linux/page-flags.h> 29 #include <linux/sched/signal.h> 30 #include <linux/sched/debug.h> 31 #include <linux/highmem.h> 32 #include <linux/perf_event.h> 33 #include <linux/preempt.h> 34 #include <linux/hugetlb.h> 35 36 #include <asm/bug.h> 37 #include <asm/cmpxchg.h> 38 #include <asm/cpufeature.h> 39 #include <asm/exception.h> 40 #include <asm/daifflags.h> 41 #include <asm/debug-monitors.h> 42 #include <asm/esr.h> 43 #include <asm/sysreg.h> 44 #include <asm/system_misc.h> 45 #include <asm/pgtable.h> 46 #include <asm/tlbflush.h> 47 #include <asm/traps.h> 48 49 #include <acpi/ghes.h> 50 51 struct fault_info { 52 int (*fn)(unsigned long addr, unsigned int esr, 53 struct pt_regs *regs); 54 int sig; 55 int code; 56 const char *name; 57 }; 58 59 static const struct fault_info fault_info[]; 60 static struct fault_info debug_fault_info[]; 61 62 static inline const struct fault_info *esr_to_fault_info(unsigned int esr) 63 { 64 return fault_info + (esr & ESR_ELx_FSC); 65 } 66 67 static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr) 68 { 69 return debug_fault_info + DBG_ESR_EVT(esr); 70 } 71 72 #ifdef CONFIG_KPROBES 73 static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) 74 { 75 int ret = 0; 76 77 /* kprobe_running() needs smp_processor_id() */ 78 if (!user_mode(regs)) { 79 preempt_disable(); 80 if (kprobe_running() && kprobe_fault_handler(regs, esr)) 81 ret = 1; 82 preempt_enable(); 83 } 84 85 return ret; 86 } 87 #else 88 static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) 89 { 90 return 0; 91 } 92 #endif 93 94 static void data_abort_decode(unsigned int esr) 95 { 96 pr_alert("Data abort info:\n"); 97 98 if (esr & ESR_ELx_ISV) { 99 pr_alert(" Access size = %u byte(s)\n", 100 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); 101 pr_alert(" SSE = %lu, SRT = %lu\n", 102 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, 103 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); 104 pr_alert(" SF = %lu, AR = %lu\n", 105 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, 106 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); 107 } else { 108 pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK); 109 } 110 111 pr_alert(" CM = %lu, WnR = %lu\n", 112 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, 113 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT); 114 } 115 116 static void mem_abort_decode(unsigned int esr) 117 { 118 pr_alert("Mem abort info:\n"); 119 120 pr_alert(" ESR = 0x%08x\n", esr); 121 pr_alert(" Exception class = %s, IL = %u bits\n", 122 esr_get_class_string(esr), 123 (esr & ESR_ELx_IL) ? 32 : 16); 124 pr_alert(" SET = %lu, FnV = %lu\n", 125 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, 126 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); 127 pr_alert(" EA = %lu, S1PTW = %lu\n", 128 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, 129 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); 130 131 if (esr_is_data_abort(esr)) 132 data_abort_decode(esr); 133 } 134 135 /* 136 * Dump out the page tables associated with 'addr' in the currently active mm. 137 */ 138 void show_pte(unsigned long addr) 139 { 140 struct mm_struct *mm; 141 pgd_t *pgdp; 142 pgd_t pgd; 143 144 if (addr < TASK_SIZE) { 145 /* TTBR0 */ 146 mm = current->active_mm; 147 if (mm == &init_mm) { 148 pr_alert("[%016lx] user address but active_mm is swapper\n", 149 addr); 150 return; 151 } 152 } else if (addr >= VA_START) { 153 /* TTBR1 */ 154 mm = &init_mm; 155 } else { 156 pr_alert("[%016lx] address between user and kernel address ranges\n", 157 addr); 158 return; 159 } 160 161 pr_alert("%s pgtable: %luk pages, %u-bit VAs, pgdp = %p\n", 162 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, 163 VA_BITS, mm->pgd); 164 pgdp = pgd_offset(mm, addr); 165 pgd = READ_ONCE(*pgdp); 166 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); 167 168 do { 169 pud_t *pudp, pud; 170 pmd_t *pmdp, pmd; 171 pte_t *ptep, pte; 172 173 if (pgd_none(pgd) || pgd_bad(pgd)) 174 break; 175 176 pudp = pud_offset(pgdp, addr); 177 pud = READ_ONCE(*pudp); 178 pr_cont(", pud=%016llx", pud_val(pud)); 179 if (pud_none(pud) || pud_bad(pud)) 180 break; 181 182 pmdp = pmd_offset(pudp, addr); 183 pmd = READ_ONCE(*pmdp); 184 pr_cont(", pmd=%016llx", pmd_val(pmd)); 185 if (pmd_none(pmd) || pmd_bad(pmd)) 186 break; 187 188 ptep = pte_offset_map(pmdp, addr); 189 pte = READ_ONCE(*ptep); 190 pr_cont(", pte=%016llx", pte_val(pte)); 191 pte_unmap(ptep); 192 } while(0); 193 194 pr_cont("\n"); 195 } 196 197 /* 198 * This function sets the access flags (dirty, accessed), as well as write 199 * permission, and only to a more permissive setting. 200 * 201 * It needs to cope with hardware update of the accessed/dirty state by other 202 * agents in the system and can safely skip the __sync_icache_dcache() call as, 203 * like set_pte_at(), the PTE is never changed from no-exec to exec here. 204 * 205 * Returns whether or not the PTE actually changed. 206 */ 207 int ptep_set_access_flags(struct vm_area_struct *vma, 208 unsigned long address, pte_t *ptep, 209 pte_t entry, int dirty) 210 { 211 pteval_t old_pteval, pteval; 212 pte_t pte = READ_ONCE(*ptep); 213 214 if (pte_same(pte, entry)) 215 return 0; 216 217 /* only preserve the access flags and write permission */ 218 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; 219 220 /* 221 * Setting the flags must be done atomically to avoid racing with the 222 * hardware update of the access/dirty state. The PTE_RDONLY bit must 223 * be set to the most permissive (lowest value) of *ptep and entry 224 * (calculated as: a & b == ~(~a | ~b)). 225 */ 226 pte_val(entry) ^= PTE_RDONLY; 227 pteval = pte_val(pte); 228 do { 229 old_pteval = pteval; 230 pteval ^= PTE_RDONLY; 231 pteval |= pte_val(entry); 232 pteval ^= PTE_RDONLY; 233 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); 234 } while (pteval != old_pteval); 235 236 flush_tlb_fix_spurious_fault(vma, address); 237 return 1; 238 } 239 240 static bool is_el1_instruction_abort(unsigned int esr) 241 { 242 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; 243 } 244 245 static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr, 246 struct pt_regs *regs) 247 { 248 unsigned int ec = ESR_ELx_EC(esr); 249 unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; 250 251 if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR) 252 return false; 253 254 if (fsc_type == ESR_ELx_FSC_PERM) 255 return true; 256 257 if (addr < TASK_SIZE && system_uses_ttbr0_pan()) 258 return fsc_type == ESR_ELx_FSC_FAULT && 259 (regs->pstate & PSR_PAN_BIT); 260 261 return false; 262 } 263 264 static void die_kernel_fault(const char *msg, unsigned long addr, 265 unsigned int esr, struct pt_regs *regs) 266 { 267 bust_spinlocks(1); 268 269 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, 270 addr); 271 272 mem_abort_decode(esr); 273 274 show_pte(addr); 275 die("Oops", regs, esr); 276 bust_spinlocks(0); 277 do_exit(SIGKILL); 278 } 279 280 static void __do_kernel_fault(unsigned long addr, unsigned int esr, 281 struct pt_regs *regs) 282 { 283 const char *msg; 284 285 /* 286 * Are we prepared to handle this kernel fault? 287 * We are almost certainly not prepared to handle instruction faults. 288 */ 289 if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) 290 return; 291 292 if (is_el1_permission_fault(addr, esr, regs)) { 293 if (esr & ESR_ELx_WNR) 294 msg = "write to read-only memory"; 295 else 296 msg = "read from unreadable memory"; 297 } else if (addr < PAGE_SIZE) { 298 msg = "NULL pointer dereference"; 299 } else { 300 msg = "paging request"; 301 } 302 303 die_kernel_fault(msg, addr, esr, regs); 304 } 305 306 static void set_thread_esr(unsigned long address, unsigned int esr) 307 { 308 current->thread.fault_address = address; 309 310 /* 311 * If the faulting address is in the kernel, we must sanitize the ESR. 312 * From userspace's point of view, kernel-only mappings don't exist 313 * at all, so we report them as level 0 translation faults. 314 * (This is not quite the way that "no mapping there at all" behaves: 315 * an alignment fault not caused by the memory type would take 316 * precedence over translation fault for a real access to empty 317 * space. Unfortunately we can't easily distinguish "alignment fault 318 * not caused by memory type" from "alignment fault caused by memory 319 * type", so we ignore this wrinkle and just return the translation 320 * fault.) 321 */ 322 if (current->thread.fault_address >= TASK_SIZE) { 323 switch (ESR_ELx_EC(esr)) { 324 case ESR_ELx_EC_DABT_LOW: 325 /* 326 * These bits provide only information about the 327 * faulting instruction, which userspace knows already. 328 * We explicitly clear bits which are architecturally 329 * RES0 in case they are given meanings in future. 330 * We always report the ESR as if the fault was taken 331 * to EL1 and so ISV and the bits in ISS[23:14] are 332 * clear. (In fact it always will be a fault to EL1.) 333 */ 334 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | 335 ESR_ELx_CM | ESR_ELx_WNR; 336 esr |= ESR_ELx_FSC_FAULT; 337 break; 338 case ESR_ELx_EC_IABT_LOW: 339 /* 340 * Claim a level 0 translation fault. 341 * All other bits are architecturally RES0 for faults 342 * reported with that DFSC value, so we clear them. 343 */ 344 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; 345 esr |= ESR_ELx_FSC_FAULT; 346 break; 347 default: 348 /* 349 * This should never happen (entry.S only brings us 350 * into this code for insn and data aborts from a lower 351 * exception level). Fail safe by not providing an ESR 352 * context record at all. 353 */ 354 WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr); 355 esr = 0; 356 break; 357 } 358 } 359 360 current->thread.fault_code = esr; 361 } 362 363 static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs) 364 { 365 /* 366 * If we are in kernel mode at this point, we have no context to 367 * handle this fault with. 368 */ 369 if (user_mode(regs)) { 370 const struct fault_info *inf = esr_to_fault_info(esr); 371 372 set_thread_esr(addr, esr); 373 arm64_force_sig_fault(inf->sig, inf->code, (void __user *)addr, 374 inf->name); 375 } else { 376 __do_kernel_fault(addr, esr, regs); 377 } 378 } 379 380 #define VM_FAULT_BADMAP 0x010000 381 #define VM_FAULT_BADACCESS 0x020000 382 383 static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr, 384 unsigned int mm_flags, unsigned long vm_flags, 385 struct task_struct *tsk) 386 { 387 struct vm_area_struct *vma; 388 vm_fault_t fault; 389 390 vma = find_vma(mm, addr); 391 fault = VM_FAULT_BADMAP; 392 if (unlikely(!vma)) 393 goto out; 394 if (unlikely(vma->vm_start > addr)) 395 goto check_stack; 396 397 /* 398 * Ok, we have a good vm_area for this memory access, so we can handle 399 * it. 400 */ 401 good_area: 402 /* 403 * Check that the permissions on the VMA allow for the fault which 404 * occurred. 405 */ 406 if (!(vma->vm_flags & vm_flags)) { 407 fault = VM_FAULT_BADACCESS; 408 goto out; 409 } 410 411 return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags); 412 413 check_stack: 414 if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr)) 415 goto good_area; 416 out: 417 return fault; 418 } 419 420 static bool is_el0_instruction_abort(unsigned int esr) 421 { 422 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; 423 } 424 425 static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, 426 struct pt_regs *regs) 427 { 428 const struct fault_info *inf; 429 struct task_struct *tsk; 430 struct mm_struct *mm; 431 vm_fault_t fault, major = 0; 432 unsigned long vm_flags = VM_READ | VM_WRITE; 433 unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; 434 435 if (notify_page_fault(regs, esr)) 436 return 0; 437 438 tsk = current; 439 mm = tsk->mm; 440 441 /* 442 * If we're in an interrupt or have no user context, we must not take 443 * the fault. 444 */ 445 if (faulthandler_disabled() || !mm) 446 goto no_context; 447 448 if (user_mode(regs)) 449 mm_flags |= FAULT_FLAG_USER; 450 451 if (is_el0_instruction_abort(esr)) { 452 vm_flags = VM_EXEC; 453 } else if ((esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM)) { 454 vm_flags = VM_WRITE; 455 mm_flags |= FAULT_FLAG_WRITE; 456 } 457 458 if (addr < TASK_SIZE && is_el1_permission_fault(addr, esr, regs)) { 459 /* regs->orig_addr_limit may be 0 if we entered from EL0 */ 460 if (regs->orig_addr_limit == KERNEL_DS) 461 die_kernel_fault("access to user memory with fs=KERNEL_DS", 462 addr, esr, regs); 463 464 if (is_el1_instruction_abort(esr)) 465 die_kernel_fault("execution of user memory", 466 addr, esr, regs); 467 468 if (!search_exception_tables(regs->pc)) 469 die_kernel_fault("access to user memory outside uaccess routines", 470 addr, esr, regs); 471 } 472 473 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); 474 475 /* 476 * As per x86, we may deadlock here. However, since the kernel only 477 * validly references user space from well defined areas of the code, 478 * we can bug out early if this is from code which shouldn't. 479 */ 480 if (!down_read_trylock(&mm->mmap_sem)) { 481 if (!user_mode(regs) && !search_exception_tables(regs->pc)) 482 goto no_context; 483 retry: 484 down_read(&mm->mmap_sem); 485 } else { 486 /* 487 * The above down_read_trylock() might have succeeded in which 488 * case, we'll have missed the might_sleep() from down_read(). 489 */ 490 might_sleep(); 491 #ifdef CONFIG_DEBUG_VM 492 if (!user_mode(regs) && !search_exception_tables(regs->pc)) 493 goto no_context; 494 #endif 495 } 496 497 fault = __do_page_fault(mm, addr, mm_flags, vm_flags, tsk); 498 major |= fault & VM_FAULT_MAJOR; 499 500 if (fault & VM_FAULT_RETRY) { 501 /* 502 * If we need to retry but a fatal signal is pending, 503 * handle the signal first. We do not need to release 504 * the mmap_sem because it would already be released 505 * in __lock_page_or_retry in mm/filemap.c. 506 */ 507 if (fatal_signal_pending(current)) { 508 if (!user_mode(regs)) 509 goto no_context; 510 return 0; 511 } 512 513 /* 514 * Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk of 515 * starvation. 516 */ 517 if (mm_flags & FAULT_FLAG_ALLOW_RETRY) { 518 mm_flags &= ~FAULT_FLAG_ALLOW_RETRY; 519 mm_flags |= FAULT_FLAG_TRIED; 520 goto retry; 521 } 522 } 523 up_read(&mm->mmap_sem); 524 525 /* 526 * Handle the "normal" (no error) case first. 527 */ 528 if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP | 529 VM_FAULT_BADACCESS)))) { 530 /* 531 * Major/minor page fault accounting is only done 532 * once. If we go through a retry, it is extremely 533 * likely that the page will be found in page cache at 534 * that point. 535 */ 536 if (major) { 537 tsk->maj_flt++; 538 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, 539 addr); 540 } else { 541 tsk->min_flt++; 542 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, 543 addr); 544 } 545 546 return 0; 547 } 548 549 /* 550 * If we are in kernel mode at this point, we have no context to 551 * handle this fault with. 552 */ 553 if (!user_mode(regs)) 554 goto no_context; 555 556 if (fault & VM_FAULT_OOM) { 557 /* 558 * We ran out of memory, call the OOM killer, and return to 559 * userspace (which will retry the fault, or kill us if we got 560 * oom-killed). 561 */ 562 pagefault_out_of_memory(); 563 return 0; 564 } 565 566 inf = esr_to_fault_info(esr); 567 set_thread_esr(addr, esr); 568 if (fault & VM_FAULT_SIGBUS) { 569 /* 570 * We had some memory, but were unable to successfully fix up 571 * this page fault. 572 */ 573 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)addr, 574 inf->name); 575 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { 576 unsigned int lsb; 577 578 lsb = PAGE_SHIFT; 579 if (fault & VM_FAULT_HWPOISON_LARGE) 580 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); 581 582 arm64_force_sig_mceerr(BUS_MCEERR_AR, (void __user *)addr, lsb, 583 inf->name); 584 } else { 585 /* 586 * Something tried to access memory that isn't in our memory 587 * map. 588 */ 589 arm64_force_sig_fault(SIGSEGV, 590 fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR, 591 (void __user *)addr, 592 inf->name); 593 } 594 595 return 0; 596 597 no_context: 598 __do_kernel_fault(addr, esr, regs); 599 return 0; 600 } 601 602 static int __kprobes do_translation_fault(unsigned long addr, 603 unsigned int esr, 604 struct pt_regs *regs) 605 { 606 if (addr < TASK_SIZE) 607 return do_page_fault(addr, esr, regs); 608 609 do_bad_area(addr, esr, regs); 610 return 0; 611 } 612 613 static int do_alignment_fault(unsigned long addr, unsigned int esr, 614 struct pt_regs *regs) 615 { 616 do_bad_area(addr, esr, regs); 617 return 0; 618 } 619 620 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) 621 { 622 return 1; /* "fault" */ 623 } 624 625 static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) 626 { 627 const struct fault_info *inf; 628 void __user *siaddr; 629 630 inf = esr_to_fault_info(esr); 631 632 /* 633 * Synchronous aborts may interrupt code which had interrupts masked. 634 * Before calling out into the wider kernel tell the interested 635 * subsystems. 636 */ 637 if (IS_ENABLED(CONFIG_ACPI_APEI_SEA)) { 638 if (interrupts_enabled(regs)) 639 nmi_enter(); 640 641 ghes_notify_sea(); 642 643 if (interrupts_enabled(regs)) 644 nmi_exit(); 645 } 646 647 if (esr & ESR_ELx_FnV) 648 siaddr = NULL; 649 else 650 siaddr = (void __user *)addr; 651 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); 652 653 return 0; 654 } 655 656 static const struct fault_info fault_info[] = { 657 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, 658 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, 659 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, 660 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, 661 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, 662 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, 663 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, 664 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, 665 { do_bad, SIGKILL, SI_KERNEL, "unknown 8" }, 666 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, 667 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, 668 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, 669 { do_bad, SIGKILL, SI_KERNEL, "unknown 12" }, 670 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, 671 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, 672 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, 673 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, 674 { do_bad, SIGKILL, SI_KERNEL, "unknown 17" }, 675 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, 676 { do_bad, SIGKILL, SI_KERNEL, "unknown 19" }, 677 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, 678 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, 679 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, 680 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, 681 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented 682 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, 683 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, 684 { do_bad, SIGKILL, SI_KERNEL, "unknown 27" }, 685 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 686 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 687 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 688 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 689 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, 690 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, 691 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, 692 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, 693 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, 694 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, 695 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, 696 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, 697 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, 698 { do_bad, SIGKILL, SI_KERNEL, "unknown 41" }, 699 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, 700 { do_bad, SIGKILL, SI_KERNEL, "unknown 43" }, 701 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, 702 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, 703 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, 704 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, 705 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, 706 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, 707 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, 708 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, 709 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, 710 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, 711 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, 712 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, 713 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, 714 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, 715 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, 716 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, 717 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, 718 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, 719 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, 720 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, 721 }; 722 723 int handle_guest_sea(phys_addr_t addr, unsigned int esr) 724 { 725 return ghes_notify_sea(); 726 } 727 728 asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, 729 struct pt_regs *regs) 730 { 731 const struct fault_info *inf = esr_to_fault_info(esr); 732 733 if (!inf->fn(addr, esr, regs)) 734 return; 735 736 if (!user_mode(regs)) { 737 pr_alert("Unhandled fault at 0x%016lx\n", addr); 738 mem_abort_decode(esr); 739 show_pte(addr); 740 } 741 742 arm64_notify_die(inf->name, regs, 743 inf->sig, inf->code, (void __user *)addr, esr); 744 } 745 746 asmlinkage void __exception do_el0_irq_bp_hardening(void) 747 { 748 /* PC has already been checked in entry.S */ 749 arm64_apply_bp_hardening(); 750 } 751 752 asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, 753 unsigned int esr, 754 struct pt_regs *regs) 755 { 756 /* 757 * We've taken an instruction abort from userspace and not yet 758 * re-enabled IRQs. If the address is a kernel address, apply 759 * BP hardening prior to enabling IRQs and pre-emption. 760 */ 761 if (addr > TASK_SIZE) 762 arm64_apply_bp_hardening(); 763 764 local_daif_restore(DAIF_PROCCTX); 765 do_mem_abort(addr, esr, regs); 766 } 767 768 769 asmlinkage void __exception do_sp_pc_abort(unsigned long addr, 770 unsigned int esr, 771 struct pt_regs *regs) 772 { 773 if (user_mode(regs)) { 774 if (instruction_pointer(regs) > TASK_SIZE) 775 arm64_apply_bp_hardening(); 776 local_daif_restore(DAIF_PROCCTX); 777 } 778 779 arm64_notify_die("SP/PC alignment exception", regs, 780 SIGBUS, BUS_ADRALN, (void __user *)addr, esr); 781 } 782 783 int __init early_brk64(unsigned long addr, unsigned int esr, 784 struct pt_regs *regs); 785 786 /* 787 * __refdata because early_brk64 is __init, but the reference to it is 788 * clobbered at arch_initcall time. 789 * See traps.c and debug-monitors.c:debug_traps_init(). 790 */ 791 static struct fault_info __refdata debug_fault_info[] = { 792 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" }, 793 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" }, 794 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" }, 795 { do_bad, SIGKILL, SI_KERNEL, "unknown 3" }, 796 { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" }, 797 { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" }, 798 { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" }, 799 { do_bad, SIGKILL, SI_KERNEL, "unknown 7" }, 800 }; 801 802 void __init hook_debug_fault_code(int nr, 803 int (*fn)(unsigned long, unsigned int, struct pt_regs *), 804 int sig, int code, const char *name) 805 { 806 BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info)); 807 808 debug_fault_info[nr].fn = fn; 809 debug_fault_info[nr].sig = sig; 810 debug_fault_info[nr].code = code; 811 debug_fault_info[nr].name = name; 812 } 813 814 asmlinkage int __exception do_debug_exception(unsigned long addr, 815 unsigned int esr, 816 struct pt_regs *regs) 817 { 818 const struct fault_info *inf = esr_to_debug_fault_info(esr); 819 int rv; 820 821 /* 822 * Tell lockdep we disabled irqs in entry.S. Do nothing if they were 823 * already disabled to preserve the last enabled/disabled addresses. 824 */ 825 if (interrupts_enabled(regs)) 826 trace_hardirqs_off(); 827 828 if (user_mode(regs) && instruction_pointer(regs) > TASK_SIZE) 829 arm64_apply_bp_hardening(); 830 831 if (!inf->fn(addr, esr, regs)) { 832 rv = 1; 833 } else { 834 arm64_notify_die(inf->name, regs, 835 inf->sig, inf->code, (void __user *)addr, esr); 836 rv = 0; 837 } 838 839 if (interrupts_enabled(regs)) 840 trace_hardirqs_on(); 841 842 return rv; 843 } 844 NOKPROBE_SYMBOL(do_debug_exception); 845