1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 * Author: Catalin Marinas <catalin.marinas@arm.com> 5 */ 6 7 #include <linux/gfp.h> 8 #include <linux/cache.h> 9 #include <linux/dma-noncoherent.h> 10 #include <linux/dma-iommu.h> 11 12 #include <asm/cacheflush.h> 13 14 pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot, 15 unsigned long attrs) 16 { 17 if (!dev_is_dma_coherent(dev) || (attrs & DMA_ATTR_WRITE_COMBINE)) 18 return pgprot_writecombine(prot); 19 return prot; 20 } 21 22 void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr, 23 size_t size, enum dma_data_direction dir) 24 { 25 __dma_map_area(phys_to_virt(paddr), size, dir); 26 } 27 28 void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr, 29 size_t size, enum dma_data_direction dir) 30 { 31 __dma_unmap_area(phys_to_virt(paddr), size, dir); 32 } 33 34 void arch_dma_prep_coherent(struct page *page, size_t size) 35 { 36 __dma_flush_area(page_address(page), size); 37 } 38 39 static int __init arm64_dma_init(void) 40 { 41 return dma_atomic_pool_init(GFP_DMA32, __pgprot(PROT_NORMAL_NC)); 42 } 43 arch_initcall(arm64_dma_init); 44 45 #ifdef CONFIG_IOMMU_DMA 46 void arch_teardown_dma_ops(struct device *dev) 47 { 48 dev->dma_ops = NULL; 49 } 50 #endif 51 52 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, 53 const struct iommu_ops *iommu, bool coherent) 54 { 55 int cls = cache_line_size_of_cpu(); 56 57 WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN, 58 TAINT_CPU_OUT_OF_SPEC, 59 "%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)", 60 dev_driver_string(dev), dev_name(dev), 61 ARCH_DMA_MINALIGN, cls); 62 63 dev->dma_coherent = coherent; 64 if (iommu) 65 iommu_setup_dma_ops(dev, dma_base, size); 66 67 #ifdef CONFIG_XEN 68 if (xen_initial_domain()) 69 dev->dma_ops = xen_dma_ops; 70 #endif 71 } 72