1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2b3901d54SCatalin Marinas /* 3b3901d54SCatalin Marinas * Based on arch/arm/mm/context.c 4b3901d54SCatalin Marinas * 5b3901d54SCatalin Marinas * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved. 6b3901d54SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 7b3901d54SCatalin Marinas */ 8b3901d54SCatalin Marinas 925b92693SMark Rutland #include <linux/bitfield.h> 105aec715dSWill Deacon #include <linux/bitops.h> 11b3901d54SCatalin Marinas #include <linux/sched.h> 125aec715dSWill Deacon #include <linux/slab.h> 13b3901d54SCatalin Marinas #include <linux/mm.h> 14b3901d54SCatalin Marinas 155aec715dSWill Deacon #include <asm/cpufeature.h> 16b3901d54SCatalin Marinas #include <asm/mmu_context.h> 1713f417f3SSuzuki K Poulose #include <asm/smp.h> 18b3901d54SCatalin Marinas #include <asm/tlbflush.h> 19b3901d54SCatalin Marinas 205aec715dSWill Deacon static u32 asid_bits; 21b3901d54SCatalin Marinas static DEFINE_RAW_SPINLOCK(cpu_asid_lock); 225aec715dSWill Deacon 235aec715dSWill Deacon static atomic64_t asid_generation; 245aec715dSWill Deacon static unsigned long *asid_map; 255aec715dSWill Deacon 265aec715dSWill Deacon static DEFINE_PER_CPU(atomic64_t, active_asids); 275aec715dSWill Deacon static DEFINE_PER_CPU(u64, reserved_asids); 285aec715dSWill Deacon static cpumask_t tlb_flush_pending; 295aec715dSWill Deacon 3048118151SJean-Philippe Brucker static unsigned long max_pinned_asids; 3148118151SJean-Philippe Brucker static unsigned long nr_pinned_asids; 3248118151SJean-Philippe Brucker static unsigned long *pinned_asid_map; 3348118151SJean-Philippe Brucker 345aec715dSWill Deacon #define ASID_MASK (~GENMASK(asid_bits - 1, 0)) 355aec715dSWill Deacon #define ASID_FIRST_VERSION (1UL << asid_bits) 360c8ea531SWill Deacon 37f88f42f8SVladimir Murzin #define NUM_USER_ASIDS ASID_FIRST_VERSION 38*a3a5b763SYunfeng Ye #define ctxid2asid(asid) ((asid) & ~ASID_MASK) 39*a3a5b763SYunfeng Ye #define asid2ctxid(asid, genid) ((asid) | (genid)) 405aec715dSWill Deacon 41038dc9c6SSuzuki K Poulose /* Get the ASIDBits supported by the current CPU */ 42038dc9c6SSuzuki K Poulose static u32 get_cpu_asid_bits(void) 43038dc9c6SSuzuki K Poulose { 44038dc9c6SSuzuki K Poulose u32 asid; 451cc6ed90SMark Rutland int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1), 46038dc9c6SSuzuki K Poulose ID_AA64MMFR0_ASID_SHIFT); 47038dc9c6SSuzuki K Poulose 48038dc9c6SSuzuki K Poulose switch (fld) { 49038dc9c6SSuzuki K Poulose default: 50038dc9c6SSuzuki K Poulose pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n", 51038dc9c6SSuzuki K Poulose smp_processor_id(), fld); 52df561f66SGustavo A. R. Silva fallthrough; 53038dc9c6SSuzuki K Poulose case 0: 54038dc9c6SSuzuki K Poulose asid = 8; 55038dc9c6SSuzuki K Poulose break; 56038dc9c6SSuzuki K Poulose case 2: 57038dc9c6SSuzuki K Poulose asid = 16; 58038dc9c6SSuzuki K Poulose } 59038dc9c6SSuzuki K Poulose 60038dc9c6SSuzuki K Poulose return asid; 61038dc9c6SSuzuki K Poulose } 62038dc9c6SSuzuki K Poulose 6313f417f3SSuzuki K Poulose /* Check if the current cpu's ASIDBits is compatible with asid_bits */ 6413f417f3SSuzuki K Poulose void verify_cpu_asid_bits(void) 6513f417f3SSuzuki K Poulose { 6613f417f3SSuzuki K Poulose u32 asid = get_cpu_asid_bits(); 6713f417f3SSuzuki K Poulose 6813f417f3SSuzuki K Poulose if (asid < asid_bits) { 6913f417f3SSuzuki K Poulose /* 7013f417f3SSuzuki K Poulose * We cannot decrease the ASID size at runtime, so panic if we support 7113f417f3SSuzuki K Poulose * fewer ASID bits than the boot CPU. 7213f417f3SSuzuki K Poulose */ 7313f417f3SSuzuki K Poulose pr_crit("CPU%d: smaller ASID size(%u) than boot CPU (%u)\n", 7413f417f3SSuzuki K Poulose smp_processor_id(), asid, asid_bits); 7517eebd1aSSuzuki K Poulose cpu_panic_kernel(); 7613f417f3SSuzuki K Poulose } 7713f417f3SSuzuki K Poulose } 7813f417f3SSuzuki K Poulose 7948118151SJean-Philippe Brucker static void set_kpti_asid_bits(unsigned long *map) 80f88f42f8SVladimir Murzin { 81f88f42f8SVladimir Murzin unsigned int len = BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(unsigned long); 82f88f42f8SVladimir Murzin /* 83f88f42f8SVladimir Murzin * In case of KPTI kernel/user ASIDs are allocated in 84f88f42f8SVladimir Murzin * pairs, the bottom bit distinguishes the two: if it 85f88f42f8SVladimir Murzin * is set, then the ASID will map only userspace. Thus 86f88f42f8SVladimir Murzin * mark even as reserved for kernel. 87f88f42f8SVladimir Murzin */ 8848118151SJean-Philippe Brucker memset(map, 0xaa, len); 89f88f42f8SVladimir Murzin } 90f88f42f8SVladimir Murzin 91f88f42f8SVladimir Murzin static void set_reserved_asid_bits(void) 92f88f42f8SVladimir Murzin { 9348118151SJean-Philippe Brucker if (pinned_asid_map) 9448118151SJean-Philippe Brucker bitmap_copy(asid_map, pinned_asid_map, NUM_USER_ASIDS); 9548118151SJean-Philippe Brucker else if (arm64_kernel_unmapped_at_el0()) 9648118151SJean-Philippe Brucker set_kpti_asid_bits(asid_map); 97f88f42f8SVladimir Murzin else 98f88f42f8SVladimir Murzin bitmap_clear(asid_map, 0, NUM_USER_ASIDS); 99f88f42f8SVladimir Murzin } 100f88f42f8SVladimir Murzin 1014fc92254SJean-Philippe Brucker #define asid_gen_match(asid) \ 1024fc92254SJean-Philippe Brucker (!(((asid) ^ atomic64_read(&asid_generation)) >> asid_bits)) 1034fc92254SJean-Philippe Brucker 104742fafa5SShaokun Zhang static void flush_context(void) 1055aec715dSWill Deacon { 1065aec715dSWill Deacon int i; 1075aec715dSWill Deacon u64 asid; 1085aec715dSWill Deacon 1095aec715dSWill Deacon /* Update the list of reserved ASIDs and the ASID bitmap. */ 110f88f42f8SVladimir Murzin set_reserved_asid_bits(); 111b3901d54SCatalin Marinas 1125aec715dSWill Deacon for_each_possible_cpu(i) { 1135aec715dSWill Deacon asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0); 1145aec715dSWill Deacon /* 1155aec715dSWill Deacon * If this CPU has already been through a 1165aec715dSWill Deacon * rollover, but hasn't run another task in 1175aec715dSWill Deacon * the meantime, we must preserve its reserved 1185aec715dSWill Deacon * ASID, as this is the only trace we have of 1195aec715dSWill Deacon * the process it is still running. 1205aec715dSWill Deacon */ 1215aec715dSWill Deacon if (asid == 0) 1225aec715dSWill Deacon asid = per_cpu(reserved_asids, i); 123*a3a5b763SYunfeng Ye __set_bit(ctxid2asid(asid), asid_map); 1245aec715dSWill Deacon per_cpu(reserved_asids, i) = asid; 125b3901d54SCatalin Marinas } 126b3901d54SCatalin Marinas 127f81a3487SMark Rutland /* 128f81a3487SMark Rutland * Queue a TLB invalidation for each CPU to perform on next 129f81a3487SMark Rutland * context-switch 130f81a3487SMark Rutland */ 1315aec715dSWill Deacon cpumask_setall(&tlb_flush_pending); 132b3901d54SCatalin Marinas } 133b3901d54SCatalin Marinas 1340ebea808SWill Deacon static bool check_update_reserved_asid(u64 asid, u64 newasid) 1355aec715dSWill Deacon { 1365aec715dSWill Deacon int cpu; 1370ebea808SWill Deacon bool hit = false; 1380ebea808SWill Deacon 1390ebea808SWill Deacon /* 1400ebea808SWill Deacon * Iterate over the set of reserved ASIDs looking for a match. 1410ebea808SWill Deacon * If we find one, then we can update our mm to use newasid 1420ebea808SWill Deacon * (i.e. the same ASID in the current generation) but we can't 1430ebea808SWill Deacon * exit the loop early, since we need to ensure that all copies 1440ebea808SWill Deacon * of the old ASID are updated to reflect the mm. Failure to do 1450ebea808SWill Deacon * so could result in us missing the reserved ASID in a future 1460ebea808SWill Deacon * generation. 1470ebea808SWill Deacon */ 1480ebea808SWill Deacon for_each_possible_cpu(cpu) { 1490ebea808SWill Deacon if (per_cpu(reserved_asids, cpu) == asid) { 1500ebea808SWill Deacon hit = true; 1510ebea808SWill Deacon per_cpu(reserved_asids, cpu) = newasid; 1520ebea808SWill Deacon } 1530ebea808SWill Deacon } 1540ebea808SWill Deacon 1550ebea808SWill Deacon return hit; 1565aec715dSWill Deacon } 1575aec715dSWill Deacon 158742fafa5SShaokun Zhang static u64 new_context(struct mm_struct *mm) 1595aec715dSWill Deacon { 1605aec715dSWill Deacon static u32 cur_idx = 1; 1615aec715dSWill Deacon u64 asid = atomic64_read(&mm->context.id); 1625aec715dSWill Deacon u64 generation = atomic64_read(&asid_generation); 1635aec715dSWill Deacon 1645aec715dSWill Deacon if (asid != 0) { 165*a3a5b763SYunfeng Ye u64 newasid = asid2ctxid(ctxid2asid(asid), generation); 1660ebea808SWill Deacon 1675aec715dSWill Deacon /* 1685aec715dSWill Deacon * If our current ASID was active during a rollover, we 1695aec715dSWill Deacon * can continue to use it and this was just a false alarm. 1705aec715dSWill Deacon */ 1710ebea808SWill Deacon if (check_update_reserved_asid(asid, newasid)) 1720ebea808SWill Deacon return newasid; 1735aec715dSWill Deacon 1745aec715dSWill Deacon /* 17548118151SJean-Philippe Brucker * If it is pinned, we can keep using it. Note that reserved 17648118151SJean-Philippe Brucker * takes priority, because even if it is also pinned, we need to 17748118151SJean-Philippe Brucker * update the generation into the reserved_asids. 17848118151SJean-Philippe Brucker */ 17948118151SJean-Philippe Brucker if (refcount_read(&mm->context.pinned)) 18048118151SJean-Philippe Brucker return newasid; 18148118151SJean-Philippe Brucker 18248118151SJean-Philippe Brucker /* 1835aec715dSWill Deacon * We had a valid ASID in a previous life, so try to re-use 1845aec715dSWill Deacon * it if possible. 1855aec715dSWill Deacon */ 186*a3a5b763SYunfeng Ye if (!__test_and_set_bit(ctxid2asid(asid), asid_map)) 1870ebea808SWill Deacon return newasid; 1885aec715dSWill Deacon } 1895aec715dSWill Deacon 1905aec715dSWill Deacon /* 1915aec715dSWill Deacon * Allocate a free ASID. If we can't find one, take a note of the 1920c8ea531SWill Deacon * currently active ASIDs and mark the TLBs as requiring flushes. We 1930c8ea531SWill Deacon * always count from ASID #2 (index 1), as we use ASID #0 when setting 1940c8ea531SWill Deacon * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd 1950c8ea531SWill Deacon * pairs. 1965aec715dSWill Deacon */ 1975aec715dSWill Deacon asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx); 1985aec715dSWill Deacon if (asid != NUM_USER_ASIDS) 1995aec715dSWill Deacon goto set_asid; 2005aec715dSWill Deacon 2015aec715dSWill Deacon /* We're out of ASIDs, so increment the global generation count */ 2025aec715dSWill Deacon generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION, 2035aec715dSWill Deacon &asid_generation); 204742fafa5SShaokun Zhang flush_context(); 2055aec715dSWill Deacon 206f7e0efc9SJean-Philippe Brucker /* We have more ASIDs than CPUs, so this will always succeed */ 2075aec715dSWill Deacon asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1); 2085aec715dSWill Deacon 2095aec715dSWill Deacon set_asid: 2105aec715dSWill Deacon __set_bit(asid, asid_map); 2115aec715dSWill Deacon cur_idx = asid; 212*a3a5b763SYunfeng Ye return asid2ctxid(asid, generation); 2135aec715dSWill Deacon } 2145aec715dSWill Deacon 215c4885bbbSPingfan Liu void check_and_switch_context(struct mm_struct *mm) 216b3901d54SCatalin Marinas { 217b3901d54SCatalin Marinas unsigned long flags; 218c4885bbbSPingfan Liu unsigned int cpu; 219a8ffaaa0SCatalin Marinas u64 asid, old_active_asid; 2205aec715dSWill Deacon 2215ffdfaedSVladimir Murzin if (system_supports_cnp()) 2225ffdfaedSVladimir Murzin cpu_set_reserved_ttbr0(); 2235ffdfaedSVladimir Murzin 2245aec715dSWill Deacon asid = atomic64_read(&mm->context.id); 225b3901d54SCatalin Marinas 226b3901d54SCatalin Marinas /* 2273a33c760SWill Deacon * The memory ordering here is subtle. 228a8ffaaa0SCatalin Marinas * If our active_asids is non-zero and the ASID matches the current 229a8ffaaa0SCatalin Marinas * generation, then we update the active_asids entry with a relaxed 230a8ffaaa0SCatalin Marinas * cmpxchg. Racing with a concurrent rollover means that either: 2313a33c760SWill Deacon * 232a8ffaaa0SCatalin Marinas * - We get a zero back from the cmpxchg and end up waiting on the 2333a33c760SWill Deacon * lock. Taking the lock synchronises with the rollover and so 2343a33c760SWill Deacon * we are forced to see the updated generation. 2353a33c760SWill Deacon * 236a8ffaaa0SCatalin Marinas * - We get a valid ASID back from the cmpxchg, which means the 2373a33c760SWill Deacon * relaxed xchg in flush_context will treat us as reserved 2383a33c760SWill Deacon * because atomic RmWs are totally ordered for a given location. 239b3901d54SCatalin Marinas */ 240c4885bbbSPingfan Liu old_active_asid = atomic64_read(this_cpu_ptr(&active_asids)); 2414fc92254SJean-Philippe Brucker if (old_active_asid && asid_gen_match(asid) && 242c4885bbbSPingfan Liu atomic64_cmpxchg_relaxed(this_cpu_ptr(&active_asids), 243a8ffaaa0SCatalin Marinas old_active_asid, asid)) 2445aec715dSWill Deacon goto switch_mm_fastpath; 245b3901d54SCatalin Marinas 2465aec715dSWill Deacon raw_spin_lock_irqsave(&cpu_asid_lock, flags); 2475aec715dSWill Deacon /* Check that our ASID belongs to the current generation. */ 2485aec715dSWill Deacon asid = atomic64_read(&mm->context.id); 2494fc92254SJean-Philippe Brucker if (!asid_gen_match(asid)) { 250742fafa5SShaokun Zhang asid = new_context(mm); 2515aec715dSWill Deacon atomic64_set(&mm->context.id, asid); 252b3901d54SCatalin Marinas } 253b3901d54SCatalin Marinas 254c4885bbbSPingfan Liu cpu = smp_processor_id(); 2555aec715dSWill Deacon if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) 2565aec715dSWill Deacon local_flush_tlb_all(); 257b3901d54SCatalin Marinas 258c4885bbbSPingfan Liu atomic64_set(this_cpu_ptr(&active_asids), asid); 2595aec715dSWill Deacon raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); 260565630d5SCatalin Marinas 2615aec715dSWill Deacon switch_mm_fastpath: 262a8e4c0a9SMarc Zyngier 263a8e4c0a9SMarc Zyngier arm64_apply_bp_hardening(); 264a8e4c0a9SMarc Zyngier 26539bc88e5SCatalin Marinas /* 26639bc88e5SCatalin Marinas * Defer TTBR0_EL1 setting for user threads to uaccess_enable() when 26739bc88e5SCatalin Marinas * emulating PAN. 26839bc88e5SCatalin Marinas */ 26939bc88e5SCatalin Marinas if (!system_uses_ttbr0_pan()) 270b3901d54SCatalin Marinas cpu_switch_mm(mm->pgd, mm); 271b3901d54SCatalin Marinas } 272b3901d54SCatalin Marinas 27348118151SJean-Philippe Brucker unsigned long arm64_mm_context_get(struct mm_struct *mm) 27448118151SJean-Philippe Brucker { 27548118151SJean-Philippe Brucker unsigned long flags; 27648118151SJean-Philippe Brucker u64 asid; 27748118151SJean-Philippe Brucker 27848118151SJean-Philippe Brucker if (!pinned_asid_map) 27948118151SJean-Philippe Brucker return 0; 28048118151SJean-Philippe Brucker 28148118151SJean-Philippe Brucker raw_spin_lock_irqsave(&cpu_asid_lock, flags); 28248118151SJean-Philippe Brucker 28348118151SJean-Philippe Brucker asid = atomic64_read(&mm->context.id); 28448118151SJean-Philippe Brucker 28548118151SJean-Philippe Brucker if (refcount_inc_not_zero(&mm->context.pinned)) 28648118151SJean-Philippe Brucker goto out_unlock; 28748118151SJean-Philippe Brucker 28848118151SJean-Philippe Brucker if (nr_pinned_asids >= max_pinned_asids) { 28948118151SJean-Philippe Brucker asid = 0; 29048118151SJean-Philippe Brucker goto out_unlock; 29148118151SJean-Philippe Brucker } 29248118151SJean-Philippe Brucker 29348118151SJean-Philippe Brucker if (!asid_gen_match(asid)) { 29448118151SJean-Philippe Brucker /* 29548118151SJean-Philippe Brucker * We went through one or more rollover since that ASID was 29648118151SJean-Philippe Brucker * used. Ensure that it is still valid, or generate a new one. 29748118151SJean-Philippe Brucker */ 29848118151SJean-Philippe Brucker asid = new_context(mm); 29948118151SJean-Philippe Brucker atomic64_set(&mm->context.id, asid); 30048118151SJean-Philippe Brucker } 30148118151SJean-Philippe Brucker 30248118151SJean-Philippe Brucker nr_pinned_asids++; 303*a3a5b763SYunfeng Ye __set_bit(ctxid2asid(asid), pinned_asid_map); 30448118151SJean-Philippe Brucker refcount_set(&mm->context.pinned, 1); 30548118151SJean-Philippe Brucker 30648118151SJean-Philippe Brucker out_unlock: 30748118151SJean-Philippe Brucker raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); 30848118151SJean-Philippe Brucker 309*a3a5b763SYunfeng Ye asid = ctxid2asid(asid); 31048118151SJean-Philippe Brucker 31148118151SJean-Philippe Brucker /* Set the equivalent of USER_ASID_BIT */ 31248118151SJean-Philippe Brucker if (asid && arm64_kernel_unmapped_at_el0()) 31348118151SJean-Philippe Brucker asid |= 1; 31448118151SJean-Philippe Brucker 31548118151SJean-Philippe Brucker return asid; 31648118151SJean-Philippe Brucker } 31748118151SJean-Philippe Brucker EXPORT_SYMBOL_GPL(arm64_mm_context_get); 31848118151SJean-Philippe Brucker 31948118151SJean-Philippe Brucker void arm64_mm_context_put(struct mm_struct *mm) 32048118151SJean-Philippe Brucker { 32148118151SJean-Philippe Brucker unsigned long flags; 32248118151SJean-Philippe Brucker u64 asid = atomic64_read(&mm->context.id); 32348118151SJean-Philippe Brucker 32448118151SJean-Philippe Brucker if (!pinned_asid_map) 32548118151SJean-Philippe Brucker return; 32648118151SJean-Philippe Brucker 32748118151SJean-Philippe Brucker raw_spin_lock_irqsave(&cpu_asid_lock, flags); 32848118151SJean-Philippe Brucker 32948118151SJean-Philippe Brucker if (refcount_dec_and_test(&mm->context.pinned)) { 330*a3a5b763SYunfeng Ye __clear_bit(ctxid2asid(asid), pinned_asid_map); 33148118151SJean-Philippe Brucker nr_pinned_asids--; 33248118151SJean-Philippe Brucker } 33348118151SJean-Philippe Brucker 33448118151SJean-Philippe Brucker raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); 33548118151SJean-Philippe Brucker } 33648118151SJean-Philippe Brucker EXPORT_SYMBOL_GPL(arm64_mm_context_put); 33748118151SJean-Philippe Brucker 33895e3de35SMarc Zyngier /* Errata workaround post TTBRx_EL1 update. */ 33995e3de35SMarc Zyngier asmlinkage void post_ttbr_update_workaround(void) 34095e3de35SMarc Zyngier { 34125b92693SMark Rutland if (!IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) 34225b92693SMark Rutland return; 34325b92693SMark Rutland 34495e3de35SMarc Zyngier asm(ALTERNATIVE("nop; nop; nop", 34595e3de35SMarc Zyngier "ic iallu; dsb nsh; isb", 34625b92693SMark Rutland ARM64_WORKAROUND_CAVIUM_27456)); 34725b92693SMark Rutland } 34825b92693SMark Rutland 34925b92693SMark Rutland void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm) 35025b92693SMark Rutland { 35125b92693SMark Rutland unsigned long ttbr1 = read_sysreg(ttbr1_el1); 35225b92693SMark Rutland unsigned long asid = ASID(mm); 35325b92693SMark Rutland unsigned long ttbr0 = phys_to_ttbr(pgd_phys); 35425b92693SMark Rutland 35525b92693SMark Rutland /* Skip CNP for the reserved ASID */ 35625b92693SMark Rutland if (system_supports_cnp() && asid) 35725b92693SMark Rutland ttbr0 |= TTBR_CNP_BIT; 35825b92693SMark Rutland 35925b92693SMark Rutland /* SW PAN needs a copy of the ASID in TTBR0 for entry */ 36025b92693SMark Rutland if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN)) 36125b92693SMark Rutland ttbr0 |= FIELD_PREP(TTBR_ASID_MASK, asid); 36225b92693SMark Rutland 36325b92693SMark Rutland /* Set ASID in TTBR1 since TCR.A1 is set */ 36425b92693SMark Rutland ttbr1 &= ~TTBR_ASID_MASK; 36525b92693SMark Rutland ttbr1 |= FIELD_PREP(TTBR_ASID_MASK, asid); 36625b92693SMark Rutland 36725b92693SMark Rutland write_sysreg(ttbr1, ttbr1_el1); 36825b92693SMark Rutland isb(); 36925b92693SMark Rutland write_sysreg(ttbr0, ttbr0_el1); 37025b92693SMark Rutland isb(); 37125b92693SMark Rutland post_ttbr_update_workaround(); 37295e3de35SMarc Zyngier } 37395e3de35SMarc Zyngier 3749abd515aSJean-Philippe Brucker static int asids_update_limit(void) 375b3901d54SCatalin Marinas { 3769abd515aSJean-Philippe Brucker unsigned long num_available_asids = NUM_USER_ASIDS; 3779abd515aSJean-Philippe Brucker 37848118151SJean-Philippe Brucker if (arm64_kernel_unmapped_at_el0()) { 3799abd515aSJean-Philippe Brucker num_available_asids /= 2; 38048118151SJean-Philippe Brucker if (pinned_asid_map) 38148118151SJean-Philippe Brucker set_kpti_asid_bits(pinned_asid_map); 38248118151SJean-Philippe Brucker } 383f7e0efc9SJean-Philippe Brucker /* 384f7e0efc9SJean-Philippe Brucker * Expect allocation after rollover to fail if we don't have at least 385f7e0efc9SJean-Philippe Brucker * one more ASID than CPUs. ASID #0 is reserved for init_mm. 386f7e0efc9SJean-Philippe Brucker */ 3879abd515aSJean-Philippe Brucker WARN_ON(num_available_asids - 1 <= num_possible_cpus()); 3889abd515aSJean-Philippe Brucker pr_info("ASID allocator initialised with %lu entries\n", 3899abd515aSJean-Philippe Brucker num_available_asids); 39048118151SJean-Philippe Brucker 39148118151SJean-Philippe Brucker /* 39248118151SJean-Philippe Brucker * There must always be an ASID available after rollover. Ensure that, 39348118151SJean-Philippe Brucker * even if all CPUs have a reserved ASID and the maximum number of ASIDs 39448118151SJean-Philippe Brucker * are pinned, there still is at least one empty slot in the ASID map. 39548118151SJean-Philippe Brucker */ 39648118151SJean-Philippe Brucker max_pinned_asids = num_available_asids - num_possible_cpus() - 2; 3979abd515aSJean-Philippe Brucker return 0; 3989abd515aSJean-Philippe Brucker } 3999abd515aSJean-Philippe Brucker arch_initcall(asids_update_limit); 4009abd515aSJean-Philippe Brucker 4019abd515aSJean-Philippe Brucker static int asids_init(void) 4029abd515aSJean-Philippe Brucker { 4039abd515aSJean-Philippe Brucker asid_bits = get_cpu_asid_bits(); 4045aec715dSWill Deacon atomic64_set(&asid_generation, ASID_FIRST_VERSION); 4055ae632edSKefeng Wang asid_map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); 4065aec715dSWill Deacon if (!asid_map) 4075aec715dSWill Deacon panic("Failed to allocate bitmap for %lu ASIDs\n", 4085aec715dSWill Deacon NUM_USER_ASIDS); 4095aec715dSWill Deacon 4105ae632edSKefeng Wang pinned_asid_map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); 41148118151SJean-Philippe Brucker nr_pinned_asids = 0; 41248118151SJean-Philippe Brucker 413f88f42f8SVladimir Murzin /* 414f88f42f8SVladimir Murzin * We cannot call set_reserved_asid_bits() here because CPU 415f88f42f8SVladimir Murzin * caps are not finalized yet, so it is safer to assume KPTI 416f88f42f8SVladimir Murzin * and reserve kernel ASID's from beginning. 417f88f42f8SVladimir Murzin */ 418f88f42f8SVladimir Murzin if (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) 41948118151SJean-Philippe Brucker set_kpti_asid_bits(asid_map); 4205aec715dSWill Deacon return 0; 421b3901d54SCatalin Marinas } 4225aec715dSWill Deacon early_initcall(asids_init); 423