1b3901d54SCatalin Marinas /* 2b3901d54SCatalin Marinas * Based on arch/arm/mm/context.c 3b3901d54SCatalin Marinas * 4b3901d54SCatalin Marinas * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved. 5b3901d54SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 6b3901d54SCatalin Marinas * 7b3901d54SCatalin Marinas * This program is free software; you can redistribute it and/or modify 8b3901d54SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 9b3901d54SCatalin Marinas * published by the Free Software Foundation. 10b3901d54SCatalin Marinas * 11b3901d54SCatalin Marinas * This program is distributed in the hope that it will be useful, 12b3901d54SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 13b3901d54SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14b3901d54SCatalin Marinas * GNU General Public License for more details. 15b3901d54SCatalin Marinas * 16b3901d54SCatalin Marinas * You should have received a copy of the GNU General Public License 17b3901d54SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 18b3901d54SCatalin Marinas */ 19b3901d54SCatalin Marinas 205aec715dSWill Deacon #include <linux/bitops.h> 21b3901d54SCatalin Marinas #include <linux/sched.h> 225aec715dSWill Deacon #include <linux/slab.h> 23b3901d54SCatalin Marinas #include <linux/mm.h> 24b3901d54SCatalin Marinas 255aec715dSWill Deacon #include <asm/cpufeature.h> 26b3901d54SCatalin Marinas #include <asm/mmu_context.h> 2713f417f3SSuzuki K Poulose #include <asm/smp.h> 28b3901d54SCatalin Marinas #include <asm/tlbflush.h> 29b3901d54SCatalin Marinas 305aec715dSWill Deacon static u32 asid_bits; 31b3901d54SCatalin Marinas static DEFINE_RAW_SPINLOCK(cpu_asid_lock); 325aec715dSWill Deacon 335aec715dSWill Deacon static atomic64_t asid_generation; 345aec715dSWill Deacon static unsigned long *asid_map; 355aec715dSWill Deacon 365aec715dSWill Deacon static DEFINE_PER_CPU(atomic64_t, active_asids); 375aec715dSWill Deacon static DEFINE_PER_CPU(u64, reserved_asids); 385aec715dSWill Deacon static cpumask_t tlb_flush_pending; 395aec715dSWill Deacon 405aec715dSWill Deacon #define ASID_MASK (~GENMASK(asid_bits - 1, 0)) 415aec715dSWill Deacon #define ASID_FIRST_VERSION (1UL << asid_bits) 420c8ea531SWill Deacon 430c8ea531SWill Deacon #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 440c8ea531SWill Deacon #define NUM_USER_ASIDS (ASID_FIRST_VERSION >> 1) 450c8ea531SWill Deacon #define asid2idx(asid) (((asid) & ~ASID_MASK) >> 1) 460c8ea531SWill Deacon #define idx2asid(idx) (((idx) << 1) & ~ASID_MASK) 470c8ea531SWill Deacon #else 480c8ea531SWill Deacon #define NUM_USER_ASIDS (ASID_FIRST_VERSION) 490c8ea531SWill Deacon #define asid2idx(asid) ((asid) & ~ASID_MASK) 500c8ea531SWill Deacon #define idx2asid(idx) asid2idx(idx) 510c8ea531SWill Deacon #endif 525aec715dSWill Deacon 53038dc9c6SSuzuki K Poulose /* Get the ASIDBits supported by the current CPU */ 54038dc9c6SSuzuki K Poulose static u32 get_cpu_asid_bits(void) 55038dc9c6SSuzuki K Poulose { 56038dc9c6SSuzuki K Poulose u32 asid; 571cc6ed90SMark Rutland int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1), 58038dc9c6SSuzuki K Poulose ID_AA64MMFR0_ASID_SHIFT); 59038dc9c6SSuzuki K Poulose 60038dc9c6SSuzuki K Poulose switch (fld) { 61038dc9c6SSuzuki K Poulose default: 62038dc9c6SSuzuki K Poulose pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n", 63038dc9c6SSuzuki K Poulose smp_processor_id(), fld); 64038dc9c6SSuzuki K Poulose /* Fallthrough */ 65038dc9c6SSuzuki K Poulose case 0: 66038dc9c6SSuzuki K Poulose asid = 8; 67038dc9c6SSuzuki K Poulose break; 68038dc9c6SSuzuki K Poulose case 2: 69038dc9c6SSuzuki K Poulose asid = 16; 70038dc9c6SSuzuki K Poulose } 71038dc9c6SSuzuki K Poulose 72038dc9c6SSuzuki K Poulose return asid; 73038dc9c6SSuzuki K Poulose } 74038dc9c6SSuzuki K Poulose 7513f417f3SSuzuki K Poulose /* Check if the current cpu's ASIDBits is compatible with asid_bits */ 7613f417f3SSuzuki K Poulose void verify_cpu_asid_bits(void) 7713f417f3SSuzuki K Poulose { 7813f417f3SSuzuki K Poulose u32 asid = get_cpu_asid_bits(); 7913f417f3SSuzuki K Poulose 8013f417f3SSuzuki K Poulose if (asid < asid_bits) { 8113f417f3SSuzuki K Poulose /* 8213f417f3SSuzuki K Poulose * We cannot decrease the ASID size at runtime, so panic if we support 8313f417f3SSuzuki K Poulose * fewer ASID bits than the boot CPU. 8413f417f3SSuzuki K Poulose */ 8513f417f3SSuzuki K Poulose pr_crit("CPU%d: smaller ASID size(%u) than boot CPU (%u)\n", 8613f417f3SSuzuki K Poulose smp_processor_id(), asid, asid_bits); 8717eebd1aSSuzuki K Poulose cpu_panic_kernel(); 8813f417f3SSuzuki K Poulose } 8913f417f3SSuzuki K Poulose } 9013f417f3SSuzuki K Poulose 91742fafa5SShaokun Zhang static void flush_context(void) 925aec715dSWill Deacon { 935aec715dSWill Deacon int i; 945aec715dSWill Deacon u64 asid; 955aec715dSWill Deacon 965aec715dSWill Deacon /* Update the list of reserved ASIDs and the ASID bitmap. */ 975aec715dSWill Deacon bitmap_clear(asid_map, 0, NUM_USER_ASIDS); 98b3901d54SCatalin Marinas 995aec715dSWill Deacon for_each_possible_cpu(i) { 1005aec715dSWill Deacon asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0); 1015aec715dSWill Deacon /* 1025aec715dSWill Deacon * If this CPU has already been through a 1035aec715dSWill Deacon * rollover, but hasn't run another task in 1045aec715dSWill Deacon * the meantime, we must preserve its reserved 1055aec715dSWill Deacon * ASID, as this is the only trace we have of 1065aec715dSWill Deacon * the process it is still running. 1075aec715dSWill Deacon */ 1085aec715dSWill Deacon if (asid == 0) 1095aec715dSWill Deacon asid = per_cpu(reserved_asids, i); 1100c8ea531SWill Deacon __set_bit(asid2idx(asid), asid_map); 1115aec715dSWill Deacon per_cpu(reserved_asids, i) = asid; 112b3901d54SCatalin Marinas } 113b3901d54SCatalin Marinas 114f81a3487SMark Rutland /* 115f81a3487SMark Rutland * Queue a TLB invalidation for each CPU to perform on next 116f81a3487SMark Rutland * context-switch 117f81a3487SMark Rutland */ 1185aec715dSWill Deacon cpumask_setall(&tlb_flush_pending); 119b3901d54SCatalin Marinas } 120b3901d54SCatalin Marinas 1210ebea808SWill Deacon static bool check_update_reserved_asid(u64 asid, u64 newasid) 1225aec715dSWill Deacon { 1235aec715dSWill Deacon int cpu; 1240ebea808SWill Deacon bool hit = false; 1250ebea808SWill Deacon 1260ebea808SWill Deacon /* 1270ebea808SWill Deacon * Iterate over the set of reserved ASIDs looking for a match. 1280ebea808SWill Deacon * If we find one, then we can update our mm to use newasid 1290ebea808SWill Deacon * (i.e. the same ASID in the current generation) but we can't 1300ebea808SWill Deacon * exit the loop early, since we need to ensure that all copies 1310ebea808SWill Deacon * of the old ASID are updated to reflect the mm. Failure to do 1320ebea808SWill Deacon * so could result in us missing the reserved ASID in a future 1330ebea808SWill Deacon * generation. 1340ebea808SWill Deacon */ 1350ebea808SWill Deacon for_each_possible_cpu(cpu) { 1360ebea808SWill Deacon if (per_cpu(reserved_asids, cpu) == asid) { 1370ebea808SWill Deacon hit = true; 1380ebea808SWill Deacon per_cpu(reserved_asids, cpu) = newasid; 1390ebea808SWill Deacon } 1400ebea808SWill Deacon } 1410ebea808SWill Deacon 1420ebea808SWill Deacon return hit; 1435aec715dSWill Deacon } 1445aec715dSWill Deacon 145742fafa5SShaokun Zhang static u64 new_context(struct mm_struct *mm) 1465aec715dSWill Deacon { 1475aec715dSWill Deacon static u32 cur_idx = 1; 1485aec715dSWill Deacon u64 asid = atomic64_read(&mm->context.id); 1495aec715dSWill Deacon u64 generation = atomic64_read(&asid_generation); 1505aec715dSWill Deacon 1515aec715dSWill Deacon if (asid != 0) { 1520ebea808SWill Deacon u64 newasid = generation | (asid & ~ASID_MASK); 1530ebea808SWill Deacon 1545aec715dSWill Deacon /* 1555aec715dSWill Deacon * If our current ASID was active during a rollover, we 1565aec715dSWill Deacon * can continue to use it and this was just a false alarm. 1575aec715dSWill Deacon */ 1580ebea808SWill Deacon if (check_update_reserved_asid(asid, newasid)) 1590ebea808SWill Deacon return newasid; 1605aec715dSWill Deacon 1615aec715dSWill Deacon /* 1625aec715dSWill Deacon * We had a valid ASID in a previous life, so try to re-use 1635aec715dSWill Deacon * it if possible. 1645aec715dSWill Deacon */ 1650c8ea531SWill Deacon if (!__test_and_set_bit(asid2idx(asid), asid_map)) 1660ebea808SWill Deacon return newasid; 1675aec715dSWill Deacon } 1685aec715dSWill Deacon 1695aec715dSWill Deacon /* 1705aec715dSWill Deacon * Allocate a free ASID. If we can't find one, take a note of the 1710c8ea531SWill Deacon * currently active ASIDs and mark the TLBs as requiring flushes. We 1720c8ea531SWill Deacon * always count from ASID #2 (index 1), as we use ASID #0 when setting 1730c8ea531SWill Deacon * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd 1740c8ea531SWill Deacon * pairs. 1755aec715dSWill Deacon */ 1765aec715dSWill Deacon asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx); 1775aec715dSWill Deacon if (asid != NUM_USER_ASIDS) 1785aec715dSWill Deacon goto set_asid; 1795aec715dSWill Deacon 1805aec715dSWill Deacon /* We're out of ASIDs, so increment the global generation count */ 1815aec715dSWill Deacon generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION, 1825aec715dSWill Deacon &asid_generation); 183742fafa5SShaokun Zhang flush_context(); 1845aec715dSWill Deacon 185f7e0efc9SJean-Philippe Brucker /* We have more ASIDs than CPUs, so this will always succeed */ 1865aec715dSWill Deacon asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1); 1875aec715dSWill Deacon 1885aec715dSWill Deacon set_asid: 1895aec715dSWill Deacon __set_bit(asid, asid_map); 1905aec715dSWill Deacon cur_idx = asid; 1910c8ea531SWill Deacon return idx2asid(asid) | generation; 1925aec715dSWill Deacon } 1935aec715dSWill Deacon 1945aec715dSWill Deacon void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) 195b3901d54SCatalin Marinas { 196b3901d54SCatalin Marinas unsigned long flags; 197a8ffaaa0SCatalin Marinas u64 asid, old_active_asid; 1985aec715dSWill Deacon 1995ffdfaedSVladimir Murzin if (system_supports_cnp()) 2005ffdfaedSVladimir Murzin cpu_set_reserved_ttbr0(); 2015ffdfaedSVladimir Murzin 2025aec715dSWill Deacon asid = atomic64_read(&mm->context.id); 203b3901d54SCatalin Marinas 204b3901d54SCatalin Marinas /* 2053a33c760SWill Deacon * The memory ordering here is subtle. 206a8ffaaa0SCatalin Marinas * If our active_asids is non-zero and the ASID matches the current 207a8ffaaa0SCatalin Marinas * generation, then we update the active_asids entry with a relaxed 208a8ffaaa0SCatalin Marinas * cmpxchg. Racing with a concurrent rollover means that either: 2093a33c760SWill Deacon * 210a8ffaaa0SCatalin Marinas * - We get a zero back from the cmpxchg and end up waiting on the 2113a33c760SWill Deacon * lock. Taking the lock synchronises with the rollover and so 2123a33c760SWill Deacon * we are forced to see the updated generation. 2133a33c760SWill Deacon * 214a8ffaaa0SCatalin Marinas * - We get a valid ASID back from the cmpxchg, which means the 2153a33c760SWill Deacon * relaxed xchg in flush_context will treat us as reserved 2163a33c760SWill Deacon * because atomic RmWs are totally ordered for a given location. 217b3901d54SCatalin Marinas */ 218a8ffaaa0SCatalin Marinas old_active_asid = atomic64_read(&per_cpu(active_asids, cpu)); 219a8ffaaa0SCatalin Marinas if (old_active_asid && 220a8ffaaa0SCatalin Marinas !((asid ^ atomic64_read(&asid_generation)) >> asid_bits) && 221a8ffaaa0SCatalin Marinas atomic64_cmpxchg_relaxed(&per_cpu(active_asids, cpu), 222a8ffaaa0SCatalin Marinas old_active_asid, asid)) 2235aec715dSWill Deacon goto switch_mm_fastpath; 224b3901d54SCatalin Marinas 2255aec715dSWill Deacon raw_spin_lock_irqsave(&cpu_asid_lock, flags); 2265aec715dSWill Deacon /* Check that our ASID belongs to the current generation. */ 2275aec715dSWill Deacon asid = atomic64_read(&mm->context.id); 2285aec715dSWill Deacon if ((asid ^ atomic64_read(&asid_generation)) >> asid_bits) { 229742fafa5SShaokun Zhang asid = new_context(mm); 2305aec715dSWill Deacon atomic64_set(&mm->context.id, asid); 231b3901d54SCatalin Marinas } 232b3901d54SCatalin Marinas 2335aec715dSWill Deacon if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) 2345aec715dSWill Deacon local_flush_tlb_all(); 235b3901d54SCatalin Marinas 2365aec715dSWill Deacon atomic64_set(&per_cpu(active_asids, cpu), asid); 2375aec715dSWill Deacon raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); 238565630d5SCatalin Marinas 2395aec715dSWill Deacon switch_mm_fastpath: 240a8e4c0a9SMarc Zyngier 241a8e4c0a9SMarc Zyngier arm64_apply_bp_hardening(); 242a8e4c0a9SMarc Zyngier 24339bc88e5SCatalin Marinas /* 24439bc88e5SCatalin Marinas * Defer TTBR0_EL1 setting for user threads to uaccess_enable() when 24539bc88e5SCatalin Marinas * emulating PAN. 24639bc88e5SCatalin Marinas */ 24739bc88e5SCatalin Marinas if (!system_uses_ttbr0_pan()) 248b3901d54SCatalin Marinas cpu_switch_mm(mm->pgd, mm); 249b3901d54SCatalin Marinas } 250b3901d54SCatalin Marinas 25195e3de35SMarc Zyngier /* Errata workaround post TTBRx_EL1 update. */ 25295e3de35SMarc Zyngier asmlinkage void post_ttbr_update_workaround(void) 25395e3de35SMarc Zyngier { 25495e3de35SMarc Zyngier asm(ALTERNATIVE("nop; nop; nop", 25595e3de35SMarc Zyngier "ic iallu; dsb nsh; isb", 25695e3de35SMarc Zyngier ARM64_WORKAROUND_CAVIUM_27456, 25795e3de35SMarc Zyngier CONFIG_CAVIUM_ERRATUM_27456)); 25895e3de35SMarc Zyngier } 25995e3de35SMarc Zyngier 2605aec715dSWill Deacon static int asids_init(void) 261b3901d54SCatalin Marinas { 262038dc9c6SSuzuki K Poulose asid_bits = get_cpu_asid_bits(); 263f7e0efc9SJean-Philippe Brucker /* 264f7e0efc9SJean-Philippe Brucker * Expect allocation after rollover to fail if we don't have at least 265f7e0efc9SJean-Philippe Brucker * one more ASID than CPUs. ASID #0 is reserved for init_mm. 266f7e0efc9SJean-Philippe Brucker */ 267f7e0efc9SJean-Philippe Brucker WARN_ON(NUM_USER_ASIDS - 1 <= num_possible_cpus()); 2685aec715dSWill Deacon atomic64_set(&asid_generation, ASID_FIRST_VERSION); 2696396bb22SKees Cook asid_map = kcalloc(BITS_TO_LONGS(NUM_USER_ASIDS), sizeof(*asid_map), 2705aec715dSWill Deacon GFP_KERNEL); 2715aec715dSWill Deacon if (!asid_map) 2725aec715dSWill Deacon panic("Failed to allocate bitmap for %lu ASIDs\n", 2735aec715dSWill Deacon NUM_USER_ASIDS); 2745aec715dSWill Deacon 2755aec715dSWill Deacon pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS); 2765aec715dSWill Deacon return 0; 277b3901d54SCatalin Marinas } 2785aec715dSWill Deacon early_initcall(asids_init); 279