1b3901d54SCatalin Marinas /* 2b3901d54SCatalin Marinas * Based on arch/arm/mm/context.c 3b3901d54SCatalin Marinas * 4b3901d54SCatalin Marinas * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved. 5b3901d54SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 6b3901d54SCatalin Marinas * 7b3901d54SCatalin Marinas * This program is free software; you can redistribute it and/or modify 8b3901d54SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 9b3901d54SCatalin Marinas * published by the Free Software Foundation. 10b3901d54SCatalin Marinas * 11b3901d54SCatalin Marinas * This program is distributed in the hope that it will be useful, 12b3901d54SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 13b3901d54SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14b3901d54SCatalin Marinas * GNU General Public License for more details. 15b3901d54SCatalin Marinas * 16b3901d54SCatalin Marinas * You should have received a copy of the GNU General Public License 17b3901d54SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 18b3901d54SCatalin Marinas */ 19b3901d54SCatalin Marinas 205aec715dSWill Deacon #include <linux/bitops.h> 21b3901d54SCatalin Marinas #include <linux/sched.h> 225aec715dSWill Deacon #include <linux/slab.h> 23b3901d54SCatalin Marinas #include <linux/mm.h> 24b3901d54SCatalin Marinas 255aec715dSWill Deacon #include <asm/cpufeature.h> 26b3901d54SCatalin Marinas #include <asm/mmu_context.h> 2713f417f3SSuzuki K Poulose #include <asm/smp.h> 28b3901d54SCatalin Marinas #include <asm/tlbflush.h> 29b3901d54SCatalin Marinas 305aec715dSWill Deacon static u32 asid_bits; 31b3901d54SCatalin Marinas static DEFINE_RAW_SPINLOCK(cpu_asid_lock); 325aec715dSWill Deacon 335aec715dSWill Deacon static atomic64_t asid_generation; 345aec715dSWill Deacon static unsigned long *asid_map; 355aec715dSWill Deacon 365aec715dSWill Deacon static DEFINE_PER_CPU(atomic64_t, active_asids); 375aec715dSWill Deacon static DEFINE_PER_CPU(u64, reserved_asids); 385aec715dSWill Deacon static cpumask_t tlb_flush_pending; 395aec715dSWill Deacon 405aec715dSWill Deacon #define ASID_MASK (~GENMASK(asid_bits - 1, 0)) 415aec715dSWill Deacon #define ASID_FIRST_VERSION (1UL << asid_bits) 425aec715dSWill Deacon #define NUM_USER_ASIDS ASID_FIRST_VERSION 435aec715dSWill Deacon 44038dc9c6SSuzuki K Poulose /* Get the ASIDBits supported by the current CPU */ 45038dc9c6SSuzuki K Poulose static u32 get_cpu_asid_bits(void) 46038dc9c6SSuzuki K Poulose { 47038dc9c6SSuzuki K Poulose u32 asid; 481cc6ed90SMark Rutland int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1), 49038dc9c6SSuzuki K Poulose ID_AA64MMFR0_ASID_SHIFT); 50038dc9c6SSuzuki K Poulose 51038dc9c6SSuzuki K Poulose switch (fld) { 52038dc9c6SSuzuki K Poulose default: 53038dc9c6SSuzuki K Poulose pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n", 54038dc9c6SSuzuki K Poulose smp_processor_id(), fld); 55038dc9c6SSuzuki K Poulose /* Fallthrough */ 56038dc9c6SSuzuki K Poulose case 0: 57038dc9c6SSuzuki K Poulose asid = 8; 58038dc9c6SSuzuki K Poulose break; 59038dc9c6SSuzuki K Poulose case 2: 60038dc9c6SSuzuki K Poulose asid = 16; 61038dc9c6SSuzuki K Poulose } 62038dc9c6SSuzuki K Poulose 63038dc9c6SSuzuki K Poulose return asid; 64038dc9c6SSuzuki K Poulose } 65038dc9c6SSuzuki K Poulose 6613f417f3SSuzuki K Poulose /* Check if the current cpu's ASIDBits is compatible with asid_bits */ 6713f417f3SSuzuki K Poulose void verify_cpu_asid_bits(void) 6813f417f3SSuzuki K Poulose { 6913f417f3SSuzuki K Poulose u32 asid = get_cpu_asid_bits(); 7013f417f3SSuzuki K Poulose 7113f417f3SSuzuki K Poulose if (asid < asid_bits) { 7213f417f3SSuzuki K Poulose /* 7313f417f3SSuzuki K Poulose * We cannot decrease the ASID size at runtime, so panic if we support 7413f417f3SSuzuki K Poulose * fewer ASID bits than the boot CPU. 7513f417f3SSuzuki K Poulose */ 7613f417f3SSuzuki K Poulose pr_crit("CPU%d: smaller ASID size(%u) than boot CPU (%u)\n", 7713f417f3SSuzuki K Poulose smp_processor_id(), asid, asid_bits); 7813f417f3SSuzuki K Poulose update_cpu_boot_status(CPU_PANIC_KERNEL); 7913f417f3SSuzuki K Poulose cpu_park_loop(); 8013f417f3SSuzuki K Poulose } 8113f417f3SSuzuki K Poulose } 8213f417f3SSuzuki K Poulose 835aec715dSWill Deacon static void flush_context(unsigned int cpu) 845aec715dSWill Deacon { 855aec715dSWill Deacon int i; 865aec715dSWill Deacon u64 asid; 875aec715dSWill Deacon 885aec715dSWill Deacon /* Update the list of reserved ASIDs and the ASID bitmap. */ 895aec715dSWill Deacon bitmap_clear(asid_map, 0, NUM_USER_ASIDS); 90b3901d54SCatalin Marinas 91b3901d54SCatalin Marinas /* 925aec715dSWill Deacon * Ensure the generation bump is observed before we xchg the 935aec715dSWill Deacon * active_asids. 94b3901d54SCatalin Marinas */ 955aec715dSWill Deacon smp_wmb(); 965aec715dSWill Deacon 975aec715dSWill Deacon for_each_possible_cpu(i) { 985aec715dSWill Deacon asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0); 995aec715dSWill Deacon /* 1005aec715dSWill Deacon * If this CPU has already been through a 1015aec715dSWill Deacon * rollover, but hasn't run another task in 1025aec715dSWill Deacon * the meantime, we must preserve its reserved 1035aec715dSWill Deacon * ASID, as this is the only trace we have of 1045aec715dSWill Deacon * the process it is still running. 1055aec715dSWill Deacon */ 1065aec715dSWill Deacon if (asid == 0) 1075aec715dSWill Deacon asid = per_cpu(reserved_asids, i); 1085aec715dSWill Deacon __set_bit(asid & ~ASID_MASK, asid_map); 1095aec715dSWill Deacon per_cpu(reserved_asids, i) = asid; 110b3901d54SCatalin Marinas } 111b3901d54SCatalin Marinas 1125aec715dSWill Deacon /* Queue a TLB invalidate and flush the I-cache if necessary. */ 1135aec715dSWill Deacon cpumask_setall(&tlb_flush_pending); 1145aec715dSWill Deacon 115b3901d54SCatalin Marinas if (icache_is_aivivt()) 1165aec715dSWill Deacon __flush_icache_all(); 117b3901d54SCatalin Marinas } 118b3901d54SCatalin Marinas 1190ebea808SWill Deacon static bool check_update_reserved_asid(u64 asid, u64 newasid) 1205aec715dSWill Deacon { 1215aec715dSWill Deacon int cpu; 1220ebea808SWill Deacon bool hit = false; 1230ebea808SWill Deacon 1240ebea808SWill Deacon /* 1250ebea808SWill Deacon * Iterate over the set of reserved ASIDs looking for a match. 1260ebea808SWill Deacon * If we find one, then we can update our mm to use newasid 1270ebea808SWill Deacon * (i.e. the same ASID in the current generation) but we can't 1280ebea808SWill Deacon * exit the loop early, since we need to ensure that all copies 1290ebea808SWill Deacon * of the old ASID are updated to reflect the mm. Failure to do 1300ebea808SWill Deacon * so could result in us missing the reserved ASID in a future 1310ebea808SWill Deacon * generation. 1320ebea808SWill Deacon */ 1330ebea808SWill Deacon for_each_possible_cpu(cpu) { 1340ebea808SWill Deacon if (per_cpu(reserved_asids, cpu) == asid) { 1350ebea808SWill Deacon hit = true; 1360ebea808SWill Deacon per_cpu(reserved_asids, cpu) = newasid; 1370ebea808SWill Deacon } 1380ebea808SWill Deacon } 1390ebea808SWill Deacon 1400ebea808SWill Deacon return hit; 1415aec715dSWill Deacon } 1425aec715dSWill Deacon 1435aec715dSWill Deacon static u64 new_context(struct mm_struct *mm, unsigned int cpu) 1445aec715dSWill Deacon { 1455aec715dSWill Deacon static u32 cur_idx = 1; 1465aec715dSWill Deacon u64 asid = atomic64_read(&mm->context.id); 1475aec715dSWill Deacon u64 generation = atomic64_read(&asid_generation); 1485aec715dSWill Deacon 1495aec715dSWill Deacon if (asid != 0) { 1500ebea808SWill Deacon u64 newasid = generation | (asid & ~ASID_MASK); 1510ebea808SWill Deacon 1525aec715dSWill Deacon /* 1535aec715dSWill Deacon * If our current ASID was active during a rollover, we 1545aec715dSWill Deacon * can continue to use it and this was just a false alarm. 1555aec715dSWill Deacon */ 1560ebea808SWill Deacon if (check_update_reserved_asid(asid, newasid)) 1570ebea808SWill Deacon return newasid; 1585aec715dSWill Deacon 1595aec715dSWill Deacon /* 1605aec715dSWill Deacon * We had a valid ASID in a previous life, so try to re-use 1615aec715dSWill Deacon * it if possible. 1625aec715dSWill Deacon */ 1635aec715dSWill Deacon asid &= ~ASID_MASK; 1645aec715dSWill Deacon if (!__test_and_set_bit(asid, asid_map)) 1650ebea808SWill Deacon return newasid; 1665aec715dSWill Deacon } 1675aec715dSWill Deacon 1685aec715dSWill Deacon /* 1695aec715dSWill Deacon * Allocate a free ASID. If we can't find one, take a note of the 1705aec715dSWill Deacon * currently active ASIDs and mark the TLBs as requiring flushes. 1715aec715dSWill Deacon * We always count from ASID #1, as we use ASID #0 when setting a 1725aec715dSWill Deacon * reserved TTBR0 for the init_mm. 1735aec715dSWill Deacon */ 1745aec715dSWill Deacon asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx); 1755aec715dSWill Deacon if (asid != NUM_USER_ASIDS) 1765aec715dSWill Deacon goto set_asid; 1775aec715dSWill Deacon 1785aec715dSWill Deacon /* We're out of ASIDs, so increment the global generation count */ 1795aec715dSWill Deacon generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION, 1805aec715dSWill Deacon &asid_generation); 1815aec715dSWill Deacon flush_context(cpu); 1825aec715dSWill Deacon 1835aec715dSWill Deacon /* We have at least 1 ASID per CPU, so this will always succeed */ 1845aec715dSWill Deacon asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1); 1855aec715dSWill Deacon 1865aec715dSWill Deacon set_asid: 1875aec715dSWill Deacon __set_bit(asid, asid_map); 1885aec715dSWill Deacon cur_idx = asid; 1890ebea808SWill Deacon return asid | generation; 1905aec715dSWill Deacon } 1915aec715dSWill Deacon 1925aec715dSWill Deacon void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) 193b3901d54SCatalin Marinas { 194b3901d54SCatalin Marinas unsigned long flags; 1955aec715dSWill Deacon u64 asid; 1965aec715dSWill Deacon 1975aec715dSWill Deacon asid = atomic64_read(&mm->context.id); 198b3901d54SCatalin Marinas 199b3901d54SCatalin Marinas /* 2005aec715dSWill Deacon * The memory ordering here is subtle. We rely on the control 2015aec715dSWill Deacon * dependency between the generation read and the update of 2025aec715dSWill Deacon * active_asids to ensure that we are synchronised with a 2035aec715dSWill Deacon * parallel rollover (i.e. this pairs with the smp_wmb() in 2045aec715dSWill Deacon * flush_context). 205b3901d54SCatalin Marinas */ 2065aec715dSWill Deacon if (!((asid ^ atomic64_read(&asid_generation)) >> asid_bits) 2075aec715dSWill Deacon && atomic64_xchg_relaxed(&per_cpu(active_asids, cpu), asid)) 2085aec715dSWill Deacon goto switch_mm_fastpath; 209b3901d54SCatalin Marinas 2105aec715dSWill Deacon raw_spin_lock_irqsave(&cpu_asid_lock, flags); 2115aec715dSWill Deacon /* Check that our ASID belongs to the current generation. */ 2125aec715dSWill Deacon asid = atomic64_read(&mm->context.id); 2135aec715dSWill Deacon if ((asid ^ atomic64_read(&asid_generation)) >> asid_bits) { 2145aec715dSWill Deacon asid = new_context(mm, cpu); 2155aec715dSWill Deacon atomic64_set(&mm->context.id, asid); 216b3901d54SCatalin Marinas } 217b3901d54SCatalin Marinas 2185aec715dSWill Deacon if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) 2195aec715dSWill Deacon local_flush_tlb_all(); 220b3901d54SCatalin Marinas 2215aec715dSWill Deacon atomic64_set(&per_cpu(active_asids, cpu), asid); 2225aec715dSWill Deacon raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); 223565630d5SCatalin Marinas 2245aec715dSWill Deacon switch_mm_fastpath: 225b3901d54SCatalin Marinas cpu_switch_mm(mm->pgd, mm); 226b3901d54SCatalin Marinas } 227b3901d54SCatalin Marinas 2285aec715dSWill Deacon static int asids_init(void) 229b3901d54SCatalin Marinas { 230038dc9c6SSuzuki K Poulose asid_bits = get_cpu_asid_bits(); 2315aec715dSWill Deacon /* If we end up with more CPUs than ASIDs, expect things to crash */ 2325aec715dSWill Deacon WARN_ON(NUM_USER_ASIDS < num_possible_cpus()); 2335aec715dSWill Deacon atomic64_set(&asid_generation, ASID_FIRST_VERSION); 2345aec715dSWill Deacon asid_map = kzalloc(BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(*asid_map), 2355aec715dSWill Deacon GFP_KERNEL); 2365aec715dSWill Deacon if (!asid_map) 2375aec715dSWill Deacon panic("Failed to allocate bitmap for %lu ASIDs\n", 2385aec715dSWill Deacon NUM_USER_ASIDS); 2395aec715dSWill Deacon 2405aec715dSWill Deacon pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS); 2415aec715dSWill Deacon return 0; 242b3901d54SCatalin Marinas } 2435aec715dSWill Deacon early_initcall(asids_init); 244