1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * VGICv3 MMIO handling functions 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/irqchip/arm-gic-v3.h> 8 #include <linux/kvm.h> 9 #include <linux/kvm_host.h> 10 #include <linux/interrupt.h> 11 #include <kvm/iodev.h> 12 #include <kvm/arm_vgic.h> 13 14 #include <asm/kvm_emulate.h> 15 #include <asm/kvm_arm.h> 16 #include <asm/kvm_mmu.h> 17 18 #include "vgic.h" 19 #include "vgic-mmio.h" 20 21 /* extract @num bytes at @offset bytes offset in data */ 22 unsigned long extract_bytes(u64 data, unsigned int offset, 23 unsigned int num) 24 { 25 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0); 26 } 27 28 /* allows updates of any half of a 64-bit register (or the whole thing) */ 29 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, 30 unsigned long val) 31 { 32 int lower = (offset & 4) * 8; 33 int upper = lower + 8 * len - 1; 34 35 reg &= ~GENMASK_ULL(upper, lower); 36 val &= GENMASK_ULL(len * 8 - 1, 0); 37 38 return reg | ((u64)val << lower); 39 } 40 41 bool vgic_has_its(struct kvm *kvm) 42 { 43 struct vgic_dist *dist = &kvm->arch.vgic; 44 45 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3) 46 return false; 47 48 return dist->has_its; 49 } 50 51 bool vgic_supports_direct_msis(struct kvm *kvm) 52 { 53 return (kvm_vgic_global_state.has_gicv4_1 || 54 (kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm))); 55 } 56 57 /* 58 * The Revision field in the IIDR have the following meanings: 59 * 60 * Revision 2: Interrupt groups are guest-configurable and signaled using 61 * their configured groups. 62 */ 63 64 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, 65 gpa_t addr, unsigned int len) 66 { 67 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; 68 u32 value = 0; 69 70 switch (addr & 0x0c) { 71 case GICD_CTLR: 72 if (vgic->enabled) 73 value |= GICD_CTLR_ENABLE_SS_G1; 74 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS; 75 if (vgic->nassgireq) 76 value |= GICD_CTLR_nASSGIreq; 77 break; 78 case GICD_TYPER: 79 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS; 80 value = (value >> 5) - 1; 81 if (vgic_has_its(vcpu->kvm)) { 82 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19; 83 value |= GICD_TYPER_LPIS; 84 } else { 85 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19; 86 } 87 break; 88 case GICD_TYPER2: 89 if (kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi()) 90 value = GICD_TYPER2_nASSGIcap; 91 break; 92 case GICD_IIDR: 93 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) | 94 (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) | 95 (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT); 96 break; 97 default: 98 return 0; 99 } 100 101 return value; 102 } 103 104 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu, 105 gpa_t addr, unsigned int len, 106 unsigned long val) 107 { 108 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 109 110 switch (addr & 0x0c) { 111 case GICD_CTLR: { 112 bool was_enabled, is_hwsgi; 113 114 mutex_lock(&vcpu->kvm->lock); 115 116 was_enabled = dist->enabled; 117 is_hwsgi = dist->nassgireq; 118 119 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; 120 121 /* Not a GICv4.1? No HW SGIs */ 122 if (!kvm_vgic_global_state.has_gicv4_1 || !gic_cpuif_has_vsgi()) 123 val &= ~GICD_CTLR_nASSGIreq; 124 125 /* Dist stays enabled? nASSGIreq is RO */ 126 if (was_enabled && dist->enabled) { 127 val &= ~GICD_CTLR_nASSGIreq; 128 val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi); 129 } 130 131 /* Switching HW SGIs? */ 132 dist->nassgireq = val & GICD_CTLR_nASSGIreq; 133 if (is_hwsgi != dist->nassgireq) 134 vgic_v4_configure_vsgis(vcpu->kvm); 135 136 if (kvm_vgic_global_state.has_gicv4_1 && 137 was_enabled != dist->enabled) 138 kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4); 139 else if (!was_enabled && dist->enabled) 140 vgic_kick_vcpus(vcpu->kvm); 141 142 mutex_unlock(&vcpu->kvm->lock); 143 break; 144 } 145 case GICD_TYPER: 146 case GICD_TYPER2: 147 case GICD_IIDR: 148 /* This is at best for documentation purposes... */ 149 return; 150 } 151 } 152 153 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu, 154 gpa_t addr, unsigned int len, 155 unsigned long val) 156 { 157 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 158 u32 reg; 159 160 switch (addr & 0x0c) { 161 case GICD_TYPER2: 162 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len)) 163 return -EINVAL; 164 return 0; 165 case GICD_IIDR: 166 reg = vgic_mmio_read_v3_misc(vcpu, addr, len); 167 if ((reg ^ val) & ~GICD_IIDR_REVISION_MASK) 168 return -EINVAL; 169 170 reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg); 171 switch (reg) { 172 case KVM_VGIC_IMP_REV_2: 173 case KVM_VGIC_IMP_REV_3: 174 dist->implementation_rev = reg; 175 return 0; 176 default: 177 return -EINVAL; 178 } 179 case GICD_CTLR: 180 /* Not a GICv4.1? No HW SGIs */ 181 if (!kvm_vgic_global_state.has_gicv4_1) 182 val &= ~GICD_CTLR_nASSGIreq; 183 184 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; 185 dist->nassgireq = val & GICD_CTLR_nASSGIreq; 186 return 0; 187 } 188 189 vgic_mmio_write_v3_misc(vcpu, addr, len, val); 190 return 0; 191 } 192 193 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu, 194 gpa_t addr, unsigned int len) 195 { 196 int intid = VGIC_ADDR_TO_INTID(addr, 64); 197 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid); 198 unsigned long ret = 0; 199 200 if (!irq) 201 return 0; 202 203 /* The upper word is RAZ for us. */ 204 if (!(addr & 4)) 205 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len); 206 207 vgic_put_irq(vcpu->kvm, irq); 208 return ret; 209 } 210 211 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu, 212 gpa_t addr, unsigned int len, 213 unsigned long val) 214 { 215 int intid = VGIC_ADDR_TO_INTID(addr, 64); 216 struct vgic_irq *irq; 217 unsigned long flags; 218 219 /* The upper word is WI for us since we don't implement Aff3. */ 220 if (addr & 4) 221 return; 222 223 irq = vgic_get_irq(vcpu->kvm, NULL, intid); 224 225 if (!irq) 226 return; 227 228 raw_spin_lock_irqsave(&irq->irq_lock, flags); 229 230 /* We only care about and preserve Aff0, Aff1 and Aff2. */ 231 irq->mpidr = val & GENMASK(23, 0); 232 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr); 233 234 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 235 vgic_put_irq(vcpu->kvm, irq); 236 } 237 238 bool vgic_lpis_enabled(struct kvm_vcpu *vcpu) 239 { 240 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 241 242 return atomic_read(&vgic_cpu->ctlr) == GICR_CTLR_ENABLE_LPIS; 243 } 244 245 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu, 246 gpa_t addr, unsigned int len) 247 { 248 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 249 unsigned long val; 250 251 val = atomic_read(&vgic_cpu->ctlr); 252 if (vgic_get_implementation_rev(vcpu) >= KVM_VGIC_IMP_REV_3) 253 val |= GICR_CTLR_IR | GICR_CTLR_CES; 254 255 return val; 256 } 257 258 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu, 259 gpa_t addr, unsigned int len, 260 unsigned long val) 261 { 262 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 263 u32 ctlr; 264 265 if (!vgic_has_its(vcpu->kvm)) 266 return; 267 268 if (!(val & GICR_CTLR_ENABLE_LPIS)) { 269 /* 270 * Don't disable if RWP is set, as there already an 271 * ongoing disable. Funky guest... 272 */ 273 ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr, 274 GICR_CTLR_ENABLE_LPIS, 275 GICR_CTLR_RWP); 276 if (ctlr != GICR_CTLR_ENABLE_LPIS) 277 return; 278 279 vgic_flush_pending_lpis(vcpu); 280 vgic_its_invalidate_cache(vcpu->kvm); 281 atomic_set_release(&vgic_cpu->ctlr, 0); 282 } else { 283 ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr, 0, 284 GICR_CTLR_ENABLE_LPIS); 285 if (ctlr != 0) 286 return; 287 288 vgic_enable_lpis(vcpu); 289 } 290 } 291 292 static bool vgic_mmio_vcpu_rdist_is_last(struct kvm_vcpu *vcpu) 293 { 294 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; 295 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 296 struct vgic_redist_region *iter, *rdreg = vgic_cpu->rdreg; 297 298 if (!rdreg) 299 return false; 300 301 if (vgic_cpu->rdreg_index < rdreg->free_index - 1) { 302 return false; 303 } else if (rdreg->count && vgic_cpu->rdreg_index == (rdreg->count - 1)) { 304 struct list_head *rd_regions = &vgic->rd_regions; 305 gpa_t end = rdreg->base + rdreg->count * KVM_VGIC_V3_REDIST_SIZE; 306 307 /* 308 * the rdist is the last one of the redist region, 309 * check whether there is no other contiguous rdist region 310 */ 311 list_for_each_entry(iter, rd_regions, list) { 312 if (iter->base == end && iter->free_index > 0) 313 return false; 314 } 315 } 316 return true; 317 } 318 319 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu, 320 gpa_t addr, unsigned int len) 321 { 322 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu); 323 int target_vcpu_id = vcpu->vcpu_id; 324 u64 value; 325 326 value = (u64)(mpidr & GENMASK(23, 0)) << 32; 327 value |= ((target_vcpu_id & 0xffff) << 8); 328 329 if (vgic_has_its(vcpu->kvm)) 330 value |= GICR_TYPER_PLPIS; 331 332 if (vgic_mmio_vcpu_rdist_is_last(vcpu)) 333 value |= GICR_TYPER_LAST; 334 335 return extract_bytes(value, addr & 7, len); 336 } 337 338 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu, 339 gpa_t addr, unsigned int len) 340 { 341 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); 342 } 343 344 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu, 345 gpa_t addr, unsigned int len) 346 { 347 switch (addr & 0xffff) { 348 case GICD_PIDR2: 349 /* report a GICv3 compliant implementation */ 350 return 0x3b; 351 } 352 353 return 0; 354 } 355 356 static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu, 357 gpa_t addr, unsigned int len) 358 { 359 u32 intid = VGIC_ADDR_TO_INTID(addr, 1); 360 u32 value = 0; 361 int i; 362 363 /* 364 * pending state of interrupt is latched in pending_latch variable. 365 * Userspace will save and restore pending state and line_level 366 * separately. 367 * Refer to Documentation/virt/kvm/devices/arm-vgic-v3.rst 368 * for handling of ISPENDR and ICPENDR. 369 */ 370 for (i = 0; i < len * 8; i++) { 371 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); 372 bool state = irq->pending_latch; 373 374 if (irq->hw && vgic_irq_is_sgi(irq->intid)) { 375 int err; 376 377 err = irq_get_irqchip_state(irq->host_irq, 378 IRQCHIP_STATE_PENDING, 379 &state); 380 WARN_ON(err); 381 } 382 383 if (state) 384 value |= (1U << i); 385 386 vgic_put_irq(vcpu->kvm, irq); 387 } 388 389 return value; 390 } 391 392 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, 393 gpa_t addr, unsigned int len, 394 unsigned long val) 395 { 396 u32 intid = VGIC_ADDR_TO_INTID(addr, 1); 397 int i; 398 unsigned long flags; 399 400 for (i = 0; i < len * 8; i++) { 401 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); 402 403 raw_spin_lock_irqsave(&irq->irq_lock, flags); 404 if (test_bit(i, &val)) { 405 /* 406 * pending_latch is set irrespective of irq type 407 * (level or edge) to avoid dependency that VM should 408 * restore irq config before pending info. 409 */ 410 irq->pending_latch = true; 411 vgic_queue_irq_unlock(vcpu->kvm, irq, flags); 412 } else { 413 irq->pending_latch = false; 414 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 415 } 416 417 vgic_put_irq(vcpu->kvm, irq); 418 } 419 420 return 0; 421 } 422 423 /* We want to avoid outer shareable. */ 424 u64 vgic_sanitise_shareability(u64 field) 425 { 426 switch (field) { 427 case GIC_BASER_OuterShareable: 428 return GIC_BASER_InnerShareable; 429 default: 430 return field; 431 } 432 } 433 434 /* Avoid any inner non-cacheable mapping. */ 435 u64 vgic_sanitise_inner_cacheability(u64 field) 436 { 437 switch (field) { 438 case GIC_BASER_CACHE_nCnB: 439 case GIC_BASER_CACHE_nC: 440 return GIC_BASER_CACHE_RaWb; 441 default: 442 return field; 443 } 444 } 445 446 /* Non-cacheable or same-as-inner are OK. */ 447 u64 vgic_sanitise_outer_cacheability(u64 field) 448 { 449 switch (field) { 450 case GIC_BASER_CACHE_SameAsInner: 451 case GIC_BASER_CACHE_nC: 452 return field; 453 default: 454 return GIC_BASER_CACHE_SameAsInner; 455 } 456 } 457 458 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, 459 u64 (*sanitise_fn)(u64)) 460 { 461 u64 field = (reg & field_mask) >> field_shift; 462 463 field = sanitise_fn(field) << field_shift; 464 return (reg & ~field_mask) | field; 465 } 466 467 #define PROPBASER_RES0_MASK \ 468 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) 469 #define PENDBASER_RES0_MASK \ 470 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ 471 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) 472 473 static u64 vgic_sanitise_pendbaser(u64 reg) 474 { 475 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK, 476 GICR_PENDBASER_SHAREABILITY_SHIFT, 477 vgic_sanitise_shareability); 478 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK, 479 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT, 480 vgic_sanitise_inner_cacheability); 481 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK, 482 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT, 483 vgic_sanitise_outer_cacheability); 484 485 reg &= ~PENDBASER_RES0_MASK; 486 487 return reg; 488 } 489 490 static u64 vgic_sanitise_propbaser(u64 reg) 491 { 492 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK, 493 GICR_PROPBASER_SHAREABILITY_SHIFT, 494 vgic_sanitise_shareability); 495 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK, 496 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT, 497 vgic_sanitise_inner_cacheability); 498 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK, 499 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT, 500 vgic_sanitise_outer_cacheability); 501 502 reg &= ~PROPBASER_RES0_MASK; 503 return reg; 504 } 505 506 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu, 507 gpa_t addr, unsigned int len) 508 { 509 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 510 511 return extract_bytes(dist->propbaser, addr & 7, len); 512 } 513 514 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu, 515 gpa_t addr, unsigned int len, 516 unsigned long val) 517 { 518 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 519 u64 old_propbaser, propbaser; 520 521 /* Storing a value with LPIs already enabled is undefined */ 522 if (vgic_lpis_enabled(vcpu)) 523 return; 524 525 do { 526 old_propbaser = READ_ONCE(dist->propbaser); 527 propbaser = old_propbaser; 528 propbaser = update_64bit_reg(propbaser, addr & 4, len, val); 529 propbaser = vgic_sanitise_propbaser(propbaser); 530 } while (cmpxchg64(&dist->propbaser, old_propbaser, 531 propbaser) != old_propbaser); 532 } 533 534 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu, 535 gpa_t addr, unsigned int len) 536 { 537 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 538 u64 value = vgic_cpu->pendbaser; 539 540 value &= ~GICR_PENDBASER_PTZ; 541 542 return extract_bytes(value, addr & 7, len); 543 } 544 545 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, 546 gpa_t addr, unsigned int len, 547 unsigned long val) 548 { 549 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 550 u64 old_pendbaser, pendbaser; 551 552 /* Storing a value with LPIs already enabled is undefined */ 553 if (vgic_lpis_enabled(vcpu)) 554 return; 555 556 do { 557 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser); 558 pendbaser = old_pendbaser; 559 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val); 560 pendbaser = vgic_sanitise_pendbaser(pendbaser); 561 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser, 562 pendbaser) != old_pendbaser); 563 } 564 565 static unsigned long vgic_mmio_read_sync(struct kvm_vcpu *vcpu, 566 gpa_t addr, unsigned int len) 567 { 568 return !!atomic_read(&vcpu->arch.vgic_cpu.syncr_busy); 569 } 570 571 static void vgic_set_rdist_busy(struct kvm_vcpu *vcpu, bool busy) 572 { 573 if (busy) { 574 atomic_inc(&vcpu->arch.vgic_cpu.syncr_busy); 575 smp_mb__after_atomic(); 576 } else { 577 smp_mb__before_atomic(); 578 atomic_dec(&vcpu->arch.vgic_cpu.syncr_busy); 579 } 580 } 581 582 static void vgic_mmio_write_invlpi(struct kvm_vcpu *vcpu, 583 gpa_t addr, unsigned int len, 584 unsigned long val) 585 { 586 struct vgic_irq *irq; 587 588 /* 589 * If the guest wrote only to the upper 32bit part of the 590 * register, drop the write on the floor, as it is only for 591 * vPEs (which we don't support for obvious reasons). 592 * 593 * Also discard the access if LPIs are not enabled. 594 */ 595 if ((addr & 4) || !vgic_lpis_enabled(vcpu)) 596 return; 597 598 vgic_set_rdist_busy(vcpu, true); 599 600 irq = vgic_get_irq(vcpu->kvm, NULL, lower_32_bits(val)); 601 if (irq) { 602 vgic_its_inv_lpi(vcpu->kvm, irq); 603 vgic_put_irq(vcpu->kvm, irq); 604 } 605 606 vgic_set_rdist_busy(vcpu, false); 607 } 608 609 static void vgic_mmio_write_invall(struct kvm_vcpu *vcpu, 610 gpa_t addr, unsigned int len, 611 unsigned long val) 612 { 613 /* See vgic_mmio_write_invlpi() for the early return rationale */ 614 if ((addr & 4) || !vgic_lpis_enabled(vcpu)) 615 return; 616 617 vgic_set_rdist_busy(vcpu, true); 618 vgic_its_invall(vcpu); 619 vgic_set_rdist_busy(vcpu, false); 620 } 621 622 /* 623 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the 624 * redistributors, while SPIs are covered by registers in the distributor 625 * block. Trying to set private IRQs in this block gets ignored. 626 * We take some special care here to fix the calculation of the register 627 * offset. 628 */ 629 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \ 630 { \ 631 .reg_offset = off, \ 632 .bits_per_irq = bpi, \ 633 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ 634 .access_flags = acc, \ 635 .read = vgic_mmio_read_raz, \ 636 .write = vgic_mmio_write_wi, \ 637 }, { \ 638 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ 639 .bits_per_irq = bpi, \ 640 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \ 641 .access_flags = acc, \ 642 .read = rd, \ 643 .write = wr, \ 644 .uaccess_read = ur, \ 645 .uaccess_write = uw, \ 646 } 647 648 static const struct vgic_register_region vgic_v3_dist_registers[] = { 649 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR, 650 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 651 NULL, vgic_mmio_uaccess_write_v3_misc, 652 16, VGIC_ACCESS_32bit), 653 REGISTER_DESC_WITH_LENGTH(GICD_STATUSR, 654 vgic_mmio_read_rao, vgic_mmio_write_wi, 4, 655 VGIC_ACCESS_32bit), 656 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR, 657 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1, 658 VGIC_ACCESS_32bit), 659 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER, 660 vgic_mmio_read_enable, vgic_mmio_write_senable, 661 NULL, vgic_uaccess_write_senable, 1, 662 VGIC_ACCESS_32bit), 663 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER, 664 vgic_mmio_read_enable, vgic_mmio_write_cenable, 665 NULL, vgic_uaccess_write_cenable, 1, 666 VGIC_ACCESS_32bit), 667 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR, 668 vgic_mmio_read_pending, vgic_mmio_write_spending, 669 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1, 670 VGIC_ACCESS_32bit), 671 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR, 672 vgic_mmio_read_pending, vgic_mmio_write_cpending, 673 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1, 674 VGIC_ACCESS_32bit), 675 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER, 676 vgic_mmio_read_active, vgic_mmio_write_sactive, 677 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1, 678 VGIC_ACCESS_32bit), 679 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER, 680 vgic_mmio_read_active, vgic_mmio_write_cactive, 681 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 682 1, VGIC_ACCESS_32bit), 683 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR, 684 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL, 685 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 686 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR, 687 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, 688 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 689 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR, 690 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2, 691 VGIC_ACCESS_32bit), 692 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR, 693 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, 694 VGIC_ACCESS_32bit), 695 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER, 696 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64, 697 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 698 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS, 699 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, 700 VGIC_ACCESS_32bit), 701 }; 702 703 static const struct vgic_register_region vgic_v3_rd_registers[] = { 704 /* RD_base registers */ 705 REGISTER_DESC_WITH_LENGTH(GICR_CTLR, 706 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4, 707 VGIC_ACCESS_32bit), 708 REGISTER_DESC_WITH_LENGTH(GICR_STATUSR, 709 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 710 VGIC_ACCESS_32bit), 711 REGISTER_DESC_WITH_LENGTH(GICR_IIDR, 712 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4, 713 VGIC_ACCESS_32bit), 714 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_TYPER, 715 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 716 NULL, vgic_mmio_uaccess_write_wi, 8, 717 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 718 REGISTER_DESC_WITH_LENGTH(GICR_WAKER, 719 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 720 VGIC_ACCESS_32bit), 721 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER, 722 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8, 723 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 724 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER, 725 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8, 726 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 727 REGISTER_DESC_WITH_LENGTH(GICR_INVLPIR, 728 vgic_mmio_read_raz, vgic_mmio_write_invlpi, 8, 729 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 730 REGISTER_DESC_WITH_LENGTH(GICR_INVALLR, 731 vgic_mmio_read_raz, vgic_mmio_write_invall, 8, 732 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 733 REGISTER_DESC_WITH_LENGTH(GICR_SYNCR, 734 vgic_mmio_read_sync, vgic_mmio_write_wi, 4, 735 VGIC_ACCESS_32bit), 736 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS, 737 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, 738 VGIC_ACCESS_32bit), 739 /* SGI_base registers */ 740 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0, 741 vgic_mmio_read_group, vgic_mmio_write_group, 4, 742 VGIC_ACCESS_32bit), 743 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0, 744 vgic_mmio_read_enable, vgic_mmio_write_senable, 745 NULL, vgic_uaccess_write_senable, 4, 746 VGIC_ACCESS_32bit), 747 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0, 748 vgic_mmio_read_enable, vgic_mmio_write_cenable, 749 NULL, vgic_uaccess_write_cenable, 4, 750 VGIC_ACCESS_32bit), 751 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0, 752 vgic_mmio_read_pending, vgic_mmio_write_spending, 753 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4, 754 VGIC_ACCESS_32bit), 755 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0, 756 vgic_mmio_read_pending, vgic_mmio_write_cpending, 757 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4, 758 VGIC_ACCESS_32bit), 759 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0, 760 vgic_mmio_read_active, vgic_mmio_write_sactive, 761 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 4, 762 VGIC_ACCESS_32bit), 763 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0, 764 vgic_mmio_read_active, vgic_mmio_write_cactive, 765 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 4, 766 VGIC_ACCESS_32bit), 767 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0, 768 vgic_mmio_read_priority, vgic_mmio_write_priority, 32, 769 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 770 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0, 771 vgic_mmio_read_config, vgic_mmio_write_config, 8, 772 VGIC_ACCESS_32bit), 773 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0, 774 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 775 VGIC_ACCESS_32bit), 776 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR, 777 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 778 VGIC_ACCESS_32bit), 779 }; 780 781 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev) 782 { 783 dev->regions = vgic_v3_dist_registers; 784 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); 785 786 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops); 787 788 return SZ_64K; 789 } 790 791 /** 792 * vgic_register_redist_iodev - register a single redist iodev 793 * @vcpu: The VCPU to which the redistributor belongs 794 * 795 * Register a KVM iodev for this VCPU's redistributor using the address 796 * provided. 797 * 798 * Return 0 on success, -ERRNO otherwise. 799 */ 800 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu) 801 { 802 struct kvm *kvm = vcpu->kvm; 803 struct vgic_dist *vgic = &kvm->arch.vgic; 804 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 805 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; 806 struct vgic_redist_region *rdreg; 807 gpa_t rd_base; 808 int ret; 809 810 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) 811 return 0; 812 813 /* 814 * We may be creating VCPUs before having set the base address for the 815 * redistributor region, in which case we will come back to this 816 * function for all VCPUs when the base address is set. Just return 817 * without doing any work for now. 818 */ 819 rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions); 820 if (!rdreg) 821 return 0; 822 823 if (!vgic_v3_check_base(kvm)) 824 return -EINVAL; 825 826 vgic_cpu->rdreg = rdreg; 827 vgic_cpu->rdreg_index = rdreg->free_index; 828 829 rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE; 830 831 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops); 832 rd_dev->base_addr = rd_base; 833 rd_dev->iodev_type = IODEV_REDIST; 834 rd_dev->regions = vgic_v3_rd_registers; 835 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); 836 rd_dev->redist_vcpu = vcpu; 837 838 mutex_lock(&kvm->slots_lock); 839 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base, 840 2 * SZ_64K, &rd_dev->dev); 841 mutex_unlock(&kvm->slots_lock); 842 843 if (ret) 844 return ret; 845 846 rdreg->free_index++; 847 return 0; 848 } 849 850 static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu) 851 { 852 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; 853 854 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev); 855 } 856 857 static int vgic_register_all_redist_iodevs(struct kvm *kvm) 858 { 859 struct kvm_vcpu *vcpu; 860 unsigned long c; 861 int ret = 0; 862 863 kvm_for_each_vcpu(c, vcpu, kvm) { 864 ret = vgic_register_redist_iodev(vcpu); 865 if (ret) 866 break; 867 } 868 869 if (ret) { 870 /* The current c failed, so iterate over the previous ones. */ 871 int i; 872 873 mutex_lock(&kvm->slots_lock); 874 for (i = 0; i < c; i++) { 875 vcpu = kvm_get_vcpu(kvm, i); 876 vgic_unregister_redist_iodev(vcpu); 877 } 878 mutex_unlock(&kvm->slots_lock); 879 } 880 881 return ret; 882 } 883 884 /** 885 * vgic_v3_alloc_redist_region - Allocate a new redistributor region 886 * 887 * Performs various checks before inserting the rdist region in the list. 888 * Those tests depend on whether the size of the rdist region is known 889 * (ie. count != 0). The list is sorted by rdist region index. 890 * 891 * @kvm: kvm handle 892 * @index: redist region index 893 * @base: base of the new rdist region 894 * @count: number of redistributors the region is made of (0 in the old style 895 * single region, whose size is induced from the number of vcpus) 896 * 897 * Return 0 on success, < 0 otherwise 898 */ 899 static int vgic_v3_alloc_redist_region(struct kvm *kvm, uint32_t index, 900 gpa_t base, uint32_t count) 901 { 902 struct vgic_dist *d = &kvm->arch.vgic; 903 struct vgic_redist_region *rdreg; 904 struct list_head *rd_regions = &d->rd_regions; 905 int nr_vcpus = atomic_read(&kvm->online_vcpus); 906 size_t size = count ? count * KVM_VGIC_V3_REDIST_SIZE 907 : nr_vcpus * KVM_VGIC_V3_REDIST_SIZE; 908 int ret; 909 910 /* cross the end of memory ? */ 911 if (base + size < base) 912 return -EINVAL; 913 914 if (list_empty(rd_regions)) { 915 if (index != 0) 916 return -EINVAL; 917 } else { 918 rdreg = list_last_entry(rd_regions, 919 struct vgic_redist_region, list); 920 921 /* Don't mix single region and discrete redist regions */ 922 if (!count && rdreg->count) 923 return -EINVAL; 924 925 if (!count) 926 return -EEXIST; 927 928 if (index != rdreg->index + 1) 929 return -EINVAL; 930 } 931 932 /* 933 * For legacy single-region redistributor regions (!count), 934 * check that the redistributor region does not overlap with the 935 * distributor's address space. 936 */ 937 if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && 938 vgic_dist_overlap(kvm, base, size)) 939 return -EINVAL; 940 941 /* collision with any other rdist region? */ 942 if (vgic_v3_rdist_overlap(kvm, base, size)) 943 return -EINVAL; 944 945 rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL_ACCOUNT); 946 if (!rdreg) 947 return -ENOMEM; 948 949 rdreg->base = VGIC_ADDR_UNDEF; 950 951 ret = vgic_check_iorange(kvm, rdreg->base, base, SZ_64K, size); 952 if (ret) 953 goto free; 954 955 rdreg->base = base; 956 rdreg->count = count; 957 rdreg->free_index = 0; 958 rdreg->index = index; 959 960 list_add_tail(&rdreg->list, rd_regions); 961 return 0; 962 free: 963 kfree(rdreg); 964 return ret; 965 } 966 967 void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg) 968 { 969 list_del(&rdreg->list); 970 kfree(rdreg); 971 } 972 973 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count) 974 { 975 int ret; 976 977 ret = vgic_v3_alloc_redist_region(kvm, index, addr, count); 978 if (ret) 979 return ret; 980 981 /* 982 * Register iodevs for each existing VCPU. Adding more VCPUs 983 * afterwards will register the iodevs when needed. 984 */ 985 ret = vgic_register_all_redist_iodevs(kvm); 986 if (ret) { 987 struct vgic_redist_region *rdreg; 988 989 rdreg = vgic_v3_rdist_region_from_index(kvm, index); 990 vgic_v3_free_redist_region(rdreg); 991 return ret; 992 } 993 994 return 0; 995 } 996 997 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr) 998 { 999 const struct vgic_register_region *region; 1000 struct vgic_io_device iodev; 1001 struct vgic_reg_attr reg_attr; 1002 struct kvm_vcpu *vcpu; 1003 gpa_t addr; 1004 int ret; 1005 1006 ret = vgic_v3_parse_attr(dev, attr, ®_attr); 1007 if (ret) 1008 return ret; 1009 1010 vcpu = reg_attr.vcpu; 1011 addr = reg_attr.addr; 1012 1013 switch (attr->group) { 1014 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 1015 iodev.regions = vgic_v3_dist_registers; 1016 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); 1017 iodev.base_addr = 0; 1018 break; 1019 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{ 1020 iodev.regions = vgic_v3_rd_registers; 1021 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); 1022 iodev.base_addr = 0; 1023 break; 1024 } 1025 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: { 1026 u64 reg, id; 1027 1028 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK); 1029 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, ®); 1030 } 1031 default: 1032 return -ENXIO; 1033 } 1034 1035 /* We only support aligned 32-bit accesses. */ 1036 if (addr & 3) 1037 return -ENXIO; 1038 1039 region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32)); 1040 if (!region) 1041 return -ENXIO; 1042 1043 return 0; 1044 } 1045 /* 1046 * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI 1047 * generation register ICC_SGI1R_EL1) with a given VCPU. 1048 * If the VCPU's MPIDR matches, return the level0 affinity, otherwise 1049 * return -1. 1050 */ 1051 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu) 1052 { 1053 unsigned long affinity; 1054 int level0; 1055 1056 /* 1057 * Split the current VCPU's MPIDR into affinity level 0 and the 1058 * rest as this is what we have to compare against. 1059 */ 1060 affinity = kvm_vcpu_get_mpidr_aff(vcpu); 1061 level0 = MPIDR_AFFINITY_LEVEL(affinity, 0); 1062 affinity &= ~MPIDR_LEVEL_MASK; 1063 1064 /* bail out if the upper three levels don't match */ 1065 if (sgi_aff != affinity) 1066 return -1; 1067 1068 /* Is this VCPU's bit set in the mask ? */ 1069 if (!(sgi_cpu_mask & BIT(level0))) 1070 return -1; 1071 1072 return level0; 1073 } 1074 1075 /* 1076 * The ICC_SGI* registers encode the affinity differently from the MPIDR, 1077 * so provide a wrapper to use the existing defines to isolate a certain 1078 * affinity level. 1079 */ 1080 #define SGI_AFFINITY_LEVEL(reg, level) \ 1081 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \ 1082 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level)) 1083 1084 /** 1085 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs 1086 * @vcpu: The VCPU requesting a SGI 1087 * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU 1088 * @allow_group1: Does the sysreg access allow generation of G1 SGIs 1089 * 1090 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register. 1091 * This will trap in sys_regs.c and call this function. 1092 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the 1093 * target processors as well as a bitmask of 16 Aff0 CPUs. 1094 * If the interrupt routing mode bit is not set, we iterate over all VCPUs to 1095 * check for matching ones. If this bit is set, we signal all, but not the 1096 * calling VCPU. 1097 */ 1098 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) 1099 { 1100 struct kvm *kvm = vcpu->kvm; 1101 struct kvm_vcpu *c_vcpu; 1102 u16 target_cpus; 1103 u64 mpidr; 1104 int sgi; 1105 int vcpu_id = vcpu->vcpu_id; 1106 bool broadcast; 1107 unsigned long c, flags; 1108 1109 sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT; 1110 broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT); 1111 target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT; 1112 mpidr = SGI_AFFINITY_LEVEL(reg, 3); 1113 mpidr |= SGI_AFFINITY_LEVEL(reg, 2); 1114 mpidr |= SGI_AFFINITY_LEVEL(reg, 1); 1115 1116 /* 1117 * We iterate over all VCPUs to find the MPIDRs matching the request. 1118 * If we have handled one CPU, we clear its bit to detect early 1119 * if we are already finished. This avoids iterating through all 1120 * VCPUs when most of the times we just signal a single VCPU. 1121 */ 1122 kvm_for_each_vcpu(c, c_vcpu, kvm) { 1123 struct vgic_irq *irq; 1124 1125 /* Exit early if we have dealt with all requested CPUs */ 1126 if (!broadcast && target_cpus == 0) 1127 break; 1128 1129 /* Don't signal the calling VCPU */ 1130 if (broadcast && c == vcpu_id) 1131 continue; 1132 1133 if (!broadcast) { 1134 int level0; 1135 1136 level0 = match_mpidr(mpidr, target_cpus, c_vcpu); 1137 if (level0 == -1) 1138 continue; 1139 1140 /* remove this matching VCPU from the mask */ 1141 target_cpus &= ~BIT(level0); 1142 } 1143 1144 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi); 1145 1146 raw_spin_lock_irqsave(&irq->irq_lock, flags); 1147 1148 /* 1149 * An access targeting Group0 SGIs can only generate 1150 * those, while an access targeting Group1 SGIs can 1151 * generate interrupts of either group. 1152 */ 1153 if (!irq->group || allow_group1) { 1154 if (!irq->hw) { 1155 irq->pending_latch = true; 1156 vgic_queue_irq_unlock(vcpu->kvm, irq, flags); 1157 } else { 1158 /* HW SGI? Ask the GIC to inject it */ 1159 int err; 1160 err = irq_set_irqchip_state(irq->host_irq, 1161 IRQCHIP_STATE_PENDING, 1162 true); 1163 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq); 1164 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 1165 } 1166 } else { 1167 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 1168 } 1169 1170 vgic_put_irq(vcpu->kvm, irq); 1171 } 1172 } 1173 1174 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1175 int offset, u32 *val) 1176 { 1177 struct vgic_io_device dev = { 1178 .regions = vgic_v3_dist_registers, 1179 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers), 1180 }; 1181 1182 return vgic_uaccess(vcpu, &dev, is_write, offset, val); 1183 } 1184 1185 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1186 int offset, u32 *val) 1187 { 1188 struct vgic_io_device rd_dev = { 1189 .regions = vgic_v3_rd_registers, 1190 .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers), 1191 }; 1192 1193 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val); 1194 } 1195 1196 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1197 u32 intid, u64 *val) 1198 { 1199 if (intid % 32) 1200 return -EINVAL; 1201 1202 if (is_write) 1203 vgic_write_irq_line_level_info(vcpu, intid, *val); 1204 else 1205 *val = vgic_read_irq_line_level_info(vcpu, intid); 1206 1207 return 0; 1208 } 1209