1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/kvm_host.h> 16 #include <linux/mm.h> 17 #include <linux/printk.h> 18 #include <linux/uaccess.h> 19 20 #include <asm/cacheflush.h> 21 #include <asm/cputype.h> 22 #include <asm/debug-monitors.h> 23 #include <asm/esr.h> 24 #include <asm/kvm_arm.h> 25 #include <asm/kvm_emulate.h> 26 #include <asm/kvm_hyp.h> 27 #include <asm/kvm_mmu.h> 28 #include <asm/kvm_nested.h> 29 #include <asm/perf_event.h> 30 #include <asm/sysreg.h> 31 32 #include <trace/events/kvm.h> 33 34 #include "sys_regs.h" 35 36 #include "trace.h" 37 38 /* 39 * For AArch32, we only take care of what is being trapped. Anything 40 * that has to do with init and userspace access has to go via the 41 * 64bit interface. 42 */ 43 44 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 45 46 static bool read_from_write_only(struct kvm_vcpu *vcpu, 47 struct sys_reg_params *params, 48 const struct sys_reg_desc *r) 49 { 50 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 51 print_sys_reg_instr(params); 52 kvm_inject_undefined(vcpu); 53 return false; 54 } 55 56 static bool write_to_read_only(struct kvm_vcpu *vcpu, 57 struct sys_reg_params *params, 58 const struct sys_reg_desc *r) 59 { 60 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 61 print_sys_reg_instr(params); 62 kvm_inject_undefined(vcpu); 63 return false; 64 } 65 66 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 67 { 68 u64 val = 0x8badf00d8badf00d; 69 70 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 71 __vcpu_read_sys_reg_from_cpu(reg, &val)) 72 return val; 73 74 return __vcpu_sys_reg(vcpu, reg); 75 } 76 77 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 78 { 79 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 80 __vcpu_write_sys_reg_to_cpu(val, reg)) 81 return; 82 83 __vcpu_sys_reg(vcpu, reg) = val; 84 } 85 86 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 87 #define CSSELR_MAX 14 88 89 /* 90 * Returns the minimum line size for the selected cache, expressed as 91 * Log2(bytes). 92 */ 93 static u8 get_min_cache_line_size(bool icache) 94 { 95 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 96 u8 field; 97 98 if (icache) 99 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 100 else 101 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 102 103 /* 104 * Cache line size is represented as Log2(words) in CTR_EL0. 105 * Log2(bytes) can be derived with the following: 106 * 107 * Log2(words) + 2 = Log2(bytes / 4) + 2 108 * = Log2(bytes) - 2 + 2 109 * = Log2(bytes) 110 */ 111 return field + 2; 112 } 113 114 /* Which cache CCSIDR represents depends on CSSELR value. */ 115 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 116 { 117 u8 line_size; 118 119 if (vcpu->arch.ccsidr) 120 return vcpu->arch.ccsidr[csselr]; 121 122 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 123 124 /* 125 * Fabricate a CCSIDR value as the overriding value does not exist. 126 * The real CCSIDR value will not be used as it can vary by the 127 * physical CPU which the vcpu currently resides in. 128 * 129 * The line size is determined with get_min_cache_line_size(), which 130 * should be valid for all CPUs even if they have different cache 131 * configuration. 132 * 133 * The associativity bits are cleared, meaning the geometry of all data 134 * and unified caches (which are guaranteed to be PIPT and thus 135 * non-aliasing) are 1 set and 1 way. 136 * Guests should not be doing cache operations by set/way at all, and 137 * for this reason, we trap them and attempt to infer the intent, so 138 * that we can flush the entire guest's address space at the appropriate 139 * time. The exposed geometry minimizes the number of the traps. 140 * [If guests should attempt to infer aliasing properties from the 141 * geometry (which is not permitted by the architecture), they would 142 * only do so for virtually indexed caches.] 143 * 144 * We don't check if the cache level exists as it is allowed to return 145 * an UNKNOWN value if not. 146 */ 147 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 148 } 149 150 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 151 { 152 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 153 u32 *ccsidr = vcpu->arch.ccsidr; 154 u32 i; 155 156 if ((val & CCSIDR_EL1_RES0) || 157 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 158 return -EINVAL; 159 160 if (!ccsidr) { 161 if (val == get_ccsidr(vcpu, csselr)) 162 return 0; 163 164 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 165 if (!ccsidr) 166 return -ENOMEM; 167 168 for (i = 0; i < CSSELR_MAX; i++) 169 ccsidr[i] = get_ccsidr(vcpu, i); 170 171 vcpu->arch.ccsidr = ccsidr; 172 } 173 174 ccsidr[csselr] = val; 175 176 return 0; 177 } 178 179 static bool access_rw(struct kvm_vcpu *vcpu, 180 struct sys_reg_params *p, 181 const struct sys_reg_desc *r) 182 { 183 if (p->is_write) 184 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 185 else 186 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 187 188 return true; 189 } 190 191 /* 192 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 193 */ 194 static bool access_dcsw(struct kvm_vcpu *vcpu, 195 struct sys_reg_params *p, 196 const struct sys_reg_desc *r) 197 { 198 if (!p->is_write) 199 return read_from_write_only(vcpu, p, r); 200 201 /* 202 * Only track S/W ops if we don't have FWB. It still indicates 203 * that the guest is a bit broken (S/W operations should only 204 * be done by firmware, knowing that there is only a single 205 * CPU left in the system, and certainly not from non-secure 206 * software). 207 */ 208 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 209 kvm_set_way_flush(vcpu); 210 211 return true; 212 } 213 214 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 215 { 216 switch (r->aarch32_map) { 217 case AA32_LO: 218 *mask = GENMASK_ULL(31, 0); 219 *shift = 0; 220 break; 221 case AA32_HI: 222 *mask = GENMASK_ULL(63, 32); 223 *shift = 32; 224 break; 225 default: 226 *mask = GENMASK_ULL(63, 0); 227 *shift = 0; 228 break; 229 } 230 } 231 232 /* 233 * Generic accessor for VM registers. Only called as long as HCR_TVM 234 * is set. If the guest enables the MMU, we stop trapping the VM 235 * sys_regs and leave it in complete control of the caches. 236 */ 237 static bool access_vm_reg(struct kvm_vcpu *vcpu, 238 struct sys_reg_params *p, 239 const struct sys_reg_desc *r) 240 { 241 bool was_enabled = vcpu_has_cache_enabled(vcpu); 242 u64 val, mask, shift; 243 244 BUG_ON(!p->is_write); 245 246 get_access_mask(r, &mask, &shift); 247 248 if (~mask) { 249 val = vcpu_read_sys_reg(vcpu, r->reg); 250 val &= ~mask; 251 } else { 252 val = 0; 253 } 254 255 val |= (p->regval & (mask >> shift)) << shift; 256 vcpu_write_sys_reg(vcpu, val, r->reg); 257 258 kvm_toggle_cache(vcpu, was_enabled); 259 return true; 260 } 261 262 static bool access_actlr(struct kvm_vcpu *vcpu, 263 struct sys_reg_params *p, 264 const struct sys_reg_desc *r) 265 { 266 u64 mask, shift; 267 268 if (p->is_write) 269 return ignore_write(vcpu, p); 270 271 get_access_mask(r, &mask, &shift); 272 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 273 274 return true; 275 } 276 277 /* 278 * Trap handler for the GICv3 SGI generation system register. 279 * Forward the request to the VGIC emulation. 280 * The cp15_64 code makes sure this automatically works 281 * for both AArch64 and AArch32 accesses. 282 */ 283 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 284 struct sys_reg_params *p, 285 const struct sys_reg_desc *r) 286 { 287 bool g1; 288 289 if (!p->is_write) 290 return read_from_write_only(vcpu, p, r); 291 292 /* 293 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 294 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 295 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 296 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 297 * group. 298 */ 299 if (p->Op0 == 0) { /* AArch32 */ 300 switch (p->Op1) { 301 default: /* Keep GCC quiet */ 302 case 0: /* ICC_SGI1R */ 303 g1 = true; 304 break; 305 case 1: /* ICC_ASGI1R */ 306 case 2: /* ICC_SGI0R */ 307 g1 = false; 308 break; 309 } 310 } else { /* AArch64 */ 311 switch (p->Op2) { 312 default: /* Keep GCC quiet */ 313 case 5: /* ICC_SGI1R_EL1 */ 314 g1 = true; 315 break; 316 case 6: /* ICC_ASGI1R_EL1 */ 317 case 7: /* ICC_SGI0R_EL1 */ 318 g1 = false; 319 break; 320 } 321 } 322 323 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 324 325 return true; 326 } 327 328 static bool access_gic_sre(struct kvm_vcpu *vcpu, 329 struct sys_reg_params *p, 330 const struct sys_reg_desc *r) 331 { 332 if (p->is_write) 333 return ignore_write(vcpu, p); 334 335 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 336 return true; 337 } 338 339 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 340 struct sys_reg_params *p, 341 const struct sys_reg_desc *r) 342 { 343 if (p->is_write) 344 return ignore_write(vcpu, p); 345 else 346 return read_zero(vcpu, p); 347 } 348 349 static bool trap_undef(struct kvm_vcpu *vcpu, 350 struct sys_reg_params *p, 351 const struct sys_reg_desc *r) 352 { 353 kvm_inject_undefined(vcpu); 354 return false; 355 } 356 357 /* 358 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 359 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 360 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 361 * treat it separately. 362 */ 363 static bool trap_loregion(struct kvm_vcpu *vcpu, 364 struct sys_reg_params *p, 365 const struct sys_reg_desc *r) 366 { 367 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 368 u32 sr = reg_to_encoding(r); 369 370 if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { 371 kvm_inject_undefined(vcpu); 372 return false; 373 } 374 375 if (p->is_write && sr == SYS_LORID_EL1) 376 return write_to_read_only(vcpu, p, r); 377 378 return trap_raz_wi(vcpu, p, r); 379 } 380 381 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 382 struct sys_reg_params *p, 383 const struct sys_reg_desc *r) 384 { 385 u64 oslsr; 386 387 if (!p->is_write) 388 return read_from_write_only(vcpu, p, r); 389 390 /* Forward the OSLK bit to OSLSR */ 391 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK; 392 if (p->regval & SYS_OSLAR_OSLK) 393 oslsr |= SYS_OSLSR_OSLK; 394 395 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 396 return true; 397 } 398 399 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 400 struct sys_reg_params *p, 401 const struct sys_reg_desc *r) 402 { 403 if (p->is_write) 404 return write_to_read_only(vcpu, p, r); 405 406 p->regval = __vcpu_sys_reg(vcpu, r->reg); 407 return true; 408 } 409 410 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 411 u64 val) 412 { 413 /* 414 * The only modifiable bit is the OSLK bit. Refuse the write if 415 * userspace attempts to change any other bit in the register. 416 */ 417 if ((val ^ rd->val) & ~SYS_OSLSR_OSLK) 418 return -EINVAL; 419 420 __vcpu_sys_reg(vcpu, rd->reg) = val; 421 return 0; 422 } 423 424 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 425 struct sys_reg_params *p, 426 const struct sys_reg_desc *r) 427 { 428 if (p->is_write) { 429 return ignore_write(vcpu, p); 430 } else { 431 p->regval = read_sysreg(dbgauthstatus_el1); 432 return true; 433 } 434 } 435 436 /* 437 * We want to avoid world-switching all the DBG registers all the 438 * time: 439 * 440 * - If we've touched any debug register, it is likely that we're 441 * going to touch more of them. It then makes sense to disable the 442 * traps and start doing the save/restore dance 443 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 444 * then mandatory to save/restore the registers, as the guest 445 * depends on them. 446 * 447 * For this, we use a DIRTY bit, indicating the guest has modified the 448 * debug registers, used as follow: 449 * 450 * On guest entry: 451 * - If the dirty bit is set (because we're coming back from trapping), 452 * disable the traps, save host registers, restore guest registers. 453 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 454 * set the dirty bit, disable the traps, save host registers, 455 * restore guest registers. 456 * - Otherwise, enable the traps 457 * 458 * On guest exit: 459 * - If the dirty bit is set, save guest registers, restore host 460 * registers and clear the dirty bit. This ensure that the host can 461 * now use the debug registers. 462 */ 463 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 464 struct sys_reg_params *p, 465 const struct sys_reg_desc *r) 466 { 467 access_rw(vcpu, p, r); 468 if (p->is_write) 469 vcpu_set_flag(vcpu, DEBUG_DIRTY); 470 471 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 472 473 return true; 474 } 475 476 /* 477 * reg_to_dbg/dbg_to_reg 478 * 479 * A 32 bit write to a debug register leave top bits alone 480 * A 32 bit read from a debug register only returns the bottom bits 481 * 482 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 483 * switches between host and guest values in future. 484 */ 485 static void reg_to_dbg(struct kvm_vcpu *vcpu, 486 struct sys_reg_params *p, 487 const struct sys_reg_desc *rd, 488 u64 *dbg_reg) 489 { 490 u64 mask, shift, val; 491 492 get_access_mask(rd, &mask, &shift); 493 494 val = *dbg_reg; 495 val &= ~mask; 496 val |= (p->regval & (mask >> shift)) << shift; 497 *dbg_reg = val; 498 499 vcpu_set_flag(vcpu, DEBUG_DIRTY); 500 } 501 502 static void dbg_to_reg(struct kvm_vcpu *vcpu, 503 struct sys_reg_params *p, 504 const struct sys_reg_desc *rd, 505 u64 *dbg_reg) 506 { 507 u64 mask, shift; 508 509 get_access_mask(rd, &mask, &shift); 510 p->regval = (*dbg_reg & mask) >> shift; 511 } 512 513 static bool trap_bvr(struct kvm_vcpu *vcpu, 514 struct sys_reg_params *p, 515 const struct sys_reg_desc *rd) 516 { 517 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 518 519 if (p->is_write) 520 reg_to_dbg(vcpu, p, rd, dbg_reg); 521 else 522 dbg_to_reg(vcpu, p, rd, dbg_reg); 523 524 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 525 526 return true; 527 } 528 529 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 530 u64 val) 531 { 532 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 533 return 0; 534 } 535 536 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 537 u64 *val) 538 { 539 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 540 return 0; 541 } 542 543 static void reset_bvr(struct kvm_vcpu *vcpu, 544 const struct sys_reg_desc *rd) 545 { 546 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 547 } 548 549 static bool trap_bcr(struct kvm_vcpu *vcpu, 550 struct sys_reg_params *p, 551 const struct sys_reg_desc *rd) 552 { 553 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 554 555 if (p->is_write) 556 reg_to_dbg(vcpu, p, rd, dbg_reg); 557 else 558 dbg_to_reg(vcpu, p, rd, dbg_reg); 559 560 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 561 562 return true; 563 } 564 565 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 566 u64 val) 567 { 568 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 569 return 0; 570 } 571 572 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 573 u64 *val) 574 { 575 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 576 return 0; 577 } 578 579 static void reset_bcr(struct kvm_vcpu *vcpu, 580 const struct sys_reg_desc *rd) 581 { 582 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 583 } 584 585 static bool trap_wvr(struct kvm_vcpu *vcpu, 586 struct sys_reg_params *p, 587 const struct sys_reg_desc *rd) 588 { 589 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 590 591 if (p->is_write) 592 reg_to_dbg(vcpu, p, rd, dbg_reg); 593 else 594 dbg_to_reg(vcpu, p, rd, dbg_reg); 595 596 trace_trap_reg(__func__, rd->CRm, p->is_write, 597 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 598 599 return true; 600 } 601 602 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 603 u64 val) 604 { 605 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 606 return 0; 607 } 608 609 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 610 u64 *val) 611 { 612 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 613 return 0; 614 } 615 616 static void reset_wvr(struct kvm_vcpu *vcpu, 617 const struct sys_reg_desc *rd) 618 { 619 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 620 } 621 622 static bool trap_wcr(struct kvm_vcpu *vcpu, 623 struct sys_reg_params *p, 624 const struct sys_reg_desc *rd) 625 { 626 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 627 628 if (p->is_write) 629 reg_to_dbg(vcpu, p, rd, dbg_reg); 630 else 631 dbg_to_reg(vcpu, p, rd, dbg_reg); 632 633 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 634 635 return true; 636 } 637 638 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 639 u64 val) 640 { 641 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 642 return 0; 643 } 644 645 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 646 u64 *val) 647 { 648 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 649 return 0; 650 } 651 652 static void reset_wcr(struct kvm_vcpu *vcpu, 653 const struct sys_reg_desc *rd) 654 { 655 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 656 } 657 658 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 659 { 660 u64 amair = read_sysreg(amair_el1); 661 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 662 } 663 664 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 665 { 666 u64 actlr = read_sysreg(actlr_el1); 667 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 668 } 669 670 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 671 { 672 u64 mpidr; 673 674 /* 675 * Map the vcpu_id into the first three affinity level fields of 676 * the MPIDR. We limit the number of VCPUs in level 0 due to a 677 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 678 * of the GICv3 to be able to address each CPU directly when 679 * sending IPIs. 680 */ 681 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 682 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 683 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 684 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 685 } 686 687 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 688 const struct sys_reg_desc *r) 689 { 690 if (kvm_vcpu_has_pmu(vcpu)) 691 return 0; 692 693 return REG_HIDDEN; 694 } 695 696 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 697 { 698 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); 699 700 /* No PMU available, any PMU reg may UNDEF... */ 701 if (!kvm_arm_support_pmu_v3()) 702 return; 703 704 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; 705 n &= ARMV8_PMU_PMCR_N_MASK; 706 if (n) 707 mask |= GENMASK(n - 1, 0); 708 709 reset_unknown(vcpu, r); 710 __vcpu_sys_reg(vcpu, r->reg) &= mask; 711 } 712 713 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 714 { 715 reset_unknown(vcpu, r); 716 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 717 } 718 719 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 720 { 721 reset_unknown(vcpu, r); 722 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK; 723 } 724 725 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 726 { 727 reset_unknown(vcpu, r); 728 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; 729 } 730 731 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 732 { 733 u64 pmcr; 734 735 /* No PMU available, PMCR_EL0 may UNDEF... */ 736 if (!kvm_arm_support_pmu_v3()) 737 return; 738 739 /* Only preserve PMCR_EL0.N, and reset the rest to 0 */ 740 pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT); 741 if (!kvm_supports_32bit_el0()) 742 pmcr |= ARMV8_PMU_PMCR_LC; 743 744 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 745 } 746 747 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 748 { 749 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 750 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 751 752 if (!enabled) 753 kvm_inject_undefined(vcpu); 754 755 return !enabled; 756 } 757 758 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 759 { 760 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 761 } 762 763 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 764 { 765 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 766 } 767 768 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 769 { 770 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 771 } 772 773 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 774 { 775 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 776 } 777 778 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 779 const struct sys_reg_desc *r) 780 { 781 u64 val; 782 783 if (pmu_access_el0_disabled(vcpu)) 784 return false; 785 786 if (p->is_write) { 787 /* 788 * Only update writeable bits of PMCR (continuing into 789 * kvm_pmu_handle_pmcr() as well) 790 */ 791 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 792 val &= ~ARMV8_PMU_PMCR_MASK; 793 val |= p->regval & ARMV8_PMU_PMCR_MASK; 794 if (!kvm_supports_32bit_el0()) 795 val |= ARMV8_PMU_PMCR_LC; 796 kvm_pmu_handle_pmcr(vcpu, val); 797 kvm_vcpu_pmu_restore_guest(vcpu); 798 } else { 799 /* PMCR.P & PMCR.C are RAZ */ 800 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 801 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 802 p->regval = val; 803 } 804 805 return true; 806 } 807 808 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 809 const struct sys_reg_desc *r) 810 { 811 if (pmu_access_event_counter_el0_disabled(vcpu)) 812 return false; 813 814 if (p->is_write) 815 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 816 else 817 /* return PMSELR.SEL field */ 818 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 819 & ARMV8_PMU_COUNTER_MASK; 820 821 return true; 822 } 823 824 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 825 const struct sys_reg_desc *r) 826 { 827 u64 pmceid, mask, shift; 828 829 BUG_ON(p->is_write); 830 831 if (pmu_access_el0_disabled(vcpu)) 832 return false; 833 834 get_access_mask(r, &mask, &shift); 835 836 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 837 pmceid &= mask; 838 pmceid >>= shift; 839 840 p->regval = pmceid; 841 842 return true; 843 } 844 845 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 846 { 847 u64 pmcr, val; 848 849 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 850 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 851 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 852 kvm_inject_undefined(vcpu); 853 return false; 854 } 855 856 return true; 857 } 858 859 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 860 u64 *val) 861 { 862 u64 idx; 863 864 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 865 /* PMCCNTR_EL0 */ 866 idx = ARMV8_PMU_CYCLE_IDX; 867 else 868 /* PMEVCNTRn_EL0 */ 869 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 870 871 *val = kvm_pmu_get_counter_value(vcpu, idx); 872 return 0; 873 } 874 875 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 876 struct sys_reg_params *p, 877 const struct sys_reg_desc *r) 878 { 879 u64 idx = ~0UL; 880 881 if (r->CRn == 9 && r->CRm == 13) { 882 if (r->Op2 == 2) { 883 /* PMXEVCNTR_EL0 */ 884 if (pmu_access_event_counter_el0_disabled(vcpu)) 885 return false; 886 887 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 888 & ARMV8_PMU_COUNTER_MASK; 889 } else if (r->Op2 == 0) { 890 /* PMCCNTR_EL0 */ 891 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 892 return false; 893 894 idx = ARMV8_PMU_CYCLE_IDX; 895 } 896 } else if (r->CRn == 0 && r->CRm == 9) { 897 /* PMCCNTR */ 898 if (pmu_access_event_counter_el0_disabled(vcpu)) 899 return false; 900 901 idx = ARMV8_PMU_CYCLE_IDX; 902 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 903 /* PMEVCNTRn_EL0 */ 904 if (pmu_access_event_counter_el0_disabled(vcpu)) 905 return false; 906 907 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 908 } 909 910 /* Catch any decoding mistake */ 911 WARN_ON(idx == ~0UL); 912 913 if (!pmu_counter_idx_valid(vcpu, idx)) 914 return false; 915 916 if (p->is_write) { 917 if (pmu_access_el0_disabled(vcpu)) 918 return false; 919 920 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 921 } else { 922 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 923 } 924 925 return true; 926 } 927 928 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 929 const struct sys_reg_desc *r) 930 { 931 u64 idx, reg; 932 933 if (pmu_access_el0_disabled(vcpu)) 934 return false; 935 936 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 937 /* PMXEVTYPER_EL0 */ 938 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 939 reg = PMEVTYPER0_EL0 + idx; 940 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 941 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 942 if (idx == ARMV8_PMU_CYCLE_IDX) 943 reg = PMCCFILTR_EL0; 944 else 945 /* PMEVTYPERn_EL0 */ 946 reg = PMEVTYPER0_EL0 + idx; 947 } else { 948 BUG(); 949 } 950 951 if (!pmu_counter_idx_valid(vcpu, idx)) 952 return false; 953 954 if (p->is_write) { 955 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 956 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 957 kvm_vcpu_pmu_restore_guest(vcpu); 958 } else { 959 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 960 } 961 962 return true; 963 } 964 965 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 966 const struct sys_reg_desc *r) 967 { 968 u64 val, mask; 969 970 if (pmu_access_el0_disabled(vcpu)) 971 return false; 972 973 mask = kvm_pmu_valid_counter_mask(vcpu); 974 if (p->is_write) { 975 val = p->regval & mask; 976 if (r->Op2 & 0x1) { 977 /* accessing PMCNTENSET_EL0 */ 978 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 979 kvm_pmu_enable_counter_mask(vcpu, val); 980 kvm_vcpu_pmu_restore_guest(vcpu); 981 } else { 982 /* accessing PMCNTENCLR_EL0 */ 983 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 984 kvm_pmu_disable_counter_mask(vcpu, val); 985 } 986 } else { 987 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 988 } 989 990 return true; 991 } 992 993 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 994 const struct sys_reg_desc *r) 995 { 996 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 997 998 if (check_pmu_access_disabled(vcpu, 0)) 999 return false; 1000 1001 if (p->is_write) { 1002 u64 val = p->regval & mask; 1003 1004 if (r->Op2 & 0x1) 1005 /* accessing PMINTENSET_EL1 */ 1006 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1007 else 1008 /* accessing PMINTENCLR_EL1 */ 1009 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1010 } else { 1011 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1012 } 1013 1014 return true; 1015 } 1016 1017 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1018 const struct sys_reg_desc *r) 1019 { 1020 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1021 1022 if (pmu_access_el0_disabled(vcpu)) 1023 return false; 1024 1025 if (p->is_write) { 1026 if (r->CRm & 0x2) 1027 /* accessing PMOVSSET_EL0 */ 1028 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1029 else 1030 /* accessing PMOVSCLR_EL0 */ 1031 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1032 } else { 1033 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1034 } 1035 1036 return true; 1037 } 1038 1039 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1040 const struct sys_reg_desc *r) 1041 { 1042 u64 mask; 1043 1044 if (!p->is_write) 1045 return read_from_write_only(vcpu, p, r); 1046 1047 if (pmu_write_swinc_el0_disabled(vcpu)) 1048 return false; 1049 1050 mask = kvm_pmu_valid_counter_mask(vcpu); 1051 kvm_pmu_software_increment(vcpu, p->regval & mask); 1052 return true; 1053 } 1054 1055 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1056 const struct sys_reg_desc *r) 1057 { 1058 if (p->is_write) { 1059 if (!vcpu_mode_priv(vcpu)) { 1060 kvm_inject_undefined(vcpu); 1061 return false; 1062 } 1063 1064 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1065 p->regval & ARMV8_PMU_USERENR_MASK; 1066 } else { 1067 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1068 & ARMV8_PMU_USERENR_MASK; 1069 } 1070 1071 return true; 1072 } 1073 1074 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1075 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1076 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1077 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1078 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1079 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1080 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1081 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1082 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1083 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1084 1085 #define PMU_SYS_REG(r) \ 1086 SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility 1087 1088 /* Macro to expand the PMEVCNTRn_EL0 register */ 1089 #define PMU_PMEVCNTR_EL0(n) \ 1090 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \ 1091 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1092 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1093 1094 /* Macro to expand the PMEVTYPERn_EL0 register */ 1095 #define PMU_PMEVTYPER_EL0(n) \ 1096 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \ 1097 .reset = reset_pmevtyper, \ 1098 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1099 1100 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1101 const struct sys_reg_desc *r) 1102 { 1103 kvm_inject_undefined(vcpu); 1104 1105 return false; 1106 } 1107 1108 /* Macro to expand the AMU counter and type registers*/ 1109 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1110 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1111 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1112 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1113 1114 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1115 const struct sys_reg_desc *rd) 1116 { 1117 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1118 } 1119 1120 /* 1121 * If we land here on a PtrAuth access, that is because we didn't 1122 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1123 * way this happens is when the guest does not have PtrAuth support 1124 * enabled. 1125 */ 1126 #define __PTRAUTH_KEY(k) \ 1127 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1128 .visibility = ptrauth_visibility} 1129 1130 #define PTRAUTH_KEY(k) \ 1131 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1132 __PTRAUTH_KEY(k ## KEYHI_EL1) 1133 1134 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1135 struct sys_reg_params *p, 1136 const struct sys_reg_desc *r) 1137 { 1138 enum kvm_arch_timers tmr; 1139 enum kvm_arch_timer_regs treg; 1140 u64 reg = reg_to_encoding(r); 1141 1142 switch (reg) { 1143 case SYS_CNTP_TVAL_EL0: 1144 case SYS_AARCH32_CNTP_TVAL: 1145 tmr = TIMER_PTIMER; 1146 treg = TIMER_REG_TVAL; 1147 break; 1148 case SYS_CNTP_CTL_EL0: 1149 case SYS_AARCH32_CNTP_CTL: 1150 tmr = TIMER_PTIMER; 1151 treg = TIMER_REG_CTL; 1152 break; 1153 case SYS_CNTP_CVAL_EL0: 1154 case SYS_AARCH32_CNTP_CVAL: 1155 tmr = TIMER_PTIMER; 1156 treg = TIMER_REG_CVAL; 1157 break; 1158 default: 1159 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1160 kvm_inject_undefined(vcpu); 1161 return false; 1162 } 1163 1164 if (p->is_write) 1165 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1166 else 1167 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1168 1169 return true; 1170 } 1171 1172 static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu) 1173 { 1174 if (kvm_vcpu_has_pmu(vcpu)) 1175 return vcpu->kvm->arch.dfr0_pmuver.imp; 1176 1177 return vcpu->kvm->arch.dfr0_pmuver.unimp; 1178 } 1179 1180 static u8 perfmon_to_pmuver(u8 perfmon) 1181 { 1182 switch (perfmon) { 1183 case ID_DFR0_EL1_PerfMon_PMUv3: 1184 return ID_AA64DFR0_EL1_PMUVer_IMP; 1185 case ID_DFR0_EL1_PerfMon_IMPDEF: 1186 return ID_AA64DFR0_EL1_PMUVer_IMP_DEF; 1187 default: 1188 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1189 return perfmon; 1190 } 1191 } 1192 1193 static u8 pmuver_to_perfmon(u8 pmuver) 1194 { 1195 switch (pmuver) { 1196 case ID_AA64DFR0_EL1_PMUVer_IMP: 1197 return ID_DFR0_EL1_PerfMon_PMUv3; 1198 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1199 return ID_DFR0_EL1_PerfMon_IMPDEF; 1200 default: 1201 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1202 return pmuver; 1203 } 1204 } 1205 1206 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1207 static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r) 1208 { 1209 u32 id = reg_to_encoding(r); 1210 u64 val; 1211 1212 if (sysreg_visible_as_raz(vcpu, r)) 1213 return 0; 1214 1215 val = read_sanitised_ftr_reg(id); 1216 1217 switch (id) { 1218 case SYS_ID_AA64PFR0_EL1: 1219 if (!vcpu_has_sve(vcpu)) 1220 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); 1221 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); 1222 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); 1223 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); 1224 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); 1225 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); 1226 if (kvm_vgic_global_state.type == VGIC_V3) { 1227 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); 1228 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1); 1229 } 1230 break; 1231 case SYS_ID_AA64PFR1_EL1: 1232 if (!kvm_has_mte(vcpu->kvm)) 1233 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1234 1235 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1236 break; 1237 case SYS_ID_AA64ISAR1_EL1: 1238 if (!vcpu_has_ptrauth(vcpu)) 1239 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1240 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1241 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1242 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1243 break; 1244 case SYS_ID_AA64ISAR2_EL1: 1245 if (!vcpu_has_ptrauth(vcpu)) 1246 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1247 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1248 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1249 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1250 break; 1251 case SYS_ID_AA64DFR0_EL1: 1252 /* Limit debug to ARMv8.0 */ 1253 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); 1254 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6); 1255 /* Set PMUver to the required version */ 1256 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); 1257 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), 1258 vcpu_pmuver(vcpu)); 1259 /* Hide SPE from guests */ 1260 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); 1261 break; 1262 case SYS_ID_DFR0_EL1: 1263 val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); 1264 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), 1265 pmuver_to_perfmon(vcpu_pmuver(vcpu))); 1266 break; 1267 case SYS_ID_AA64MMFR2_EL1: 1268 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1269 break; 1270 case SYS_ID_MMFR4_EL1: 1271 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1272 break; 1273 } 1274 1275 return val; 1276 } 1277 1278 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1279 const struct sys_reg_desc *r) 1280 { 1281 u32 id = reg_to_encoding(r); 1282 1283 switch (id) { 1284 case SYS_ID_AA64ZFR0_EL1: 1285 if (!vcpu_has_sve(vcpu)) 1286 return REG_RAZ; 1287 break; 1288 } 1289 1290 return 0; 1291 } 1292 1293 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1294 const struct sys_reg_desc *r) 1295 { 1296 /* 1297 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1298 * EL. Promote to RAZ/WI in order to guarantee consistency between 1299 * systems. 1300 */ 1301 if (!kvm_supports_32bit_el0()) 1302 return REG_RAZ | REG_USER_WI; 1303 1304 return id_visibility(vcpu, r); 1305 } 1306 1307 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1308 const struct sys_reg_desc *r) 1309 { 1310 return REG_RAZ; 1311 } 1312 1313 /* cpufeature ID register access trap handlers */ 1314 1315 static bool access_id_reg(struct kvm_vcpu *vcpu, 1316 struct sys_reg_params *p, 1317 const struct sys_reg_desc *r) 1318 { 1319 if (p->is_write) 1320 return write_to_read_only(vcpu, p, r); 1321 1322 p->regval = read_id_reg(vcpu, r); 1323 if (vcpu_has_nv(vcpu)) 1324 access_nested_id_reg(vcpu, p, r); 1325 1326 return true; 1327 } 1328 1329 /* Visibility overrides for SVE-specific control registers */ 1330 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1331 const struct sys_reg_desc *rd) 1332 { 1333 if (vcpu_has_sve(vcpu)) 1334 return 0; 1335 1336 return REG_HIDDEN; 1337 } 1338 1339 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1340 const struct sys_reg_desc *rd, 1341 u64 val) 1342 { 1343 u8 csv2, csv3; 1344 1345 /* 1346 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as 1347 * it doesn't promise more than what is actually provided (the 1348 * guest could otherwise be covered in ectoplasmic residue). 1349 */ 1350 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV2_SHIFT); 1351 if (csv2 > 1 || 1352 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) 1353 return -EINVAL; 1354 1355 /* Same thing for CSV3 */ 1356 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV3_SHIFT); 1357 if (csv3 > 1 || 1358 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) 1359 return -EINVAL; 1360 1361 /* We can only differ with CSV[23], and anything else is an error */ 1362 val ^= read_id_reg(vcpu, rd); 1363 val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) | 1364 ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3)); 1365 if (val) 1366 return -EINVAL; 1367 1368 vcpu->kvm->arch.pfr0_csv2 = csv2; 1369 vcpu->kvm->arch.pfr0_csv3 = csv3; 1370 1371 return 0; 1372 } 1373 1374 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1375 const struct sys_reg_desc *rd, 1376 u64 val) 1377 { 1378 u8 pmuver, host_pmuver; 1379 bool valid_pmu; 1380 1381 host_pmuver = kvm_arm_pmu_get_pmuver_limit(); 1382 1383 /* 1384 * Allow AA64DFR0_EL1.PMUver to be set from userspace as long 1385 * as it doesn't promise more than what the HW gives us. We 1386 * allow an IMPDEF PMU though, only if no PMU is supported 1387 * (KVM backward compatibility handling). 1388 */ 1389 pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val); 1390 if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver)) 1391 return -EINVAL; 1392 1393 valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF); 1394 1395 /* Make sure view register and PMU support do match */ 1396 if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) 1397 return -EINVAL; 1398 1399 /* We can only differ with PMUver, and anything else is an error */ 1400 val ^= read_id_reg(vcpu, rd); 1401 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); 1402 if (val) 1403 return -EINVAL; 1404 1405 if (valid_pmu) 1406 vcpu->kvm->arch.dfr0_pmuver.imp = pmuver; 1407 else 1408 vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver; 1409 1410 return 0; 1411 } 1412 1413 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1414 const struct sys_reg_desc *rd, 1415 u64 val) 1416 { 1417 u8 perfmon, host_perfmon; 1418 bool valid_pmu; 1419 1420 host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1421 1422 /* 1423 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1424 * it doesn't promise more than what the HW gives us on the 1425 * AArch64 side (as everything is emulated with that), and 1426 * that this is a PMUv3. 1427 */ 1428 perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val); 1429 if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) || 1430 (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)) 1431 return -EINVAL; 1432 1433 valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_EL1_PerfMon_IMPDEF); 1434 1435 /* Make sure view register and PMU support do match */ 1436 if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) 1437 return -EINVAL; 1438 1439 /* We can only differ with PerfMon, and anything else is an error */ 1440 val ^= read_id_reg(vcpu, rd); 1441 val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); 1442 if (val) 1443 return -EINVAL; 1444 1445 if (valid_pmu) 1446 vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon); 1447 else 1448 vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon); 1449 1450 return 0; 1451 } 1452 1453 /* 1454 * cpufeature ID register user accessors 1455 * 1456 * For now, these registers are immutable for userspace, so no values 1457 * are stored, and for set_id_reg() we don't allow the effective value 1458 * to be changed. 1459 */ 1460 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1461 u64 *val) 1462 { 1463 *val = read_id_reg(vcpu, rd); 1464 return 0; 1465 } 1466 1467 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1468 u64 val) 1469 { 1470 /* This is what we mean by invariant: you can't change it. */ 1471 if (val != read_id_reg(vcpu, rd)) 1472 return -EINVAL; 1473 1474 return 0; 1475 } 1476 1477 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1478 u64 *val) 1479 { 1480 *val = 0; 1481 return 0; 1482 } 1483 1484 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1485 u64 val) 1486 { 1487 return 0; 1488 } 1489 1490 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1491 const struct sys_reg_desc *r) 1492 { 1493 if (p->is_write) 1494 return write_to_read_only(vcpu, p, r); 1495 1496 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1497 return true; 1498 } 1499 1500 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1501 const struct sys_reg_desc *r) 1502 { 1503 if (p->is_write) 1504 return write_to_read_only(vcpu, p, r); 1505 1506 p->regval = __vcpu_sys_reg(vcpu, r->reg); 1507 return true; 1508 } 1509 1510 /* 1511 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 1512 * by the physical CPU which the vcpu currently resides in. 1513 */ 1514 static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1515 { 1516 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1517 u64 clidr; 1518 u8 loc; 1519 1520 if ((ctr_el0 & CTR_EL0_IDC)) { 1521 /* 1522 * Data cache clean to the PoU is not required so LoUU and LoUIS 1523 * will not be set and a unified cache, which will be marked as 1524 * LoC, will be added. 1525 * 1526 * If not DIC, let the unified cache L2 so that an instruction 1527 * cache can be added as L1 later. 1528 */ 1529 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 1530 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 1531 } else { 1532 /* 1533 * Data cache clean to the PoU is required so let L1 have a data 1534 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 1535 * it can be marked as LoC too. 1536 */ 1537 loc = 1; 1538 clidr = 1 << CLIDR_LOUU_SHIFT; 1539 clidr |= 1 << CLIDR_LOUIS_SHIFT; 1540 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 1541 } 1542 1543 /* 1544 * Instruction cache invalidation to the PoU is required so let L1 have 1545 * an instruction cache. If L1 already has a data cache, it will be 1546 * CACHE_TYPE_SEPARATE. 1547 */ 1548 if (!(ctr_el0 & CTR_EL0_DIC)) 1549 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 1550 1551 clidr |= loc << CLIDR_LOC_SHIFT; 1552 1553 /* 1554 * Add tag cache unified to data cache. Allocation tags and data are 1555 * unified in a cache line so that it looks valid even if there is only 1556 * one cache line. 1557 */ 1558 if (kvm_has_mte(vcpu->kvm)) 1559 clidr |= 2 << CLIDR_TTYPE_SHIFT(loc); 1560 1561 __vcpu_sys_reg(vcpu, r->reg) = clidr; 1562 } 1563 1564 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1565 u64 val) 1566 { 1567 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1568 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 1569 1570 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 1571 return -EINVAL; 1572 1573 __vcpu_sys_reg(vcpu, rd->reg) = val; 1574 1575 return 0; 1576 } 1577 1578 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1579 const struct sys_reg_desc *r) 1580 { 1581 int reg = r->reg; 1582 1583 if (p->is_write) 1584 vcpu_write_sys_reg(vcpu, p->regval, reg); 1585 else 1586 p->regval = vcpu_read_sys_reg(vcpu, reg); 1587 return true; 1588 } 1589 1590 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1591 const struct sys_reg_desc *r) 1592 { 1593 u32 csselr; 1594 1595 if (p->is_write) 1596 return write_to_read_only(vcpu, p, r); 1597 1598 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1599 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 1600 if (csselr < CSSELR_MAX) 1601 p->regval = get_ccsidr(vcpu, csselr); 1602 1603 return true; 1604 } 1605 1606 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 1607 const struct sys_reg_desc *rd) 1608 { 1609 if (kvm_has_mte(vcpu->kvm)) 1610 return 0; 1611 1612 return REG_HIDDEN; 1613 } 1614 1615 #define MTE_REG(name) { \ 1616 SYS_DESC(SYS_##name), \ 1617 .access = undef_access, \ 1618 .reset = reset_unknown, \ 1619 .reg = name, \ 1620 .visibility = mte_visibility, \ 1621 } 1622 1623 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 1624 const struct sys_reg_desc *rd) 1625 { 1626 if (vcpu_has_nv(vcpu)) 1627 return 0; 1628 1629 return REG_HIDDEN; 1630 } 1631 1632 #define EL2_REG(name, acc, rst, v) { \ 1633 SYS_DESC(SYS_##name), \ 1634 .access = acc, \ 1635 .reset = rst, \ 1636 .reg = name, \ 1637 .visibility = el2_visibility, \ 1638 .val = v, \ 1639 } 1640 1641 /* 1642 * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when 1643 * HCR_EL2.E2H==1, and only in the sysreg table for convenience of 1644 * handling traps. Given that, they are always hidden from userspace. 1645 */ 1646 static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, 1647 const struct sys_reg_desc *rd) 1648 { 1649 return REG_HIDDEN_USER; 1650 } 1651 1652 #define EL12_REG(name, acc, rst, v) { \ 1653 SYS_DESC(SYS_##name##_EL12), \ 1654 .access = acc, \ 1655 .reset = rst, \ 1656 .reg = name##_EL1, \ 1657 .val = v, \ 1658 .visibility = elx2_visibility, \ 1659 } 1660 1661 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1662 #define ID_SANITISED(name) { \ 1663 SYS_DESC(SYS_##name), \ 1664 .access = access_id_reg, \ 1665 .get_user = get_id_reg, \ 1666 .set_user = set_id_reg, \ 1667 .visibility = id_visibility, \ 1668 } 1669 1670 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1671 #define AA32_ID_SANITISED(name) { \ 1672 SYS_DESC(SYS_##name), \ 1673 .access = access_id_reg, \ 1674 .get_user = get_id_reg, \ 1675 .set_user = set_id_reg, \ 1676 .visibility = aa32_id_visibility, \ 1677 } 1678 1679 /* 1680 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1681 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1682 * (1 <= crm < 8, 0 <= Op2 < 8). 1683 */ 1684 #define ID_UNALLOCATED(crm, op2) { \ 1685 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1686 .access = access_id_reg, \ 1687 .get_user = get_id_reg, \ 1688 .set_user = set_id_reg, \ 1689 .visibility = raz_visibility \ 1690 } 1691 1692 /* 1693 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1694 * For now, these are exposed just like unallocated ID regs: they appear 1695 * RAZ for the guest. 1696 */ 1697 #define ID_HIDDEN(name) { \ 1698 SYS_DESC(SYS_##name), \ 1699 .access = access_id_reg, \ 1700 .get_user = get_id_reg, \ 1701 .set_user = set_id_reg, \ 1702 .visibility = raz_visibility, \ 1703 } 1704 1705 static bool access_sp_el1(struct kvm_vcpu *vcpu, 1706 struct sys_reg_params *p, 1707 const struct sys_reg_desc *r) 1708 { 1709 if (p->is_write) 1710 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 1711 else 1712 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 1713 1714 return true; 1715 } 1716 1717 static bool access_elr(struct kvm_vcpu *vcpu, 1718 struct sys_reg_params *p, 1719 const struct sys_reg_desc *r) 1720 { 1721 if (p->is_write) 1722 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 1723 else 1724 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 1725 1726 return true; 1727 } 1728 1729 static bool access_spsr(struct kvm_vcpu *vcpu, 1730 struct sys_reg_params *p, 1731 const struct sys_reg_desc *r) 1732 { 1733 if (p->is_write) 1734 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 1735 else 1736 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 1737 1738 return true; 1739 } 1740 1741 /* 1742 * Architected system registers. 1743 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1744 * 1745 * Debug handling: We do trap most, if not all debug related system 1746 * registers. The implementation is good enough to ensure that a guest 1747 * can use these with minimal performance degradation. The drawback is 1748 * that we don't implement any of the external debug architecture. 1749 * This should be revisited if we ever encounter a more demanding 1750 * guest... 1751 */ 1752 static const struct sys_reg_desc sys_reg_descs[] = { 1753 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1754 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1755 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1756 1757 DBG_BCR_BVR_WCR_WVR_EL1(0), 1758 DBG_BCR_BVR_WCR_WVR_EL1(1), 1759 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1760 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1761 DBG_BCR_BVR_WCR_WVR_EL1(2), 1762 DBG_BCR_BVR_WCR_WVR_EL1(3), 1763 DBG_BCR_BVR_WCR_WVR_EL1(4), 1764 DBG_BCR_BVR_WCR_WVR_EL1(5), 1765 DBG_BCR_BVR_WCR_WVR_EL1(6), 1766 DBG_BCR_BVR_WCR_WVR_EL1(7), 1767 DBG_BCR_BVR_WCR_WVR_EL1(8), 1768 DBG_BCR_BVR_WCR_WVR_EL1(9), 1769 DBG_BCR_BVR_WCR_WVR_EL1(10), 1770 DBG_BCR_BVR_WCR_WVR_EL1(11), 1771 DBG_BCR_BVR_WCR_WVR_EL1(12), 1772 DBG_BCR_BVR_WCR_WVR_EL1(13), 1773 DBG_BCR_BVR_WCR_WVR_EL1(14), 1774 DBG_BCR_BVR_WCR_WVR_EL1(15), 1775 1776 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1777 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 1778 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 1779 SYS_OSLSR_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 1780 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1781 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1782 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1783 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1784 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1785 1786 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1787 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1788 // DBGDTR[TR]X_EL0 share the same encoding 1789 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1790 1791 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1792 1793 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1794 1795 /* 1796 * ID regs: all ID_SANITISED() entries here must have corresponding 1797 * entries in arm64_ftr_regs[]. 1798 */ 1799 1800 /* AArch64 mappings of the AArch32 ID registers */ 1801 /* CRm=1 */ 1802 AA32_ID_SANITISED(ID_PFR0_EL1), 1803 AA32_ID_SANITISED(ID_PFR1_EL1), 1804 { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg, 1805 .get_user = get_id_reg, .set_user = set_id_dfr0_el1, 1806 .visibility = aa32_id_visibility, }, 1807 ID_HIDDEN(ID_AFR0_EL1), 1808 AA32_ID_SANITISED(ID_MMFR0_EL1), 1809 AA32_ID_SANITISED(ID_MMFR1_EL1), 1810 AA32_ID_SANITISED(ID_MMFR2_EL1), 1811 AA32_ID_SANITISED(ID_MMFR3_EL1), 1812 1813 /* CRm=2 */ 1814 AA32_ID_SANITISED(ID_ISAR0_EL1), 1815 AA32_ID_SANITISED(ID_ISAR1_EL1), 1816 AA32_ID_SANITISED(ID_ISAR2_EL1), 1817 AA32_ID_SANITISED(ID_ISAR3_EL1), 1818 AA32_ID_SANITISED(ID_ISAR4_EL1), 1819 AA32_ID_SANITISED(ID_ISAR5_EL1), 1820 AA32_ID_SANITISED(ID_MMFR4_EL1), 1821 AA32_ID_SANITISED(ID_ISAR6_EL1), 1822 1823 /* CRm=3 */ 1824 AA32_ID_SANITISED(MVFR0_EL1), 1825 AA32_ID_SANITISED(MVFR1_EL1), 1826 AA32_ID_SANITISED(MVFR2_EL1), 1827 ID_UNALLOCATED(3,3), 1828 AA32_ID_SANITISED(ID_PFR2_EL1), 1829 ID_HIDDEN(ID_DFR1_EL1), 1830 AA32_ID_SANITISED(ID_MMFR5_EL1), 1831 ID_UNALLOCATED(3,7), 1832 1833 /* AArch64 ID registers */ 1834 /* CRm=4 */ 1835 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, 1836 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, 1837 ID_SANITISED(ID_AA64PFR1_EL1), 1838 ID_UNALLOCATED(4,2), 1839 ID_UNALLOCATED(4,3), 1840 ID_SANITISED(ID_AA64ZFR0_EL1), 1841 ID_HIDDEN(ID_AA64SMFR0_EL1), 1842 ID_UNALLOCATED(4,6), 1843 ID_UNALLOCATED(4,7), 1844 1845 /* CRm=5 */ 1846 { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg, 1847 .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, }, 1848 ID_SANITISED(ID_AA64DFR1_EL1), 1849 ID_UNALLOCATED(5,2), 1850 ID_UNALLOCATED(5,3), 1851 ID_HIDDEN(ID_AA64AFR0_EL1), 1852 ID_HIDDEN(ID_AA64AFR1_EL1), 1853 ID_UNALLOCATED(5,6), 1854 ID_UNALLOCATED(5,7), 1855 1856 /* CRm=6 */ 1857 ID_SANITISED(ID_AA64ISAR0_EL1), 1858 ID_SANITISED(ID_AA64ISAR1_EL1), 1859 ID_SANITISED(ID_AA64ISAR2_EL1), 1860 ID_UNALLOCATED(6,3), 1861 ID_UNALLOCATED(6,4), 1862 ID_UNALLOCATED(6,5), 1863 ID_UNALLOCATED(6,6), 1864 ID_UNALLOCATED(6,7), 1865 1866 /* CRm=7 */ 1867 ID_SANITISED(ID_AA64MMFR0_EL1), 1868 ID_SANITISED(ID_AA64MMFR1_EL1), 1869 ID_SANITISED(ID_AA64MMFR2_EL1), 1870 ID_UNALLOCATED(7,3), 1871 ID_UNALLOCATED(7,4), 1872 ID_UNALLOCATED(7,5), 1873 ID_UNALLOCATED(7,6), 1874 ID_UNALLOCATED(7,7), 1875 1876 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1877 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1878 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1879 1880 MTE_REG(RGSR_EL1), 1881 MTE_REG(GCR_EL1), 1882 1883 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1884 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 1885 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 1886 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 1887 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1888 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1889 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1890 1891 PTRAUTH_KEY(APIA), 1892 PTRAUTH_KEY(APIB), 1893 PTRAUTH_KEY(APDA), 1894 PTRAUTH_KEY(APDB), 1895 PTRAUTH_KEY(APGA), 1896 1897 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 1898 { SYS_DESC(SYS_ELR_EL1), access_elr}, 1899 1900 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1901 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1902 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1903 1904 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1905 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1906 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1907 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1908 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1909 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1910 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1911 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1912 1913 MTE_REG(TFSR_EL1), 1914 MTE_REG(TFSRE0_EL1), 1915 1916 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1917 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1918 1919 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 1920 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 1921 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 1922 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 1923 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 1924 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 1925 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 1926 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 1927 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 1928 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 1929 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 1930 /* PMBIDR_EL1 is not trapped */ 1931 1932 { PMU_SYS_REG(SYS_PMINTENSET_EL1), 1933 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1934 { PMU_SYS_REG(SYS_PMINTENCLR_EL1), 1935 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1936 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 1937 1938 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1939 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1940 1941 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1942 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1943 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1944 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1945 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1946 1947 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 1948 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1949 1950 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1951 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1952 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1953 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1954 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1955 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1956 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1957 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1958 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1959 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1960 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1961 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1962 1963 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1964 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1965 1966 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 1967 1968 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1969 1970 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1971 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 1972 .set_user = set_clidr }, 1973 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 1974 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 1975 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1976 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1977 { SYS_DESC(SYS_SVCR), undef_access }, 1978 1979 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, 1980 .reset = reset_pmcr, .reg = PMCR_EL0 }, 1981 { PMU_SYS_REG(SYS_PMCNTENSET_EL0), 1982 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1983 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0), 1984 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1985 { PMU_SYS_REG(SYS_PMOVSCLR_EL0), 1986 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1987 /* 1988 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 1989 * previously (and pointlessly) advertised in the past... 1990 */ 1991 { PMU_SYS_REG(SYS_PMSWINC_EL0), 1992 .get_user = get_raz_reg, .set_user = set_wi_reg, 1993 .access = access_pmswinc, .reset = NULL }, 1994 { PMU_SYS_REG(SYS_PMSELR_EL0), 1995 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 1996 { PMU_SYS_REG(SYS_PMCEID0_EL0), 1997 .access = access_pmceid, .reset = NULL }, 1998 { PMU_SYS_REG(SYS_PMCEID1_EL0), 1999 .access = access_pmceid, .reset = NULL }, 2000 { PMU_SYS_REG(SYS_PMCCNTR_EL0), 2001 .access = access_pmu_evcntr, .reset = reset_unknown, 2002 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2003 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0), 2004 .access = access_pmu_evtyper, .reset = NULL }, 2005 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0), 2006 .access = access_pmu_evcntr, .reset = NULL }, 2007 /* 2008 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2009 * in 32bit mode. Here we choose to reset it as zero for consistency. 2010 */ 2011 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr, 2012 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2013 { PMU_SYS_REG(SYS_PMOVSSET_EL0), 2014 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 2015 2016 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2017 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2018 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2019 2020 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2021 2022 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2023 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2024 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2025 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2026 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2027 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2028 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2029 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2030 AMU_AMEVCNTR0_EL0(0), 2031 AMU_AMEVCNTR0_EL0(1), 2032 AMU_AMEVCNTR0_EL0(2), 2033 AMU_AMEVCNTR0_EL0(3), 2034 AMU_AMEVCNTR0_EL0(4), 2035 AMU_AMEVCNTR0_EL0(5), 2036 AMU_AMEVCNTR0_EL0(6), 2037 AMU_AMEVCNTR0_EL0(7), 2038 AMU_AMEVCNTR0_EL0(8), 2039 AMU_AMEVCNTR0_EL0(9), 2040 AMU_AMEVCNTR0_EL0(10), 2041 AMU_AMEVCNTR0_EL0(11), 2042 AMU_AMEVCNTR0_EL0(12), 2043 AMU_AMEVCNTR0_EL0(13), 2044 AMU_AMEVCNTR0_EL0(14), 2045 AMU_AMEVCNTR0_EL0(15), 2046 AMU_AMEVTYPER0_EL0(0), 2047 AMU_AMEVTYPER0_EL0(1), 2048 AMU_AMEVTYPER0_EL0(2), 2049 AMU_AMEVTYPER0_EL0(3), 2050 AMU_AMEVTYPER0_EL0(4), 2051 AMU_AMEVTYPER0_EL0(5), 2052 AMU_AMEVTYPER0_EL0(6), 2053 AMU_AMEVTYPER0_EL0(7), 2054 AMU_AMEVTYPER0_EL0(8), 2055 AMU_AMEVTYPER0_EL0(9), 2056 AMU_AMEVTYPER0_EL0(10), 2057 AMU_AMEVTYPER0_EL0(11), 2058 AMU_AMEVTYPER0_EL0(12), 2059 AMU_AMEVTYPER0_EL0(13), 2060 AMU_AMEVTYPER0_EL0(14), 2061 AMU_AMEVTYPER0_EL0(15), 2062 AMU_AMEVCNTR1_EL0(0), 2063 AMU_AMEVCNTR1_EL0(1), 2064 AMU_AMEVCNTR1_EL0(2), 2065 AMU_AMEVCNTR1_EL0(3), 2066 AMU_AMEVCNTR1_EL0(4), 2067 AMU_AMEVCNTR1_EL0(5), 2068 AMU_AMEVCNTR1_EL0(6), 2069 AMU_AMEVCNTR1_EL0(7), 2070 AMU_AMEVCNTR1_EL0(8), 2071 AMU_AMEVCNTR1_EL0(9), 2072 AMU_AMEVCNTR1_EL0(10), 2073 AMU_AMEVCNTR1_EL0(11), 2074 AMU_AMEVCNTR1_EL0(12), 2075 AMU_AMEVCNTR1_EL0(13), 2076 AMU_AMEVCNTR1_EL0(14), 2077 AMU_AMEVCNTR1_EL0(15), 2078 AMU_AMEVTYPER1_EL0(0), 2079 AMU_AMEVTYPER1_EL0(1), 2080 AMU_AMEVTYPER1_EL0(2), 2081 AMU_AMEVTYPER1_EL0(3), 2082 AMU_AMEVTYPER1_EL0(4), 2083 AMU_AMEVTYPER1_EL0(5), 2084 AMU_AMEVTYPER1_EL0(6), 2085 AMU_AMEVTYPER1_EL0(7), 2086 AMU_AMEVTYPER1_EL0(8), 2087 AMU_AMEVTYPER1_EL0(9), 2088 AMU_AMEVTYPER1_EL0(10), 2089 AMU_AMEVTYPER1_EL0(11), 2090 AMU_AMEVTYPER1_EL0(12), 2091 AMU_AMEVTYPER1_EL0(13), 2092 AMU_AMEVTYPER1_EL0(14), 2093 AMU_AMEVTYPER1_EL0(15), 2094 2095 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2096 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2097 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2098 2099 /* PMEVCNTRn_EL0 */ 2100 PMU_PMEVCNTR_EL0(0), 2101 PMU_PMEVCNTR_EL0(1), 2102 PMU_PMEVCNTR_EL0(2), 2103 PMU_PMEVCNTR_EL0(3), 2104 PMU_PMEVCNTR_EL0(4), 2105 PMU_PMEVCNTR_EL0(5), 2106 PMU_PMEVCNTR_EL0(6), 2107 PMU_PMEVCNTR_EL0(7), 2108 PMU_PMEVCNTR_EL0(8), 2109 PMU_PMEVCNTR_EL0(9), 2110 PMU_PMEVCNTR_EL0(10), 2111 PMU_PMEVCNTR_EL0(11), 2112 PMU_PMEVCNTR_EL0(12), 2113 PMU_PMEVCNTR_EL0(13), 2114 PMU_PMEVCNTR_EL0(14), 2115 PMU_PMEVCNTR_EL0(15), 2116 PMU_PMEVCNTR_EL0(16), 2117 PMU_PMEVCNTR_EL0(17), 2118 PMU_PMEVCNTR_EL0(18), 2119 PMU_PMEVCNTR_EL0(19), 2120 PMU_PMEVCNTR_EL0(20), 2121 PMU_PMEVCNTR_EL0(21), 2122 PMU_PMEVCNTR_EL0(22), 2123 PMU_PMEVCNTR_EL0(23), 2124 PMU_PMEVCNTR_EL0(24), 2125 PMU_PMEVCNTR_EL0(25), 2126 PMU_PMEVCNTR_EL0(26), 2127 PMU_PMEVCNTR_EL0(27), 2128 PMU_PMEVCNTR_EL0(28), 2129 PMU_PMEVCNTR_EL0(29), 2130 PMU_PMEVCNTR_EL0(30), 2131 /* PMEVTYPERn_EL0 */ 2132 PMU_PMEVTYPER_EL0(0), 2133 PMU_PMEVTYPER_EL0(1), 2134 PMU_PMEVTYPER_EL0(2), 2135 PMU_PMEVTYPER_EL0(3), 2136 PMU_PMEVTYPER_EL0(4), 2137 PMU_PMEVTYPER_EL0(5), 2138 PMU_PMEVTYPER_EL0(6), 2139 PMU_PMEVTYPER_EL0(7), 2140 PMU_PMEVTYPER_EL0(8), 2141 PMU_PMEVTYPER_EL0(9), 2142 PMU_PMEVTYPER_EL0(10), 2143 PMU_PMEVTYPER_EL0(11), 2144 PMU_PMEVTYPER_EL0(12), 2145 PMU_PMEVTYPER_EL0(13), 2146 PMU_PMEVTYPER_EL0(14), 2147 PMU_PMEVTYPER_EL0(15), 2148 PMU_PMEVTYPER_EL0(16), 2149 PMU_PMEVTYPER_EL0(17), 2150 PMU_PMEVTYPER_EL0(18), 2151 PMU_PMEVTYPER_EL0(19), 2152 PMU_PMEVTYPER_EL0(20), 2153 PMU_PMEVTYPER_EL0(21), 2154 PMU_PMEVTYPER_EL0(22), 2155 PMU_PMEVTYPER_EL0(23), 2156 PMU_PMEVTYPER_EL0(24), 2157 PMU_PMEVTYPER_EL0(25), 2158 PMU_PMEVTYPER_EL0(26), 2159 PMU_PMEVTYPER_EL0(27), 2160 PMU_PMEVTYPER_EL0(28), 2161 PMU_PMEVTYPER_EL0(29), 2162 PMU_PMEVTYPER_EL0(30), 2163 /* 2164 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2165 * in 32bit mode. Here we choose to reset it as zero for consistency. 2166 */ 2167 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper, 2168 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2169 2170 EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0), 2171 EL2_REG(VMPIDR_EL2, access_rw, reset_unknown, 0), 2172 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 2173 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 2174 EL2_REG(HCR_EL2, access_rw, reset_val, 0), 2175 EL2_REG(MDCR_EL2, access_rw, reset_val, 0), 2176 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_EL2_DEFAULT ), 2177 EL2_REG(HSTR_EL2, access_rw, reset_val, 0), 2178 EL2_REG(HACR_EL2, access_rw, reset_val, 0), 2179 2180 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 2181 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 2182 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 2183 EL2_REG(VTTBR_EL2, access_rw, reset_val, 0), 2184 EL2_REG(VTCR_EL2, access_rw, reset_val, 0), 2185 2186 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 2187 EL2_REG(SPSR_EL2, access_rw, reset_val, 0), 2188 EL2_REG(ELR_EL2, access_rw, reset_val, 0), 2189 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 2190 2191 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 2192 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 2193 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 2194 EL2_REG(ESR_EL2, access_rw, reset_val, 0), 2195 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 2196 2197 EL2_REG(FAR_EL2, access_rw, reset_val, 0), 2198 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 2199 2200 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 2201 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 2202 2203 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 2204 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 2205 { SYS_DESC(SYS_RMR_EL2), trap_undef }, 2206 2207 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 2208 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 2209 2210 EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0), 2211 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 2212 2213 EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078), 2214 EL12_REG(CPACR, access_rw, reset_val, 0), 2215 EL12_REG(TTBR0, access_vm_reg, reset_unknown, 0), 2216 EL12_REG(TTBR1, access_vm_reg, reset_unknown, 0), 2217 EL12_REG(TCR, access_vm_reg, reset_val, 0), 2218 { SYS_DESC(SYS_SPSR_EL12), access_spsr}, 2219 { SYS_DESC(SYS_ELR_EL12), access_elr}, 2220 EL12_REG(AFSR0, access_vm_reg, reset_unknown, 0), 2221 EL12_REG(AFSR1, access_vm_reg, reset_unknown, 0), 2222 EL12_REG(ESR, access_vm_reg, reset_unknown, 0), 2223 EL12_REG(FAR, access_vm_reg, reset_unknown, 0), 2224 EL12_REG(MAIR, access_vm_reg, reset_unknown, 0), 2225 EL12_REG(AMAIR, access_vm_reg, reset_amair_el1, 0), 2226 EL12_REG(VBAR, access_rw, reset_val, 0), 2227 EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0), 2228 EL12_REG(CNTKCTL, access_rw, reset_val, 0), 2229 2230 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 2231 }; 2232 2233 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 2234 struct sys_reg_params *p, 2235 const struct sys_reg_desc *r) 2236 { 2237 if (p->is_write) { 2238 return ignore_write(vcpu, p); 2239 } else { 2240 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 2241 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2242 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); 2243 2244 p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | 2245 (((dfr >> ID_AA64DFR0_EL1_BRPs_SHIFT) & 0xf) << 24) | 2246 (((dfr >> ID_AA64DFR0_EL1_CTX_CMPs_SHIFT) & 0xf) << 20) 2247 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); 2248 return true; 2249 } 2250 } 2251 2252 /* 2253 * AArch32 debug register mappings 2254 * 2255 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 2256 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 2257 * 2258 * None of the other registers share their location, so treat them as 2259 * if they were 64bit. 2260 */ 2261 #define DBG_BCR_BVR_WCR_WVR(n) \ 2262 /* DBGBVRn */ \ 2263 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 2264 /* DBGBCRn */ \ 2265 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 2266 /* DBGWVRn */ \ 2267 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 2268 /* DBGWCRn */ \ 2269 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 2270 2271 #define DBGBXVR(n) \ 2272 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 2273 2274 /* 2275 * Trapped cp14 registers. We generally ignore most of the external 2276 * debug, on the principle that they don't really make sense to a 2277 * guest. Revisit this one day, would this principle change. 2278 */ 2279 static const struct sys_reg_desc cp14_regs[] = { 2280 /* DBGDIDR */ 2281 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 2282 /* DBGDTRRXext */ 2283 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 2284 2285 DBG_BCR_BVR_WCR_WVR(0), 2286 /* DBGDSCRint */ 2287 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 2288 DBG_BCR_BVR_WCR_WVR(1), 2289 /* DBGDCCINT */ 2290 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 2291 /* DBGDSCRext */ 2292 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 2293 DBG_BCR_BVR_WCR_WVR(2), 2294 /* DBGDTR[RT]Xint */ 2295 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 2296 /* DBGDTR[RT]Xext */ 2297 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 2298 DBG_BCR_BVR_WCR_WVR(3), 2299 DBG_BCR_BVR_WCR_WVR(4), 2300 DBG_BCR_BVR_WCR_WVR(5), 2301 /* DBGWFAR */ 2302 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 2303 /* DBGOSECCR */ 2304 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 2305 DBG_BCR_BVR_WCR_WVR(6), 2306 /* DBGVCR */ 2307 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 2308 DBG_BCR_BVR_WCR_WVR(7), 2309 DBG_BCR_BVR_WCR_WVR(8), 2310 DBG_BCR_BVR_WCR_WVR(9), 2311 DBG_BCR_BVR_WCR_WVR(10), 2312 DBG_BCR_BVR_WCR_WVR(11), 2313 DBG_BCR_BVR_WCR_WVR(12), 2314 DBG_BCR_BVR_WCR_WVR(13), 2315 DBG_BCR_BVR_WCR_WVR(14), 2316 DBG_BCR_BVR_WCR_WVR(15), 2317 2318 /* DBGDRAR (32bit) */ 2319 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 2320 2321 DBGBXVR(0), 2322 /* DBGOSLAR */ 2323 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 2324 DBGBXVR(1), 2325 /* DBGOSLSR */ 2326 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 2327 DBGBXVR(2), 2328 DBGBXVR(3), 2329 /* DBGOSDLR */ 2330 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 2331 DBGBXVR(4), 2332 /* DBGPRCR */ 2333 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 2334 DBGBXVR(5), 2335 DBGBXVR(6), 2336 DBGBXVR(7), 2337 DBGBXVR(8), 2338 DBGBXVR(9), 2339 DBGBXVR(10), 2340 DBGBXVR(11), 2341 DBGBXVR(12), 2342 DBGBXVR(13), 2343 DBGBXVR(14), 2344 DBGBXVR(15), 2345 2346 /* DBGDSAR (32bit) */ 2347 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 2348 2349 /* DBGDEVID2 */ 2350 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 2351 /* DBGDEVID1 */ 2352 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 2353 /* DBGDEVID */ 2354 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 2355 /* DBGCLAIMSET */ 2356 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 2357 /* DBGCLAIMCLR */ 2358 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 2359 /* DBGAUTHSTATUS */ 2360 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 2361 }; 2362 2363 /* Trapped cp14 64bit registers */ 2364 static const struct sys_reg_desc cp14_64_regs[] = { 2365 /* DBGDRAR (64bit) */ 2366 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 2367 2368 /* DBGDSAR (64bit) */ 2369 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 2370 }; 2371 2372 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 2373 AA32(_map), \ 2374 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 2375 .visibility = pmu_visibility 2376 2377 /* Macro to expand the PMEVCNTRn register */ 2378 #define PMU_PMEVCNTR(n) \ 2379 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 2380 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 2381 .access = access_pmu_evcntr } 2382 2383 /* Macro to expand the PMEVTYPERn register */ 2384 #define PMU_PMEVTYPER(n) \ 2385 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 2386 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 2387 .access = access_pmu_evtyper } 2388 /* 2389 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 2390 * depending on the way they are accessed (as a 32bit or a 64bit 2391 * register). 2392 */ 2393 static const struct sys_reg_desc cp15_regs[] = { 2394 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 2395 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 2396 /* ACTLR */ 2397 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 2398 /* ACTLR2 */ 2399 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 2400 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2401 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 2402 /* TTBCR */ 2403 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 2404 /* TTBCR2 */ 2405 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 2406 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 2407 /* DFSR */ 2408 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 2409 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 2410 /* ADFSR */ 2411 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 2412 /* AIFSR */ 2413 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 2414 /* DFAR */ 2415 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 2416 /* IFAR */ 2417 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 2418 2419 /* 2420 * DC{C,I,CI}SW operations: 2421 */ 2422 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 2423 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 2424 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 2425 2426 /* PMU */ 2427 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 2428 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 2429 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 2430 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 2431 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 2432 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 2433 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 2434 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 2435 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 2436 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 2437 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 2438 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 2439 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 2440 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 2441 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 2442 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 2443 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 2444 /* PMMIR */ 2445 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 2446 2447 /* PRRR/MAIR0 */ 2448 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 2449 /* NMRR/MAIR1 */ 2450 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 2451 /* AMAIR0 */ 2452 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 2453 /* AMAIR1 */ 2454 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 2455 2456 /* ICC_SRE */ 2457 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 2458 2459 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 2460 2461 /* Arch Tmers */ 2462 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 2463 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 2464 2465 /* PMEVCNTRn */ 2466 PMU_PMEVCNTR(0), 2467 PMU_PMEVCNTR(1), 2468 PMU_PMEVCNTR(2), 2469 PMU_PMEVCNTR(3), 2470 PMU_PMEVCNTR(4), 2471 PMU_PMEVCNTR(5), 2472 PMU_PMEVCNTR(6), 2473 PMU_PMEVCNTR(7), 2474 PMU_PMEVCNTR(8), 2475 PMU_PMEVCNTR(9), 2476 PMU_PMEVCNTR(10), 2477 PMU_PMEVCNTR(11), 2478 PMU_PMEVCNTR(12), 2479 PMU_PMEVCNTR(13), 2480 PMU_PMEVCNTR(14), 2481 PMU_PMEVCNTR(15), 2482 PMU_PMEVCNTR(16), 2483 PMU_PMEVCNTR(17), 2484 PMU_PMEVCNTR(18), 2485 PMU_PMEVCNTR(19), 2486 PMU_PMEVCNTR(20), 2487 PMU_PMEVCNTR(21), 2488 PMU_PMEVCNTR(22), 2489 PMU_PMEVCNTR(23), 2490 PMU_PMEVCNTR(24), 2491 PMU_PMEVCNTR(25), 2492 PMU_PMEVCNTR(26), 2493 PMU_PMEVCNTR(27), 2494 PMU_PMEVCNTR(28), 2495 PMU_PMEVCNTR(29), 2496 PMU_PMEVCNTR(30), 2497 /* PMEVTYPERn */ 2498 PMU_PMEVTYPER(0), 2499 PMU_PMEVTYPER(1), 2500 PMU_PMEVTYPER(2), 2501 PMU_PMEVTYPER(3), 2502 PMU_PMEVTYPER(4), 2503 PMU_PMEVTYPER(5), 2504 PMU_PMEVTYPER(6), 2505 PMU_PMEVTYPER(7), 2506 PMU_PMEVTYPER(8), 2507 PMU_PMEVTYPER(9), 2508 PMU_PMEVTYPER(10), 2509 PMU_PMEVTYPER(11), 2510 PMU_PMEVTYPER(12), 2511 PMU_PMEVTYPER(13), 2512 PMU_PMEVTYPER(14), 2513 PMU_PMEVTYPER(15), 2514 PMU_PMEVTYPER(16), 2515 PMU_PMEVTYPER(17), 2516 PMU_PMEVTYPER(18), 2517 PMU_PMEVTYPER(19), 2518 PMU_PMEVTYPER(20), 2519 PMU_PMEVTYPER(21), 2520 PMU_PMEVTYPER(22), 2521 PMU_PMEVTYPER(23), 2522 PMU_PMEVTYPER(24), 2523 PMU_PMEVTYPER(25), 2524 PMU_PMEVTYPER(26), 2525 PMU_PMEVTYPER(27), 2526 PMU_PMEVTYPER(28), 2527 PMU_PMEVTYPER(29), 2528 PMU_PMEVTYPER(30), 2529 /* PMCCFILTR */ 2530 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 2531 2532 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2533 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2534 2535 /* CCSIDR2 */ 2536 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 2537 2538 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 2539 }; 2540 2541 static const struct sys_reg_desc cp15_64_regs[] = { 2542 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2543 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 2544 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2545 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 2546 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2547 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2548 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2549 }; 2550 2551 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2552 bool is_32) 2553 { 2554 unsigned int i; 2555 2556 for (i = 0; i < n; i++) { 2557 if (!is_32 && table[i].reg && !table[i].reset) { 2558 kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i); 2559 return false; 2560 } 2561 2562 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2563 kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1); 2564 return false; 2565 } 2566 } 2567 2568 return true; 2569 } 2570 2571 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2572 { 2573 kvm_inject_undefined(vcpu); 2574 return 1; 2575 } 2576 2577 static void perform_access(struct kvm_vcpu *vcpu, 2578 struct sys_reg_params *params, 2579 const struct sys_reg_desc *r) 2580 { 2581 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2582 2583 /* Check for regs disabled by runtime config */ 2584 if (sysreg_hidden(vcpu, r)) { 2585 kvm_inject_undefined(vcpu); 2586 return; 2587 } 2588 2589 /* 2590 * Not having an accessor means that we have configured a trap 2591 * that we don't know how to handle. This certainly qualifies 2592 * as a gross bug that should be fixed right away. 2593 */ 2594 BUG_ON(!r->access); 2595 2596 /* Skip instruction if instructed so */ 2597 if (likely(r->access(vcpu, params, r))) 2598 kvm_incr_pc(vcpu); 2599 } 2600 2601 /* 2602 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2603 * call the corresponding trap handler. 2604 * 2605 * @params: pointer to the descriptor of the access 2606 * @table: array of trap descriptors 2607 * @num: size of the trap descriptor array 2608 * 2609 * Return true if the access has been handled, false if not. 2610 */ 2611 static bool emulate_cp(struct kvm_vcpu *vcpu, 2612 struct sys_reg_params *params, 2613 const struct sys_reg_desc *table, 2614 size_t num) 2615 { 2616 const struct sys_reg_desc *r; 2617 2618 if (!table) 2619 return false; /* Not handled */ 2620 2621 r = find_reg(params, table, num); 2622 2623 if (r) { 2624 perform_access(vcpu, params, r); 2625 return true; 2626 } 2627 2628 /* Not handled */ 2629 return false; 2630 } 2631 2632 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2633 struct sys_reg_params *params) 2634 { 2635 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2636 int cp = -1; 2637 2638 switch (esr_ec) { 2639 case ESR_ELx_EC_CP15_32: 2640 case ESR_ELx_EC_CP15_64: 2641 cp = 15; 2642 break; 2643 case ESR_ELx_EC_CP14_MR: 2644 case ESR_ELx_EC_CP14_64: 2645 cp = 14; 2646 break; 2647 default: 2648 WARN_ON(1); 2649 } 2650 2651 print_sys_reg_msg(params, 2652 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2653 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2654 kvm_inject_undefined(vcpu); 2655 } 2656 2657 /** 2658 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2659 * @vcpu: The VCPU pointer 2660 * @run: The kvm_run struct 2661 */ 2662 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2663 const struct sys_reg_desc *global, 2664 size_t nr_global) 2665 { 2666 struct sys_reg_params params; 2667 u64 esr = kvm_vcpu_get_esr(vcpu); 2668 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2669 int Rt2 = (esr >> 10) & 0x1f; 2670 2671 params.CRm = (esr >> 1) & 0xf; 2672 params.is_write = ((esr & 1) == 0); 2673 2674 params.Op0 = 0; 2675 params.Op1 = (esr >> 16) & 0xf; 2676 params.Op2 = 0; 2677 params.CRn = 0; 2678 2679 /* 2680 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2681 * backends between AArch32 and AArch64, we get away with it. 2682 */ 2683 if (params.is_write) { 2684 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2685 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2686 } 2687 2688 /* 2689 * If the table contains a handler, handle the 2690 * potential register operation in the case of a read and return 2691 * with success. 2692 */ 2693 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 2694 /* Split up the value between registers for the read side */ 2695 if (!params.is_write) { 2696 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2697 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2698 } 2699 2700 return 1; 2701 } 2702 2703 unhandled_cp_access(vcpu, ¶ms); 2704 return 1; 2705 } 2706 2707 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 2708 2709 /* 2710 * The CP10 ID registers are architecturally mapped to AArch64 feature 2711 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 2712 * from AArch32. 2713 */ 2714 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 2715 { 2716 u8 reg_id = (esr >> 10) & 0xf; 2717 bool valid; 2718 2719 params->is_write = ((esr & 1) == 0); 2720 params->Op0 = 3; 2721 params->Op1 = 0; 2722 params->CRn = 0; 2723 params->CRm = 3; 2724 2725 /* CP10 ID registers are read-only */ 2726 valid = !params->is_write; 2727 2728 switch (reg_id) { 2729 /* MVFR0 */ 2730 case 0b0111: 2731 params->Op2 = 0; 2732 break; 2733 /* MVFR1 */ 2734 case 0b0110: 2735 params->Op2 = 1; 2736 break; 2737 /* MVFR2 */ 2738 case 0b0101: 2739 params->Op2 = 2; 2740 break; 2741 default: 2742 valid = false; 2743 } 2744 2745 if (valid) 2746 return true; 2747 2748 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 2749 params->is_write ? "write" : "read", reg_id); 2750 return false; 2751 } 2752 2753 /** 2754 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 2755 * VFP Register' from AArch32. 2756 * @vcpu: The vCPU pointer 2757 * 2758 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 2759 * Work out the correct AArch64 system register encoding and reroute to the 2760 * AArch64 system register emulation. 2761 */ 2762 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 2763 { 2764 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2765 u64 esr = kvm_vcpu_get_esr(vcpu); 2766 struct sys_reg_params params; 2767 2768 /* UNDEF on any unhandled register access */ 2769 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 2770 kvm_inject_undefined(vcpu); 2771 return 1; 2772 } 2773 2774 if (emulate_sys_reg(vcpu, ¶ms)) 2775 vcpu_set_reg(vcpu, Rt, params.regval); 2776 2777 return 1; 2778 } 2779 2780 /** 2781 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 2782 * CRn=0, which corresponds to the AArch32 feature 2783 * registers. 2784 * @vcpu: the vCPU pointer 2785 * @params: the system register access parameters. 2786 * 2787 * Our cp15 system register tables do not enumerate the AArch32 feature 2788 * registers. Conveniently, our AArch64 table does, and the AArch32 system 2789 * register encoding can be trivially remapped into the AArch64 for the feature 2790 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 2791 * 2792 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 2793 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 2794 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 2795 * treat undefined registers in this range as RAZ. 2796 */ 2797 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 2798 struct sys_reg_params *params) 2799 { 2800 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2801 2802 /* Treat impossible writes to RO registers as UNDEFINED */ 2803 if (params->is_write) { 2804 unhandled_cp_access(vcpu, params); 2805 return 1; 2806 } 2807 2808 params->Op0 = 3; 2809 2810 /* 2811 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 2812 * Avoid conflicting with future expansion of AArch64 feature registers 2813 * and simply treat them as RAZ here. 2814 */ 2815 if (params->CRm > 3) 2816 params->regval = 0; 2817 else if (!emulate_sys_reg(vcpu, params)) 2818 return 1; 2819 2820 vcpu_set_reg(vcpu, Rt, params->regval); 2821 return 1; 2822 } 2823 2824 /** 2825 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2826 * @vcpu: The VCPU pointer 2827 * @run: The kvm_run struct 2828 */ 2829 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2830 struct sys_reg_params *params, 2831 const struct sys_reg_desc *global, 2832 size_t nr_global) 2833 { 2834 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2835 2836 params->regval = vcpu_get_reg(vcpu, Rt); 2837 2838 if (emulate_cp(vcpu, params, global, nr_global)) { 2839 if (!params->is_write) 2840 vcpu_set_reg(vcpu, Rt, params->regval); 2841 return 1; 2842 } 2843 2844 unhandled_cp_access(vcpu, params); 2845 return 1; 2846 } 2847 2848 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2849 { 2850 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2851 } 2852 2853 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2854 { 2855 struct sys_reg_params params; 2856 2857 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 2858 2859 /* 2860 * Certain AArch32 ID registers are handled by rerouting to the AArch64 2861 * system register table. Registers in the ID range where CRm=0 are 2862 * excluded from this scheme as they do not trivially map into AArch64 2863 * system register encodings. 2864 */ 2865 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 2866 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 2867 2868 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 2869 } 2870 2871 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2872 { 2873 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2874 } 2875 2876 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2877 { 2878 struct sys_reg_params params; 2879 2880 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 2881 2882 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 2883 } 2884 2885 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2886 { 2887 // See ARM DDI 0487E.a, section D12.3.2 2888 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2889 } 2890 2891 /** 2892 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 2893 * @vcpu: The VCPU pointer 2894 * @params: Decoded system register parameters 2895 * 2896 * Return: true if the system register access was successful, false otherwise. 2897 */ 2898 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 2899 struct sys_reg_params *params) 2900 { 2901 const struct sys_reg_desc *r; 2902 2903 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2904 2905 if (likely(r)) { 2906 perform_access(vcpu, params, r); 2907 return true; 2908 } 2909 2910 if (is_imp_def_sys_reg(params)) { 2911 kvm_inject_undefined(vcpu); 2912 } else { 2913 print_sys_reg_msg(params, 2914 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2915 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2916 kvm_inject_undefined(vcpu); 2917 } 2918 return false; 2919 } 2920 2921 /** 2922 * kvm_reset_sys_regs - sets system registers to reset value 2923 * @vcpu: The VCPU pointer 2924 * 2925 * This function finds the right table above and sets the registers on the 2926 * virtual CPU struct to their architecturally defined reset values. 2927 */ 2928 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2929 { 2930 unsigned long i; 2931 2932 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2933 if (sys_reg_descs[i].reset) 2934 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2935 } 2936 2937 /** 2938 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2939 * @vcpu: The VCPU pointer 2940 */ 2941 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2942 { 2943 struct sys_reg_params params; 2944 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2945 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2946 2947 trace_kvm_handle_sys_reg(esr); 2948 2949 params = esr_sys64_to_params(esr); 2950 params.regval = vcpu_get_reg(vcpu, Rt); 2951 2952 if (!emulate_sys_reg(vcpu, ¶ms)) 2953 return 1; 2954 2955 if (!params.is_write) 2956 vcpu_set_reg(vcpu, Rt, params.regval); 2957 return 1; 2958 } 2959 2960 /****************************************************************************** 2961 * Userspace API 2962 *****************************************************************************/ 2963 2964 static bool index_to_params(u64 id, struct sys_reg_params *params) 2965 { 2966 switch (id & KVM_REG_SIZE_MASK) { 2967 case KVM_REG_SIZE_U64: 2968 /* Any unused index bits means it's not valid. */ 2969 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2970 | KVM_REG_ARM_COPROC_MASK 2971 | KVM_REG_ARM64_SYSREG_OP0_MASK 2972 | KVM_REG_ARM64_SYSREG_OP1_MASK 2973 | KVM_REG_ARM64_SYSREG_CRN_MASK 2974 | KVM_REG_ARM64_SYSREG_CRM_MASK 2975 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2976 return false; 2977 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2978 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2979 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2980 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2981 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2982 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2983 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2984 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2985 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2986 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2987 return true; 2988 default: 2989 return false; 2990 } 2991 } 2992 2993 const struct sys_reg_desc *get_reg_by_id(u64 id, 2994 const struct sys_reg_desc table[], 2995 unsigned int num) 2996 { 2997 struct sys_reg_params params; 2998 2999 if (!index_to_params(id, ¶ms)) 3000 return NULL; 3001 3002 return find_reg(¶ms, table, num); 3003 } 3004 3005 /* Decode an index value, and find the sys_reg_desc entry. */ 3006 static const struct sys_reg_desc * 3007 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 3008 const struct sys_reg_desc table[], unsigned int num) 3009 3010 { 3011 const struct sys_reg_desc *r; 3012 3013 /* We only do sys_reg for now. */ 3014 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 3015 return NULL; 3016 3017 r = get_reg_by_id(id, table, num); 3018 3019 /* Not saved in the sys_reg array and not otherwise accessible? */ 3020 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 3021 r = NULL; 3022 3023 return r; 3024 } 3025 3026 /* 3027 * These are the invariant sys_reg registers: we let the guest see the 3028 * host versions of these, so they're part of the guest state. 3029 * 3030 * A future CPU may provide a mechanism to present different values to 3031 * the guest, or a future kvm may trap them. 3032 */ 3033 3034 #define FUNCTION_INVARIANT(reg) \ 3035 static void get_##reg(struct kvm_vcpu *v, \ 3036 const struct sys_reg_desc *r) \ 3037 { \ 3038 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 3039 } 3040 3041 FUNCTION_INVARIANT(midr_el1) 3042 FUNCTION_INVARIANT(revidr_el1) 3043 FUNCTION_INVARIANT(aidr_el1) 3044 3045 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 3046 { 3047 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 3048 } 3049 3050 /* ->val is filled in by kvm_sys_reg_table_init() */ 3051 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 3052 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 3053 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 3054 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 3055 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 3056 }; 3057 3058 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 3059 { 3060 const struct sys_reg_desc *r; 3061 3062 r = get_reg_by_id(id, invariant_sys_regs, 3063 ARRAY_SIZE(invariant_sys_regs)); 3064 if (!r) 3065 return -ENOENT; 3066 3067 return put_user(r->val, uaddr); 3068 } 3069 3070 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 3071 { 3072 const struct sys_reg_desc *r; 3073 u64 val; 3074 3075 r = get_reg_by_id(id, invariant_sys_regs, 3076 ARRAY_SIZE(invariant_sys_regs)); 3077 if (!r) 3078 return -ENOENT; 3079 3080 if (get_user(val, uaddr)) 3081 return -EFAULT; 3082 3083 /* This is what we mean by invariant: you can't change it. */ 3084 if (r->val != val) 3085 return -EINVAL; 3086 3087 return 0; 3088 } 3089 3090 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 3091 { 3092 u32 val; 3093 u32 __user *uval = uaddr; 3094 3095 /* Fail if we have unknown bits set. */ 3096 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 3097 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 3098 return -ENOENT; 3099 3100 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 3101 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 3102 if (KVM_REG_SIZE(id) != 4) 3103 return -ENOENT; 3104 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 3105 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 3106 if (val >= CSSELR_MAX) 3107 return -ENOENT; 3108 3109 return put_user(get_ccsidr(vcpu, val), uval); 3110 default: 3111 return -ENOENT; 3112 } 3113 } 3114 3115 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 3116 { 3117 u32 val, newval; 3118 u32 __user *uval = uaddr; 3119 3120 /* Fail if we have unknown bits set. */ 3121 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 3122 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 3123 return -ENOENT; 3124 3125 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 3126 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 3127 if (KVM_REG_SIZE(id) != 4) 3128 return -ENOENT; 3129 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 3130 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 3131 if (val >= CSSELR_MAX) 3132 return -ENOENT; 3133 3134 if (get_user(newval, uval)) 3135 return -EFAULT; 3136 3137 return set_ccsidr(vcpu, val, newval); 3138 default: 3139 return -ENOENT; 3140 } 3141 } 3142 3143 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 3144 const struct sys_reg_desc table[], unsigned int num) 3145 { 3146 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 3147 const struct sys_reg_desc *r; 3148 u64 val; 3149 int ret; 3150 3151 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 3152 if (!r || sysreg_hidden_user(vcpu, r)) 3153 return -ENOENT; 3154 3155 if (r->get_user) { 3156 ret = (r->get_user)(vcpu, r, &val); 3157 } else { 3158 val = __vcpu_sys_reg(vcpu, r->reg); 3159 ret = 0; 3160 } 3161 3162 if (!ret) 3163 ret = put_user(val, uaddr); 3164 3165 return ret; 3166 } 3167 3168 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 3169 { 3170 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 3171 int err; 3172 3173 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 3174 return demux_c15_get(vcpu, reg->id, uaddr); 3175 3176 err = get_invariant_sys_reg(reg->id, uaddr); 3177 if (err != -ENOENT) 3178 return err; 3179 3180 return kvm_sys_reg_get_user(vcpu, reg, 3181 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3182 } 3183 3184 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 3185 const struct sys_reg_desc table[], unsigned int num) 3186 { 3187 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 3188 const struct sys_reg_desc *r; 3189 u64 val; 3190 int ret; 3191 3192 if (get_user(val, uaddr)) 3193 return -EFAULT; 3194 3195 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 3196 if (!r || sysreg_hidden_user(vcpu, r)) 3197 return -ENOENT; 3198 3199 if (sysreg_user_write_ignore(vcpu, r)) 3200 return 0; 3201 3202 if (r->set_user) { 3203 ret = (r->set_user)(vcpu, r, val); 3204 } else { 3205 __vcpu_sys_reg(vcpu, r->reg) = val; 3206 ret = 0; 3207 } 3208 3209 return ret; 3210 } 3211 3212 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 3213 { 3214 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 3215 int err; 3216 3217 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 3218 return demux_c15_set(vcpu, reg->id, uaddr); 3219 3220 err = set_invariant_sys_reg(reg->id, uaddr); 3221 if (err != -ENOENT) 3222 return err; 3223 3224 return kvm_sys_reg_set_user(vcpu, reg, 3225 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3226 } 3227 3228 static unsigned int num_demux_regs(void) 3229 { 3230 return CSSELR_MAX; 3231 } 3232 3233 static int write_demux_regids(u64 __user *uindices) 3234 { 3235 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 3236 unsigned int i; 3237 3238 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 3239 for (i = 0; i < CSSELR_MAX; i++) { 3240 if (put_user(val | i, uindices)) 3241 return -EFAULT; 3242 uindices++; 3243 } 3244 return 0; 3245 } 3246 3247 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 3248 { 3249 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 3250 KVM_REG_ARM64_SYSREG | 3251 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 3252 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 3253 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 3254 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 3255 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 3256 } 3257 3258 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 3259 { 3260 if (!*uind) 3261 return true; 3262 3263 if (put_user(sys_reg_to_index(reg), *uind)) 3264 return false; 3265 3266 (*uind)++; 3267 return true; 3268 } 3269 3270 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 3271 const struct sys_reg_desc *rd, 3272 u64 __user **uind, 3273 unsigned int *total) 3274 { 3275 /* 3276 * Ignore registers we trap but don't save, 3277 * and for which no custom user accessor is provided. 3278 */ 3279 if (!(rd->reg || rd->get_user)) 3280 return 0; 3281 3282 if (sysreg_hidden_user(vcpu, rd)) 3283 return 0; 3284 3285 if (!copy_reg_to_user(rd, uind)) 3286 return -EFAULT; 3287 3288 (*total)++; 3289 return 0; 3290 } 3291 3292 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 3293 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 3294 { 3295 const struct sys_reg_desc *i2, *end2; 3296 unsigned int total = 0; 3297 int err; 3298 3299 i2 = sys_reg_descs; 3300 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 3301 3302 while (i2 != end2) { 3303 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 3304 if (err) 3305 return err; 3306 } 3307 return total; 3308 } 3309 3310 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 3311 { 3312 return ARRAY_SIZE(invariant_sys_regs) 3313 + num_demux_regs() 3314 + walk_sys_regs(vcpu, (u64 __user *)NULL); 3315 } 3316 3317 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 3318 { 3319 unsigned int i; 3320 int err; 3321 3322 /* Then give them all the invariant registers' indices. */ 3323 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 3324 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 3325 return -EFAULT; 3326 uindices++; 3327 } 3328 3329 err = walk_sys_regs(vcpu, uindices); 3330 if (err < 0) 3331 return err; 3332 uindices += err; 3333 3334 return write_demux_regids(uindices); 3335 } 3336 3337 int __init kvm_sys_reg_table_init(void) 3338 { 3339 bool valid = true; 3340 unsigned int i; 3341 3342 /* Make sure tables are unique and in order. */ 3343 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 3344 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 3345 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 3346 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 3347 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 3348 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 3349 3350 if (!valid) 3351 return -EINVAL; 3352 3353 /* We abuse the reset function to overwrite the table itself. */ 3354 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 3355 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 3356 3357 return 0; 3358 } 3359