1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/kvm_host.h> 16 #include <linux/mm.h> 17 #include <linux/printk.h> 18 #include <linux/uaccess.h> 19 20 #include <asm/cacheflush.h> 21 #include <asm/cputype.h> 22 #include <asm/debug-monitors.h> 23 #include <asm/esr.h> 24 #include <asm/kvm_arm.h> 25 #include <asm/kvm_emulate.h> 26 #include <asm/kvm_hyp.h> 27 #include <asm/kvm_mmu.h> 28 #include <asm/kvm_nested.h> 29 #include <asm/perf_event.h> 30 #include <asm/sysreg.h> 31 32 #include <trace/events/kvm.h> 33 34 #include "sys_regs.h" 35 #include "vgic/vgic.h" 36 37 #include "trace.h" 38 39 /* 40 * For AArch32, we only take care of what is being trapped. Anything 41 * that has to do with init and userspace access has to go via the 42 * 64bit interface. 43 */ 44 45 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 46 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 47 u64 val); 48 49 static bool read_from_write_only(struct kvm_vcpu *vcpu, 50 struct sys_reg_params *params, 51 const struct sys_reg_desc *r) 52 { 53 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 54 print_sys_reg_instr(params); 55 kvm_inject_undefined(vcpu); 56 return false; 57 } 58 59 static bool write_to_read_only(struct kvm_vcpu *vcpu, 60 struct sys_reg_params *params, 61 const struct sys_reg_desc *r) 62 { 63 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 64 print_sys_reg_instr(params); 65 kvm_inject_undefined(vcpu); 66 return false; 67 } 68 69 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 70 { 71 u64 val = 0x8badf00d8badf00d; 72 73 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 74 __vcpu_read_sys_reg_from_cpu(reg, &val)) 75 return val; 76 77 return __vcpu_sys_reg(vcpu, reg); 78 } 79 80 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 81 { 82 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 83 __vcpu_write_sys_reg_to_cpu(val, reg)) 84 return; 85 86 __vcpu_sys_reg(vcpu, reg) = val; 87 } 88 89 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 90 #define CSSELR_MAX 14 91 92 /* 93 * Returns the minimum line size for the selected cache, expressed as 94 * Log2(bytes). 95 */ 96 static u8 get_min_cache_line_size(bool icache) 97 { 98 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 99 u8 field; 100 101 if (icache) 102 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 103 else 104 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 105 106 /* 107 * Cache line size is represented as Log2(words) in CTR_EL0. 108 * Log2(bytes) can be derived with the following: 109 * 110 * Log2(words) + 2 = Log2(bytes / 4) + 2 111 * = Log2(bytes) - 2 + 2 112 * = Log2(bytes) 113 */ 114 return field + 2; 115 } 116 117 /* Which cache CCSIDR represents depends on CSSELR value. */ 118 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 119 { 120 u8 line_size; 121 122 if (vcpu->arch.ccsidr) 123 return vcpu->arch.ccsidr[csselr]; 124 125 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 126 127 /* 128 * Fabricate a CCSIDR value as the overriding value does not exist. 129 * The real CCSIDR value will not be used as it can vary by the 130 * physical CPU which the vcpu currently resides in. 131 * 132 * The line size is determined with get_min_cache_line_size(), which 133 * should be valid for all CPUs even if they have different cache 134 * configuration. 135 * 136 * The associativity bits are cleared, meaning the geometry of all data 137 * and unified caches (which are guaranteed to be PIPT and thus 138 * non-aliasing) are 1 set and 1 way. 139 * Guests should not be doing cache operations by set/way at all, and 140 * for this reason, we trap them and attempt to infer the intent, so 141 * that we can flush the entire guest's address space at the appropriate 142 * time. The exposed geometry minimizes the number of the traps. 143 * [If guests should attempt to infer aliasing properties from the 144 * geometry (which is not permitted by the architecture), they would 145 * only do so for virtually indexed caches.] 146 * 147 * We don't check if the cache level exists as it is allowed to return 148 * an UNKNOWN value if not. 149 */ 150 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 151 } 152 153 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 154 { 155 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 156 u32 *ccsidr = vcpu->arch.ccsidr; 157 u32 i; 158 159 if ((val & CCSIDR_EL1_RES0) || 160 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 161 return -EINVAL; 162 163 if (!ccsidr) { 164 if (val == get_ccsidr(vcpu, csselr)) 165 return 0; 166 167 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 168 if (!ccsidr) 169 return -ENOMEM; 170 171 for (i = 0; i < CSSELR_MAX; i++) 172 ccsidr[i] = get_ccsidr(vcpu, i); 173 174 vcpu->arch.ccsidr = ccsidr; 175 } 176 177 ccsidr[csselr] = val; 178 179 return 0; 180 } 181 182 static bool access_rw(struct kvm_vcpu *vcpu, 183 struct sys_reg_params *p, 184 const struct sys_reg_desc *r) 185 { 186 if (p->is_write) 187 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 188 else 189 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 190 191 return true; 192 } 193 194 /* 195 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 196 */ 197 static bool access_dcsw(struct kvm_vcpu *vcpu, 198 struct sys_reg_params *p, 199 const struct sys_reg_desc *r) 200 { 201 if (!p->is_write) 202 return read_from_write_only(vcpu, p, r); 203 204 /* 205 * Only track S/W ops if we don't have FWB. It still indicates 206 * that the guest is a bit broken (S/W operations should only 207 * be done by firmware, knowing that there is only a single 208 * CPU left in the system, and certainly not from non-secure 209 * software). 210 */ 211 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 212 kvm_set_way_flush(vcpu); 213 214 return true; 215 } 216 217 static bool access_dcgsw(struct kvm_vcpu *vcpu, 218 struct sys_reg_params *p, 219 const struct sys_reg_desc *r) 220 { 221 if (!kvm_has_mte(vcpu->kvm)) { 222 kvm_inject_undefined(vcpu); 223 return false; 224 } 225 226 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 227 return access_dcsw(vcpu, p, r); 228 } 229 230 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 231 { 232 switch (r->aarch32_map) { 233 case AA32_LO: 234 *mask = GENMASK_ULL(31, 0); 235 *shift = 0; 236 break; 237 case AA32_HI: 238 *mask = GENMASK_ULL(63, 32); 239 *shift = 32; 240 break; 241 default: 242 *mask = GENMASK_ULL(63, 0); 243 *shift = 0; 244 break; 245 } 246 } 247 248 /* 249 * Generic accessor for VM registers. Only called as long as HCR_TVM 250 * is set. If the guest enables the MMU, we stop trapping the VM 251 * sys_regs and leave it in complete control of the caches. 252 */ 253 static bool access_vm_reg(struct kvm_vcpu *vcpu, 254 struct sys_reg_params *p, 255 const struct sys_reg_desc *r) 256 { 257 bool was_enabled = vcpu_has_cache_enabled(vcpu); 258 u64 val, mask, shift; 259 260 BUG_ON(!p->is_write); 261 262 get_access_mask(r, &mask, &shift); 263 264 if (~mask) { 265 val = vcpu_read_sys_reg(vcpu, r->reg); 266 val &= ~mask; 267 } else { 268 val = 0; 269 } 270 271 val |= (p->regval & (mask >> shift)) << shift; 272 vcpu_write_sys_reg(vcpu, val, r->reg); 273 274 kvm_toggle_cache(vcpu, was_enabled); 275 return true; 276 } 277 278 static bool access_actlr(struct kvm_vcpu *vcpu, 279 struct sys_reg_params *p, 280 const struct sys_reg_desc *r) 281 { 282 u64 mask, shift; 283 284 if (p->is_write) 285 return ignore_write(vcpu, p); 286 287 get_access_mask(r, &mask, &shift); 288 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 289 290 return true; 291 } 292 293 /* 294 * Trap handler for the GICv3 SGI generation system register. 295 * Forward the request to the VGIC emulation. 296 * The cp15_64 code makes sure this automatically works 297 * for both AArch64 and AArch32 accesses. 298 */ 299 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 300 struct sys_reg_params *p, 301 const struct sys_reg_desc *r) 302 { 303 bool g1; 304 305 if (!kvm_has_gicv3(vcpu->kvm)) { 306 kvm_inject_undefined(vcpu); 307 return false; 308 } 309 310 if (!p->is_write) 311 return read_from_write_only(vcpu, p, r); 312 313 /* 314 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 315 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 316 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 317 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 318 * group. 319 */ 320 if (p->Op0 == 0) { /* AArch32 */ 321 switch (p->Op1) { 322 default: /* Keep GCC quiet */ 323 case 0: /* ICC_SGI1R */ 324 g1 = true; 325 break; 326 case 1: /* ICC_ASGI1R */ 327 case 2: /* ICC_SGI0R */ 328 g1 = false; 329 break; 330 } 331 } else { /* AArch64 */ 332 switch (p->Op2) { 333 default: /* Keep GCC quiet */ 334 case 5: /* ICC_SGI1R_EL1 */ 335 g1 = true; 336 break; 337 case 6: /* ICC_ASGI1R_EL1 */ 338 case 7: /* ICC_SGI0R_EL1 */ 339 g1 = false; 340 break; 341 } 342 } 343 344 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 345 346 return true; 347 } 348 349 static bool access_gic_sre(struct kvm_vcpu *vcpu, 350 struct sys_reg_params *p, 351 const struct sys_reg_desc *r) 352 { 353 if (p->is_write) 354 return ignore_write(vcpu, p); 355 356 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 357 return true; 358 } 359 360 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 361 struct sys_reg_params *p, 362 const struct sys_reg_desc *r) 363 { 364 if (p->is_write) 365 return ignore_write(vcpu, p); 366 else 367 return read_zero(vcpu, p); 368 } 369 370 static bool trap_undef(struct kvm_vcpu *vcpu, 371 struct sys_reg_params *p, 372 const struct sys_reg_desc *r) 373 { 374 kvm_inject_undefined(vcpu); 375 return false; 376 } 377 378 /* 379 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 380 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 381 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 382 * treat it separately. 383 */ 384 static bool trap_loregion(struct kvm_vcpu *vcpu, 385 struct sys_reg_params *p, 386 const struct sys_reg_desc *r) 387 { 388 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 389 u32 sr = reg_to_encoding(r); 390 391 if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { 392 kvm_inject_undefined(vcpu); 393 return false; 394 } 395 396 if (p->is_write && sr == SYS_LORID_EL1) 397 return write_to_read_only(vcpu, p, r); 398 399 return trap_raz_wi(vcpu, p, r); 400 } 401 402 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 403 struct sys_reg_params *p, 404 const struct sys_reg_desc *r) 405 { 406 u64 oslsr; 407 408 if (!p->is_write) 409 return read_from_write_only(vcpu, p, r); 410 411 /* Forward the OSLK bit to OSLSR */ 412 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK; 413 if (p->regval & OSLAR_EL1_OSLK) 414 oslsr |= OSLSR_EL1_OSLK; 415 416 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 417 return true; 418 } 419 420 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 421 struct sys_reg_params *p, 422 const struct sys_reg_desc *r) 423 { 424 if (p->is_write) 425 return write_to_read_only(vcpu, p, r); 426 427 p->regval = __vcpu_sys_reg(vcpu, r->reg); 428 return true; 429 } 430 431 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 432 u64 val) 433 { 434 /* 435 * The only modifiable bit is the OSLK bit. Refuse the write if 436 * userspace attempts to change any other bit in the register. 437 */ 438 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 439 return -EINVAL; 440 441 __vcpu_sys_reg(vcpu, rd->reg) = val; 442 return 0; 443 } 444 445 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 446 struct sys_reg_params *p, 447 const struct sys_reg_desc *r) 448 { 449 if (p->is_write) { 450 return ignore_write(vcpu, p); 451 } else { 452 p->regval = read_sysreg(dbgauthstatus_el1); 453 return true; 454 } 455 } 456 457 /* 458 * We want to avoid world-switching all the DBG registers all the 459 * time: 460 * 461 * - If we've touched any debug register, it is likely that we're 462 * going to touch more of them. It then makes sense to disable the 463 * traps and start doing the save/restore dance 464 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 465 * then mandatory to save/restore the registers, as the guest 466 * depends on them. 467 * 468 * For this, we use a DIRTY bit, indicating the guest has modified the 469 * debug registers, used as follow: 470 * 471 * On guest entry: 472 * - If the dirty bit is set (because we're coming back from trapping), 473 * disable the traps, save host registers, restore guest registers. 474 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 475 * set the dirty bit, disable the traps, save host registers, 476 * restore guest registers. 477 * - Otherwise, enable the traps 478 * 479 * On guest exit: 480 * - If the dirty bit is set, save guest registers, restore host 481 * registers and clear the dirty bit. This ensure that the host can 482 * now use the debug registers. 483 */ 484 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 485 struct sys_reg_params *p, 486 const struct sys_reg_desc *r) 487 { 488 access_rw(vcpu, p, r); 489 if (p->is_write) 490 vcpu_set_flag(vcpu, DEBUG_DIRTY); 491 492 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 493 494 return true; 495 } 496 497 /* 498 * reg_to_dbg/dbg_to_reg 499 * 500 * A 32 bit write to a debug register leave top bits alone 501 * A 32 bit read from a debug register only returns the bottom bits 502 * 503 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 504 * switches between host and guest values in future. 505 */ 506 static void reg_to_dbg(struct kvm_vcpu *vcpu, 507 struct sys_reg_params *p, 508 const struct sys_reg_desc *rd, 509 u64 *dbg_reg) 510 { 511 u64 mask, shift, val; 512 513 get_access_mask(rd, &mask, &shift); 514 515 val = *dbg_reg; 516 val &= ~mask; 517 val |= (p->regval & (mask >> shift)) << shift; 518 *dbg_reg = val; 519 520 vcpu_set_flag(vcpu, DEBUG_DIRTY); 521 } 522 523 static void dbg_to_reg(struct kvm_vcpu *vcpu, 524 struct sys_reg_params *p, 525 const struct sys_reg_desc *rd, 526 u64 *dbg_reg) 527 { 528 u64 mask, shift; 529 530 get_access_mask(rd, &mask, &shift); 531 p->regval = (*dbg_reg & mask) >> shift; 532 } 533 534 static bool trap_bvr(struct kvm_vcpu *vcpu, 535 struct sys_reg_params *p, 536 const struct sys_reg_desc *rd) 537 { 538 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 539 540 if (p->is_write) 541 reg_to_dbg(vcpu, p, rd, dbg_reg); 542 else 543 dbg_to_reg(vcpu, p, rd, dbg_reg); 544 545 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 546 547 return true; 548 } 549 550 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 551 u64 val) 552 { 553 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 554 return 0; 555 } 556 557 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 558 u64 *val) 559 { 560 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 561 return 0; 562 } 563 564 static u64 reset_bvr(struct kvm_vcpu *vcpu, 565 const struct sys_reg_desc *rd) 566 { 567 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 568 return rd->val; 569 } 570 571 static bool trap_bcr(struct kvm_vcpu *vcpu, 572 struct sys_reg_params *p, 573 const struct sys_reg_desc *rd) 574 { 575 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 576 577 if (p->is_write) 578 reg_to_dbg(vcpu, p, rd, dbg_reg); 579 else 580 dbg_to_reg(vcpu, p, rd, dbg_reg); 581 582 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 583 584 return true; 585 } 586 587 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 588 u64 val) 589 { 590 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 591 return 0; 592 } 593 594 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 595 u64 *val) 596 { 597 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 598 return 0; 599 } 600 601 static u64 reset_bcr(struct kvm_vcpu *vcpu, 602 const struct sys_reg_desc *rd) 603 { 604 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 605 return rd->val; 606 } 607 608 static bool trap_wvr(struct kvm_vcpu *vcpu, 609 struct sys_reg_params *p, 610 const struct sys_reg_desc *rd) 611 { 612 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 613 614 if (p->is_write) 615 reg_to_dbg(vcpu, p, rd, dbg_reg); 616 else 617 dbg_to_reg(vcpu, p, rd, dbg_reg); 618 619 trace_trap_reg(__func__, rd->CRm, p->is_write, 620 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 621 622 return true; 623 } 624 625 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 626 u64 val) 627 { 628 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 629 return 0; 630 } 631 632 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 633 u64 *val) 634 { 635 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 636 return 0; 637 } 638 639 static u64 reset_wvr(struct kvm_vcpu *vcpu, 640 const struct sys_reg_desc *rd) 641 { 642 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 643 return rd->val; 644 } 645 646 static bool trap_wcr(struct kvm_vcpu *vcpu, 647 struct sys_reg_params *p, 648 const struct sys_reg_desc *rd) 649 { 650 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 651 652 if (p->is_write) 653 reg_to_dbg(vcpu, p, rd, dbg_reg); 654 else 655 dbg_to_reg(vcpu, p, rd, dbg_reg); 656 657 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 658 659 return true; 660 } 661 662 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 663 u64 val) 664 { 665 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 666 return 0; 667 } 668 669 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 670 u64 *val) 671 { 672 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 673 return 0; 674 } 675 676 static u64 reset_wcr(struct kvm_vcpu *vcpu, 677 const struct sys_reg_desc *rd) 678 { 679 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 680 return rd->val; 681 } 682 683 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 684 { 685 u64 amair = read_sysreg(amair_el1); 686 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 687 return amair; 688 } 689 690 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 691 { 692 u64 actlr = read_sysreg(actlr_el1); 693 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 694 return actlr; 695 } 696 697 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 698 { 699 u64 mpidr; 700 701 /* 702 * Map the vcpu_id into the first three affinity level fields of 703 * the MPIDR. We limit the number of VCPUs in level 0 due to a 704 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 705 * of the GICv3 to be able to address each CPU directly when 706 * sending IPIs. 707 */ 708 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 709 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 710 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 711 mpidr |= (1ULL << 31); 712 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 713 714 return mpidr; 715 } 716 717 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 718 const struct sys_reg_desc *r) 719 { 720 if (kvm_vcpu_has_pmu(vcpu)) 721 return 0; 722 723 return REG_HIDDEN; 724 } 725 726 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 727 { 728 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); 729 730 /* No PMU available, any PMU reg may UNDEF... */ 731 if (!kvm_arm_support_pmu_v3()) 732 return 0; 733 734 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; 735 n &= ARMV8_PMU_PMCR_N_MASK; 736 if (n) 737 mask |= GENMASK(n - 1, 0); 738 739 reset_unknown(vcpu, r); 740 __vcpu_sys_reg(vcpu, r->reg) &= mask; 741 742 return __vcpu_sys_reg(vcpu, r->reg); 743 } 744 745 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 746 { 747 reset_unknown(vcpu, r); 748 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 749 750 return __vcpu_sys_reg(vcpu, r->reg); 751 } 752 753 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 754 { 755 reset_unknown(vcpu, r); 756 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK; 757 758 return __vcpu_sys_reg(vcpu, r->reg); 759 } 760 761 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 762 { 763 reset_unknown(vcpu, r); 764 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; 765 766 return __vcpu_sys_reg(vcpu, r->reg); 767 } 768 769 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 770 { 771 u64 pmcr; 772 773 /* No PMU available, PMCR_EL0 may UNDEF... */ 774 if (!kvm_arm_support_pmu_v3()) 775 return 0; 776 777 /* Only preserve PMCR_EL0.N, and reset the rest to 0 */ 778 pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT); 779 if (!kvm_supports_32bit_el0()) 780 pmcr |= ARMV8_PMU_PMCR_LC; 781 782 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 783 784 return __vcpu_sys_reg(vcpu, r->reg); 785 } 786 787 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 788 { 789 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 790 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 791 792 if (!enabled) 793 kvm_inject_undefined(vcpu); 794 795 return !enabled; 796 } 797 798 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 799 { 800 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 801 } 802 803 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 804 { 805 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 806 } 807 808 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 809 { 810 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 811 } 812 813 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 814 { 815 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 816 } 817 818 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 819 const struct sys_reg_desc *r) 820 { 821 u64 val; 822 823 if (pmu_access_el0_disabled(vcpu)) 824 return false; 825 826 if (p->is_write) { 827 /* 828 * Only update writeable bits of PMCR (continuing into 829 * kvm_pmu_handle_pmcr() as well) 830 */ 831 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 832 val &= ~ARMV8_PMU_PMCR_MASK; 833 val |= p->regval & ARMV8_PMU_PMCR_MASK; 834 if (!kvm_supports_32bit_el0()) 835 val |= ARMV8_PMU_PMCR_LC; 836 kvm_pmu_handle_pmcr(vcpu, val); 837 } else { 838 /* PMCR.P & PMCR.C are RAZ */ 839 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 840 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 841 p->regval = val; 842 } 843 844 return true; 845 } 846 847 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 848 const struct sys_reg_desc *r) 849 { 850 if (pmu_access_event_counter_el0_disabled(vcpu)) 851 return false; 852 853 if (p->is_write) 854 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 855 else 856 /* return PMSELR.SEL field */ 857 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 858 & ARMV8_PMU_COUNTER_MASK; 859 860 return true; 861 } 862 863 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 864 const struct sys_reg_desc *r) 865 { 866 u64 pmceid, mask, shift; 867 868 BUG_ON(p->is_write); 869 870 if (pmu_access_el0_disabled(vcpu)) 871 return false; 872 873 get_access_mask(r, &mask, &shift); 874 875 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 876 pmceid &= mask; 877 pmceid >>= shift; 878 879 p->regval = pmceid; 880 881 return true; 882 } 883 884 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 885 { 886 u64 pmcr, val; 887 888 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 889 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 890 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 891 kvm_inject_undefined(vcpu); 892 return false; 893 } 894 895 return true; 896 } 897 898 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 899 u64 *val) 900 { 901 u64 idx; 902 903 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 904 /* PMCCNTR_EL0 */ 905 idx = ARMV8_PMU_CYCLE_IDX; 906 else 907 /* PMEVCNTRn_EL0 */ 908 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 909 910 *val = kvm_pmu_get_counter_value(vcpu, idx); 911 return 0; 912 } 913 914 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 915 struct sys_reg_params *p, 916 const struct sys_reg_desc *r) 917 { 918 u64 idx = ~0UL; 919 920 if (r->CRn == 9 && r->CRm == 13) { 921 if (r->Op2 == 2) { 922 /* PMXEVCNTR_EL0 */ 923 if (pmu_access_event_counter_el0_disabled(vcpu)) 924 return false; 925 926 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 927 & ARMV8_PMU_COUNTER_MASK; 928 } else if (r->Op2 == 0) { 929 /* PMCCNTR_EL0 */ 930 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 931 return false; 932 933 idx = ARMV8_PMU_CYCLE_IDX; 934 } 935 } else if (r->CRn == 0 && r->CRm == 9) { 936 /* PMCCNTR */ 937 if (pmu_access_event_counter_el0_disabled(vcpu)) 938 return false; 939 940 idx = ARMV8_PMU_CYCLE_IDX; 941 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 942 /* PMEVCNTRn_EL0 */ 943 if (pmu_access_event_counter_el0_disabled(vcpu)) 944 return false; 945 946 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 947 } 948 949 /* Catch any decoding mistake */ 950 WARN_ON(idx == ~0UL); 951 952 if (!pmu_counter_idx_valid(vcpu, idx)) 953 return false; 954 955 if (p->is_write) { 956 if (pmu_access_el0_disabled(vcpu)) 957 return false; 958 959 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 960 } else { 961 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 962 } 963 964 return true; 965 } 966 967 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 968 const struct sys_reg_desc *r) 969 { 970 u64 idx, reg; 971 972 if (pmu_access_el0_disabled(vcpu)) 973 return false; 974 975 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 976 /* PMXEVTYPER_EL0 */ 977 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 978 reg = PMEVTYPER0_EL0 + idx; 979 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 980 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 981 if (idx == ARMV8_PMU_CYCLE_IDX) 982 reg = PMCCFILTR_EL0; 983 else 984 /* PMEVTYPERn_EL0 */ 985 reg = PMEVTYPER0_EL0 + idx; 986 } else { 987 BUG(); 988 } 989 990 if (!pmu_counter_idx_valid(vcpu, idx)) 991 return false; 992 993 if (p->is_write) { 994 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 995 kvm_vcpu_pmu_restore_guest(vcpu); 996 } else { 997 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 998 } 999 1000 return true; 1001 } 1002 1003 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1004 const struct sys_reg_desc *r) 1005 { 1006 u64 val, mask; 1007 1008 if (pmu_access_el0_disabled(vcpu)) 1009 return false; 1010 1011 mask = kvm_pmu_valid_counter_mask(vcpu); 1012 if (p->is_write) { 1013 val = p->regval & mask; 1014 if (r->Op2 & 0x1) { 1015 /* accessing PMCNTENSET_EL0 */ 1016 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1017 kvm_pmu_enable_counter_mask(vcpu, val); 1018 kvm_vcpu_pmu_restore_guest(vcpu); 1019 } else { 1020 /* accessing PMCNTENCLR_EL0 */ 1021 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1022 kvm_pmu_disable_counter_mask(vcpu, val); 1023 } 1024 } else { 1025 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1026 } 1027 1028 return true; 1029 } 1030 1031 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1032 const struct sys_reg_desc *r) 1033 { 1034 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1035 1036 if (check_pmu_access_disabled(vcpu, 0)) 1037 return false; 1038 1039 if (p->is_write) { 1040 u64 val = p->regval & mask; 1041 1042 if (r->Op2 & 0x1) 1043 /* accessing PMINTENSET_EL1 */ 1044 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1045 else 1046 /* accessing PMINTENCLR_EL1 */ 1047 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1048 } else { 1049 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1050 } 1051 1052 return true; 1053 } 1054 1055 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1056 const struct sys_reg_desc *r) 1057 { 1058 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1059 1060 if (pmu_access_el0_disabled(vcpu)) 1061 return false; 1062 1063 if (p->is_write) { 1064 if (r->CRm & 0x2) 1065 /* accessing PMOVSSET_EL0 */ 1066 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1067 else 1068 /* accessing PMOVSCLR_EL0 */ 1069 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1070 } else { 1071 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1072 } 1073 1074 return true; 1075 } 1076 1077 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1078 const struct sys_reg_desc *r) 1079 { 1080 u64 mask; 1081 1082 if (!p->is_write) 1083 return read_from_write_only(vcpu, p, r); 1084 1085 if (pmu_write_swinc_el0_disabled(vcpu)) 1086 return false; 1087 1088 mask = kvm_pmu_valid_counter_mask(vcpu); 1089 kvm_pmu_software_increment(vcpu, p->regval & mask); 1090 return true; 1091 } 1092 1093 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1094 const struct sys_reg_desc *r) 1095 { 1096 if (p->is_write) { 1097 if (!vcpu_mode_priv(vcpu)) { 1098 kvm_inject_undefined(vcpu); 1099 return false; 1100 } 1101 1102 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1103 p->regval & ARMV8_PMU_USERENR_MASK; 1104 } else { 1105 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1106 & ARMV8_PMU_USERENR_MASK; 1107 } 1108 1109 return true; 1110 } 1111 1112 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1113 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1114 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1115 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1116 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1117 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1118 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1119 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1120 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1121 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1122 1123 #define PMU_SYS_REG(name) \ 1124 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1125 .visibility = pmu_visibility 1126 1127 /* Macro to expand the PMEVCNTRn_EL0 register */ 1128 #define PMU_PMEVCNTR_EL0(n) \ 1129 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1130 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1131 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1132 1133 /* Macro to expand the PMEVTYPERn_EL0 register */ 1134 #define PMU_PMEVTYPER_EL0(n) \ 1135 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1136 .reset = reset_pmevtyper, \ 1137 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1138 1139 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1140 const struct sys_reg_desc *r) 1141 { 1142 kvm_inject_undefined(vcpu); 1143 1144 return false; 1145 } 1146 1147 /* Macro to expand the AMU counter and type registers*/ 1148 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1149 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1150 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1151 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1152 1153 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1154 const struct sys_reg_desc *rd) 1155 { 1156 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1157 } 1158 1159 /* 1160 * If we land here on a PtrAuth access, that is because we didn't 1161 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1162 * way this happens is when the guest does not have PtrAuth support 1163 * enabled. 1164 */ 1165 #define __PTRAUTH_KEY(k) \ 1166 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1167 .visibility = ptrauth_visibility} 1168 1169 #define PTRAUTH_KEY(k) \ 1170 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1171 __PTRAUTH_KEY(k ## KEYHI_EL1) 1172 1173 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1174 struct sys_reg_params *p, 1175 const struct sys_reg_desc *r) 1176 { 1177 enum kvm_arch_timers tmr; 1178 enum kvm_arch_timer_regs treg; 1179 u64 reg = reg_to_encoding(r); 1180 1181 switch (reg) { 1182 case SYS_CNTP_TVAL_EL0: 1183 case SYS_AARCH32_CNTP_TVAL: 1184 tmr = TIMER_PTIMER; 1185 treg = TIMER_REG_TVAL; 1186 break; 1187 case SYS_CNTP_CTL_EL0: 1188 case SYS_AARCH32_CNTP_CTL: 1189 tmr = TIMER_PTIMER; 1190 treg = TIMER_REG_CTL; 1191 break; 1192 case SYS_CNTP_CVAL_EL0: 1193 case SYS_AARCH32_CNTP_CVAL: 1194 tmr = TIMER_PTIMER; 1195 treg = TIMER_REG_CVAL; 1196 break; 1197 case SYS_CNTPCT_EL0: 1198 case SYS_CNTPCTSS_EL0: 1199 case SYS_AARCH32_CNTPCT: 1200 tmr = TIMER_PTIMER; 1201 treg = TIMER_REG_CNT; 1202 break; 1203 default: 1204 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1205 kvm_inject_undefined(vcpu); 1206 return false; 1207 } 1208 1209 if (p->is_write) 1210 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1211 else 1212 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1213 1214 return true; 1215 } 1216 1217 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1218 s64 new, s64 cur) 1219 { 1220 struct arm64_ftr_bits kvm_ftr = *ftrp; 1221 1222 /* Some features have different safe value type in KVM than host features */ 1223 switch (id) { 1224 case SYS_ID_AA64DFR0_EL1: 1225 if (kvm_ftr.shift == ID_AA64DFR0_EL1_PMUVer_SHIFT) 1226 kvm_ftr.type = FTR_LOWER_SAFE; 1227 break; 1228 case SYS_ID_DFR0_EL1: 1229 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1230 kvm_ftr.type = FTR_LOWER_SAFE; 1231 break; 1232 } 1233 1234 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1235 } 1236 1237 /** 1238 * arm64_check_features() - Check if a feature register value constitutes 1239 * a subset of features indicated by the idreg's KVM sanitised limit. 1240 * 1241 * This function will check if each feature field of @val is the "safe" value 1242 * against idreg's KVM sanitised limit return from reset() callback. 1243 * If a field value in @val is the same as the one in limit, it is always 1244 * considered the safe value regardless For register fields that are not in 1245 * writable, only the value in limit is considered the safe value. 1246 * 1247 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1248 */ 1249 static int arm64_check_features(struct kvm_vcpu *vcpu, 1250 const struct sys_reg_desc *rd, 1251 u64 val) 1252 { 1253 const struct arm64_ftr_reg *ftr_reg; 1254 const struct arm64_ftr_bits *ftrp = NULL; 1255 u32 id = reg_to_encoding(rd); 1256 u64 writable_mask = rd->val; 1257 u64 limit = rd->reset(vcpu, rd); 1258 u64 mask = 0; 1259 1260 /* 1261 * Hidden and unallocated ID registers may not have a corresponding 1262 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1263 * only safe value is 0. 1264 */ 1265 if (sysreg_visible_as_raz(vcpu, rd)) 1266 return val ? -E2BIG : 0; 1267 1268 ftr_reg = get_arm64_ftr_reg(id); 1269 if (!ftr_reg) 1270 return -EINVAL; 1271 1272 ftrp = ftr_reg->ftr_bits; 1273 1274 for (; ftrp && ftrp->width; ftrp++) { 1275 s64 f_val, f_lim, safe_val; 1276 u64 ftr_mask; 1277 1278 ftr_mask = arm64_ftr_mask(ftrp); 1279 if ((ftr_mask & writable_mask) != ftr_mask) 1280 continue; 1281 1282 f_val = arm64_ftr_value(ftrp, val); 1283 f_lim = arm64_ftr_value(ftrp, limit); 1284 mask |= ftr_mask; 1285 1286 if (f_val == f_lim) 1287 safe_val = f_val; 1288 else 1289 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1290 1291 if (safe_val != f_val) 1292 return -E2BIG; 1293 } 1294 1295 /* For fields that are not writable, values in limit are the safe values. */ 1296 if ((val & ~mask) != (limit & ~mask)) 1297 return -E2BIG; 1298 1299 return 0; 1300 } 1301 1302 static u8 pmuver_to_perfmon(u8 pmuver) 1303 { 1304 switch (pmuver) { 1305 case ID_AA64DFR0_EL1_PMUVer_IMP: 1306 return ID_DFR0_EL1_PerfMon_PMUv3; 1307 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1308 return ID_DFR0_EL1_PerfMon_IMPDEF; 1309 default: 1310 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1311 return pmuver; 1312 } 1313 } 1314 1315 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1316 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1317 const struct sys_reg_desc *r) 1318 { 1319 u32 id = reg_to_encoding(r); 1320 u64 val; 1321 1322 if (sysreg_visible_as_raz(vcpu, r)) 1323 return 0; 1324 1325 val = read_sanitised_ftr_reg(id); 1326 1327 switch (id) { 1328 case SYS_ID_AA64PFR1_EL1: 1329 if (!kvm_has_mte(vcpu->kvm)) 1330 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1331 1332 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1333 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac); 1334 break; 1335 case SYS_ID_AA64ISAR1_EL1: 1336 if (!vcpu_has_ptrauth(vcpu)) 1337 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1338 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1339 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1340 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1341 break; 1342 case SYS_ID_AA64ISAR2_EL1: 1343 if (!vcpu_has_ptrauth(vcpu)) 1344 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1345 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1346 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1347 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1348 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS); 1349 break; 1350 case SYS_ID_AA64MMFR2_EL1: 1351 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1352 break; 1353 case SYS_ID_MMFR4_EL1: 1354 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1355 break; 1356 } 1357 1358 return val; 1359 } 1360 1361 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1362 const struct sys_reg_desc *r) 1363 { 1364 return __kvm_read_sanitised_id_reg(vcpu, r); 1365 } 1366 1367 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1368 { 1369 return IDREG(vcpu->kvm, reg_to_encoding(r)); 1370 } 1371 1372 /* 1373 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1374 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 1375 */ 1376 static inline bool is_id_reg(u32 id) 1377 { 1378 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1379 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1380 sys_reg_CRm(id) < 8); 1381 } 1382 1383 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1384 const struct sys_reg_desc *r) 1385 { 1386 u32 id = reg_to_encoding(r); 1387 1388 switch (id) { 1389 case SYS_ID_AA64ZFR0_EL1: 1390 if (!vcpu_has_sve(vcpu)) 1391 return REG_RAZ; 1392 break; 1393 } 1394 1395 return 0; 1396 } 1397 1398 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1399 const struct sys_reg_desc *r) 1400 { 1401 /* 1402 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1403 * EL. Promote to RAZ/WI in order to guarantee consistency between 1404 * systems. 1405 */ 1406 if (!kvm_supports_32bit_el0()) 1407 return REG_RAZ | REG_USER_WI; 1408 1409 return id_visibility(vcpu, r); 1410 } 1411 1412 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1413 const struct sys_reg_desc *r) 1414 { 1415 return REG_RAZ; 1416 } 1417 1418 /* cpufeature ID register access trap handlers */ 1419 1420 static bool access_id_reg(struct kvm_vcpu *vcpu, 1421 struct sys_reg_params *p, 1422 const struct sys_reg_desc *r) 1423 { 1424 if (p->is_write) 1425 return write_to_read_only(vcpu, p, r); 1426 1427 p->regval = read_id_reg(vcpu, r); 1428 if (vcpu_has_nv(vcpu)) 1429 access_nested_id_reg(vcpu, p, r); 1430 1431 return true; 1432 } 1433 1434 /* Visibility overrides for SVE-specific control registers */ 1435 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1436 const struct sys_reg_desc *rd) 1437 { 1438 if (vcpu_has_sve(vcpu)) 1439 return 0; 1440 1441 return REG_HIDDEN; 1442 } 1443 1444 static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1445 const struct sys_reg_desc *rd) 1446 { 1447 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1448 1449 if (!vcpu_has_sve(vcpu)) 1450 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1451 1452 /* 1453 * The default is to expose CSV2 == 1 if the HW isn't affected. 1454 * Although this is a per-CPU feature, we make it global because 1455 * asymmetric systems are just a nuisance. 1456 * 1457 * Userspace can override this as long as it doesn't promise 1458 * the impossible. 1459 */ 1460 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1461 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1462 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1463 } 1464 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1465 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1466 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1467 } 1468 1469 if (kvm_vgic_global_state.type == VGIC_V3) { 1470 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1471 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1472 } 1473 1474 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1475 1476 /* 1477 * MPAM is disabled by default as KVM also needs a set of PARTID to 1478 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 1479 * older kernels let the guest see the ID bit. 1480 */ 1481 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1482 1483 return val; 1484 } 1485 1486 static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1487 const struct sys_reg_desc *rd) 1488 { 1489 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1490 1491 /* Limit debug to ARMv8.0 */ 1492 val &= ~ID_AA64DFR0_EL1_DebugVer_MASK; 1493 val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DebugVer, IMP); 1494 1495 /* 1496 * Only initialize the PMU version if the vCPU was configured with one. 1497 */ 1498 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1499 if (kvm_vcpu_has_pmu(vcpu)) 1500 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1501 kvm_arm_pmu_get_pmuver_limit()); 1502 1503 /* Hide SPE from guests */ 1504 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1505 1506 return val; 1507 } 1508 1509 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1510 const struct sys_reg_desc *rd, 1511 u64 val) 1512 { 1513 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1514 1515 /* 1516 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1517 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1518 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1519 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1520 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1521 * 1522 * At minimum, we're on the hook to allow values that were given to 1523 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1524 * with a more sensible NI. The value of an ID register changing under 1525 * the nose of the guest is unfortunate, but is certainly no more 1526 * surprising than an ill-guided PMU driver poking at impdef system 1527 * registers that end in an UNDEF... 1528 */ 1529 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1530 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1531 1532 return set_id_reg(vcpu, rd, val); 1533 } 1534 1535 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1536 const struct sys_reg_desc *rd) 1537 { 1538 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1539 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1540 1541 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1542 if (kvm_vcpu_has_pmu(vcpu)) 1543 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1544 1545 return val; 1546 } 1547 1548 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1549 const struct sys_reg_desc *rd, 1550 u64 val) 1551 { 1552 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1553 1554 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1555 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1556 perfmon = 0; 1557 } 1558 1559 /* 1560 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1561 * it doesn't promise more than what the HW gives us on the 1562 * AArch64 side (as everything is emulated with that), and 1563 * that this is a PMUv3. 1564 */ 1565 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1566 return -EINVAL; 1567 1568 return set_id_reg(vcpu, rd, val); 1569 } 1570 1571 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1572 const struct sys_reg_desc *rd, u64 user_val) 1573 { 1574 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1575 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 1576 1577 /* 1578 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 1579 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 1580 * guests, but didn't add trap handling. KVM doesn't support MPAM and 1581 * always returns an UNDEF for these registers. The guest must see 0 1582 * for this field. 1583 * 1584 * But KVM must also accept values from user-space that were provided 1585 * by KVM. On CPUs that support MPAM, permit user-space to write 1586 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 1587 */ 1588 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1589 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1590 1591 return set_id_reg(vcpu, rd, user_val); 1592 } 1593 1594 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 1595 const struct sys_reg_desc *rd, u64 user_val) 1596 { 1597 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1598 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 1599 1600 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 1601 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1602 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 1603 1604 return set_id_reg(vcpu, rd, user_val); 1605 } 1606 1607 /* 1608 * cpufeature ID register user accessors 1609 * 1610 * For now, these registers are immutable for userspace, so no values 1611 * are stored, and for set_id_reg() we don't allow the effective value 1612 * to be changed. 1613 */ 1614 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1615 u64 *val) 1616 { 1617 /* 1618 * Avoid locking if the VM has already started, as the ID registers are 1619 * guaranteed to be invariant at that point. 1620 */ 1621 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1622 *val = read_id_reg(vcpu, rd); 1623 return 0; 1624 } 1625 1626 mutex_lock(&vcpu->kvm->arch.config_lock); 1627 *val = read_id_reg(vcpu, rd); 1628 mutex_unlock(&vcpu->kvm->arch.config_lock); 1629 1630 return 0; 1631 } 1632 1633 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1634 u64 val) 1635 { 1636 u32 id = reg_to_encoding(rd); 1637 int ret; 1638 1639 mutex_lock(&vcpu->kvm->arch.config_lock); 1640 1641 /* 1642 * Once the VM has started the ID registers are immutable. Reject any 1643 * write that does not match the final register value. 1644 */ 1645 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1646 if (val != read_id_reg(vcpu, rd)) 1647 ret = -EBUSY; 1648 else 1649 ret = 0; 1650 1651 mutex_unlock(&vcpu->kvm->arch.config_lock); 1652 return ret; 1653 } 1654 1655 ret = arm64_check_features(vcpu, rd, val); 1656 if (!ret) 1657 IDREG(vcpu->kvm, id) = val; 1658 1659 mutex_unlock(&vcpu->kvm->arch.config_lock); 1660 1661 /* 1662 * arm64_check_features() returns -E2BIG to indicate the register's 1663 * feature set is a superset of the maximally-allowed register value. 1664 * While it would be nice to precisely describe this to userspace, the 1665 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 1666 * writes return -EINVAL. 1667 */ 1668 if (ret == -E2BIG) 1669 ret = -EINVAL; 1670 return ret; 1671 } 1672 1673 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1674 u64 *val) 1675 { 1676 *val = 0; 1677 return 0; 1678 } 1679 1680 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1681 u64 val) 1682 { 1683 return 0; 1684 } 1685 1686 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1687 const struct sys_reg_desc *r) 1688 { 1689 if (p->is_write) 1690 return write_to_read_only(vcpu, p, r); 1691 1692 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1693 return true; 1694 } 1695 1696 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1697 const struct sys_reg_desc *r) 1698 { 1699 if (p->is_write) 1700 return write_to_read_only(vcpu, p, r); 1701 1702 p->regval = __vcpu_sys_reg(vcpu, r->reg); 1703 return true; 1704 } 1705 1706 /* 1707 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 1708 * by the physical CPU which the vcpu currently resides in. 1709 */ 1710 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1711 { 1712 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1713 u64 clidr; 1714 u8 loc; 1715 1716 if ((ctr_el0 & CTR_EL0_IDC)) { 1717 /* 1718 * Data cache clean to the PoU is not required so LoUU and LoUIS 1719 * will not be set and a unified cache, which will be marked as 1720 * LoC, will be added. 1721 * 1722 * If not DIC, let the unified cache L2 so that an instruction 1723 * cache can be added as L1 later. 1724 */ 1725 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 1726 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 1727 } else { 1728 /* 1729 * Data cache clean to the PoU is required so let L1 have a data 1730 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 1731 * it can be marked as LoC too. 1732 */ 1733 loc = 1; 1734 clidr = 1 << CLIDR_LOUU_SHIFT; 1735 clidr |= 1 << CLIDR_LOUIS_SHIFT; 1736 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 1737 } 1738 1739 /* 1740 * Instruction cache invalidation to the PoU is required so let L1 have 1741 * an instruction cache. If L1 already has a data cache, it will be 1742 * CACHE_TYPE_SEPARATE. 1743 */ 1744 if (!(ctr_el0 & CTR_EL0_DIC)) 1745 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 1746 1747 clidr |= loc << CLIDR_LOC_SHIFT; 1748 1749 /* 1750 * Add tag cache unified to data cache. Allocation tags and data are 1751 * unified in a cache line so that it looks valid even if there is only 1752 * one cache line. 1753 */ 1754 if (kvm_has_mte(vcpu->kvm)) 1755 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 1756 1757 __vcpu_sys_reg(vcpu, r->reg) = clidr; 1758 1759 return __vcpu_sys_reg(vcpu, r->reg); 1760 } 1761 1762 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1763 u64 val) 1764 { 1765 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1766 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 1767 1768 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 1769 return -EINVAL; 1770 1771 __vcpu_sys_reg(vcpu, rd->reg) = val; 1772 1773 return 0; 1774 } 1775 1776 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1777 const struct sys_reg_desc *r) 1778 { 1779 int reg = r->reg; 1780 1781 if (p->is_write) 1782 vcpu_write_sys_reg(vcpu, p->regval, reg); 1783 else 1784 p->regval = vcpu_read_sys_reg(vcpu, reg); 1785 return true; 1786 } 1787 1788 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1789 const struct sys_reg_desc *r) 1790 { 1791 u32 csselr; 1792 1793 if (p->is_write) 1794 return write_to_read_only(vcpu, p, r); 1795 1796 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1797 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 1798 if (csselr < CSSELR_MAX) 1799 p->regval = get_ccsidr(vcpu, csselr); 1800 1801 return true; 1802 } 1803 1804 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 1805 const struct sys_reg_desc *rd) 1806 { 1807 if (kvm_has_mte(vcpu->kvm)) 1808 return 0; 1809 1810 return REG_HIDDEN; 1811 } 1812 1813 #define MTE_REG(name) { \ 1814 SYS_DESC(SYS_##name), \ 1815 .access = undef_access, \ 1816 .reset = reset_unknown, \ 1817 .reg = name, \ 1818 .visibility = mte_visibility, \ 1819 } 1820 1821 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 1822 const struct sys_reg_desc *rd) 1823 { 1824 if (vcpu_has_nv(vcpu)) 1825 return 0; 1826 1827 return REG_HIDDEN; 1828 } 1829 1830 #define EL2_REG(name, acc, rst, v) { \ 1831 SYS_DESC(SYS_##name), \ 1832 .access = acc, \ 1833 .reset = rst, \ 1834 .reg = name, \ 1835 .visibility = el2_visibility, \ 1836 .val = v, \ 1837 } 1838 1839 /* 1840 * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when 1841 * HCR_EL2.E2H==1, and only in the sysreg table for convenience of 1842 * handling traps. Given that, they are always hidden from userspace. 1843 */ 1844 static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, 1845 const struct sys_reg_desc *rd) 1846 { 1847 return REG_HIDDEN_USER; 1848 } 1849 1850 #define EL12_REG(name, acc, rst, v) { \ 1851 SYS_DESC(SYS_##name##_EL12), \ 1852 .access = acc, \ 1853 .reset = rst, \ 1854 .reg = name##_EL1, \ 1855 .val = v, \ 1856 .visibility = elx2_visibility, \ 1857 } 1858 1859 /* 1860 * Since reset() callback and field val are not used for idregs, they will be 1861 * used for specific purposes for idregs. 1862 * The reset() would return KVM sanitised register value. The value would be the 1863 * same as the host kernel sanitised value if there is no KVM sanitisation. 1864 * The val would be used as a mask indicating writable fields for the idreg. 1865 * Only bits with 1 are writable from userspace. This mask might not be 1866 * necessary in the future whenever all ID registers are enabled as writable 1867 * from userspace. 1868 */ 1869 1870 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1871 #define ID_SANITISED(name) { \ 1872 SYS_DESC(SYS_##name), \ 1873 .access = access_id_reg, \ 1874 .get_user = get_id_reg, \ 1875 .set_user = set_id_reg, \ 1876 .visibility = id_visibility, \ 1877 .reset = kvm_read_sanitised_id_reg, \ 1878 .val = 0, \ 1879 } 1880 1881 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1882 #define AA32_ID_SANITISED(name) { \ 1883 SYS_DESC(SYS_##name), \ 1884 .access = access_id_reg, \ 1885 .get_user = get_id_reg, \ 1886 .set_user = set_id_reg, \ 1887 .visibility = aa32_id_visibility, \ 1888 .reset = kvm_read_sanitised_id_reg, \ 1889 .val = 0, \ 1890 } 1891 1892 /* 1893 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1894 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1895 * (1 <= crm < 8, 0 <= Op2 < 8). 1896 */ 1897 #define ID_UNALLOCATED(crm, op2) { \ 1898 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1899 .access = access_id_reg, \ 1900 .get_user = get_id_reg, \ 1901 .set_user = set_id_reg, \ 1902 .visibility = raz_visibility, \ 1903 .reset = kvm_read_sanitised_id_reg, \ 1904 .val = 0, \ 1905 } 1906 1907 /* 1908 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1909 * For now, these are exposed just like unallocated ID regs: they appear 1910 * RAZ for the guest. 1911 */ 1912 #define ID_HIDDEN(name) { \ 1913 SYS_DESC(SYS_##name), \ 1914 .access = access_id_reg, \ 1915 .get_user = get_id_reg, \ 1916 .set_user = set_id_reg, \ 1917 .visibility = raz_visibility, \ 1918 .reset = kvm_read_sanitised_id_reg, \ 1919 .val = 0, \ 1920 } 1921 1922 static bool access_sp_el1(struct kvm_vcpu *vcpu, 1923 struct sys_reg_params *p, 1924 const struct sys_reg_desc *r) 1925 { 1926 if (p->is_write) 1927 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 1928 else 1929 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 1930 1931 return true; 1932 } 1933 1934 static bool access_elr(struct kvm_vcpu *vcpu, 1935 struct sys_reg_params *p, 1936 const struct sys_reg_desc *r) 1937 { 1938 if (p->is_write) 1939 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 1940 else 1941 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 1942 1943 return true; 1944 } 1945 1946 static bool access_spsr(struct kvm_vcpu *vcpu, 1947 struct sys_reg_params *p, 1948 const struct sys_reg_desc *r) 1949 { 1950 if (p->is_write) 1951 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 1952 else 1953 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 1954 1955 return true; 1956 } 1957 1958 /* 1959 * Architected system registers. 1960 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1961 * 1962 * Debug handling: We do trap most, if not all debug related system 1963 * registers. The implementation is good enough to ensure that a guest 1964 * can use these with minimal performance degradation. The drawback is 1965 * that we don't implement any of the external debug architecture. 1966 * This should be revisited if we ever encounter a more demanding 1967 * guest... 1968 */ 1969 static const struct sys_reg_desc sys_reg_descs[] = { 1970 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1971 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 1972 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 1973 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1974 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 1975 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 1976 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1977 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 1978 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 1979 1980 DBG_BCR_BVR_WCR_WVR_EL1(0), 1981 DBG_BCR_BVR_WCR_WVR_EL1(1), 1982 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1983 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1984 DBG_BCR_BVR_WCR_WVR_EL1(2), 1985 DBG_BCR_BVR_WCR_WVR_EL1(3), 1986 DBG_BCR_BVR_WCR_WVR_EL1(4), 1987 DBG_BCR_BVR_WCR_WVR_EL1(5), 1988 DBG_BCR_BVR_WCR_WVR_EL1(6), 1989 DBG_BCR_BVR_WCR_WVR_EL1(7), 1990 DBG_BCR_BVR_WCR_WVR_EL1(8), 1991 DBG_BCR_BVR_WCR_WVR_EL1(9), 1992 DBG_BCR_BVR_WCR_WVR_EL1(10), 1993 DBG_BCR_BVR_WCR_WVR_EL1(11), 1994 DBG_BCR_BVR_WCR_WVR_EL1(12), 1995 DBG_BCR_BVR_WCR_WVR_EL1(13), 1996 DBG_BCR_BVR_WCR_WVR_EL1(14), 1997 DBG_BCR_BVR_WCR_WVR_EL1(15), 1998 1999 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2000 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2001 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2002 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2003 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2004 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2005 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2006 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2007 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2008 2009 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2010 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2011 // DBGDTR[TR]X_EL0 share the same encoding 2012 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2013 2014 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 2015 2016 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2017 2018 /* 2019 * ID regs: all ID_SANITISED() entries here must have corresponding 2020 * entries in arm64_ftr_regs[]. 2021 */ 2022 2023 /* AArch64 mappings of the AArch32 ID registers */ 2024 /* CRm=1 */ 2025 AA32_ID_SANITISED(ID_PFR0_EL1), 2026 AA32_ID_SANITISED(ID_PFR1_EL1), 2027 { SYS_DESC(SYS_ID_DFR0_EL1), 2028 .access = access_id_reg, 2029 .get_user = get_id_reg, 2030 .set_user = set_id_dfr0_el1, 2031 .visibility = aa32_id_visibility, 2032 .reset = read_sanitised_id_dfr0_el1, 2033 .val = ID_DFR0_EL1_PerfMon_MASK, }, 2034 ID_HIDDEN(ID_AFR0_EL1), 2035 AA32_ID_SANITISED(ID_MMFR0_EL1), 2036 AA32_ID_SANITISED(ID_MMFR1_EL1), 2037 AA32_ID_SANITISED(ID_MMFR2_EL1), 2038 AA32_ID_SANITISED(ID_MMFR3_EL1), 2039 2040 /* CRm=2 */ 2041 AA32_ID_SANITISED(ID_ISAR0_EL1), 2042 AA32_ID_SANITISED(ID_ISAR1_EL1), 2043 AA32_ID_SANITISED(ID_ISAR2_EL1), 2044 AA32_ID_SANITISED(ID_ISAR3_EL1), 2045 AA32_ID_SANITISED(ID_ISAR4_EL1), 2046 AA32_ID_SANITISED(ID_ISAR5_EL1), 2047 AA32_ID_SANITISED(ID_MMFR4_EL1), 2048 AA32_ID_SANITISED(ID_ISAR6_EL1), 2049 2050 /* CRm=3 */ 2051 AA32_ID_SANITISED(MVFR0_EL1), 2052 AA32_ID_SANITISED(MVFR1_EL1), 2053 AA32_ID_SANITISED(MVFR2_EL1), 2054 ID_UNALLOCATED(3,3), 2055 AA32_ID_SANITISED(ID_PFR2_EL1), 2056 ID_HIDDEN(ID_DFR1_EL1), 2057 AA32_ID_SANITISED(ID_MMFR5_EL1), 2058 ID_UNALLOCATED(3,7), 2059 2060 /* AArch64 ID registers */ 2061 /* CRm=4 */ 2062 { SYS_DESC(SYS_ID_AA64PFR0_EL1), 2063 .access = access_id_reg, 2064 .get_user = get_id_reg, 2065 .set_user = set_id_aa64pfr0_el1, 2066 .reset = read_sanitised_id_aa64pfr0_el1, 2067 .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, }, 2068 { SYS_DESC(SYS_ID_AA64PFR1_EL1), 2069 .access = access_id_reg, 2070 .get_user = get_id_reg, 2071 .set_user = set_id_aa64pfr1_el1, 2072 .reset = kvm_read_sanitised_id_reg, }, 2073 ID_UNALLOCATED(4,2), 2074 ID_UNALLOCATED(4,3), 2075 ID_SANITISED(ID_AA64ZFR0_EL1), 2076 ID_HIDDEN(ID_AA64SMFR0_EL1), 2077 ID_UNALLOCATED(4,6), 2078 ID_UNALLOCATED(4,7), 2079 2080 /* CRm=5 */ 2081 { SYS_DESC(SYS_ID_AA64DFR0_EL1), 2082 .access = access_id_reg, 2083 .get_user = get_id_reg, 2084 .set_user = set_id_aa64dfr0_el1, 2085 .reset = read_sanitised_id_aa64dfr0_el1, 2086 .val = ID_AA64DFR0_EL1_PMUVer_MASK, }, 2087 ID_SANITISED(ID_AA64DFR1_EL1), 2088 ID_UNALLOCATED(5,2), 2089 ID_UNALLOCATED(5,3), 2090 ID_HIDDEN(ID_AA64AFR0_EL1), 2091 ID_HIDDEN(ID_AA64AFR1_EL1), 2092 ID_UNALLOCATED(5,6), 2093 ID_UNALLOCATED(5,7), 2094 2095 /* CRm=6 */ 2096 ID_SANITISED(ID_AA64ISAR0_EL1), 2097 ID_SANITISED(ID_AA64ISAR1_EL1), 2098 ID_SANITISED(ID_AA64ISAR2_EL1), 2099 ID_UNALLOCATED(6,3), 2100 ID_UNALLOCATED(6,4), 2101 ID_UNALLOCATED(6,5), 2102 ID_UNALLOCATED(6,6), 2103 ID_UNALLOCATED(6,7), 2104 2105 /* CRm=7 */ 2106 ID_SANITISED(ID_AA64MMFR0_EL1), 2107 ID_SANITISED(ID_AA64MMFR1_EL1), 2108 ID_SANITISED(ID_AA64MMFR2_EL1), 2109 ID_SANITISED(ID_AA64MMFR3_EL1), 2110 ID_UNALLOCATED(7,4), 2111 ID_UNALLOCATED(7,5), 2112 ID_UNALLOCATED(7,6), 2113 ID_UNALLOCATED(7,7), 2114 2115 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2116 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2117 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2118 2119 MTE_REG(RGSR_EL1), 2120 MTE_REG(GCR_EL1), 2121 2122 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2123 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2124 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2125 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2126 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2127 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2128 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2129 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 }, 2130 2131 PTRAUTH_KEY(APIA), 2132 PTRAUTH_KEY(APIB), 2133 PTRAUTH_KEY(APDA), 2134 PTRAUTH_KEY(APDB), 2135 PTRAUTH_KEY(APGA), 2136 2137 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2138 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2139 2140 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2141 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2142 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2143 2144 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2145 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2146 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2147 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2148 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2149 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2150 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2151 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2152 2153 MTE_REG(TFSR_EL1), 2154 MTE_REG(TFSRE0_EL1), 2155 2156 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2157 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2158 2159 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2160 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2161 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2162 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2163 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2164 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2165 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2166 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2167 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2168 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2169 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2170 /* PMBIDR_EL1 is not trapped */ 2171 2172 { PMU_SYS_REG(PMINTENSET_EL1), 2173 .access = access_pminten, .reg = PMINTENSET_EL1 }, 2174 { PMU_SYS_REG(PMINTENCLR_EL1), 2175 .access = access_pminten, .reg = PMINTENSET_EL1 }, 2176 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2177 2178 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2179 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 }, 2180 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 }, 2181 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2182 2183 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2184 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2185 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2186 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2187 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2188 2189 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2190 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2191 2192 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 2193 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 2194 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 2195 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 2196 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 2197 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2198 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2199 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2200 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 2201 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 2202 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 2203 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2204 2205 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2206 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2207 2208 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2209 2210 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2211 2212 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2213 2214 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2215 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2216 .set_user = set_clidr }, 2217 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2218 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2219 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2220 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 2221 { SYS_DESC(SYS_SVCR), undef_access }, 2222 2223 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, 2224 .reset = reset_pmcr, .reg = PMCR_EL0 }, 2225 { PMU_SYS_REG(PMCNTENSET_EL0), 2226 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 2227 { PMU_SYS_REG(PMCNTENCLR_EL0), 2228 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 2229 { PMU_SYS_REG(PMOVSCLR_EL0), 2230 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 2231 /* 2232 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2233 * previously (and pointlessly) advertised in the past... 2234 */ 2235 { PMU_SYS_REG(PMSWINC_EL0), 2236 .get_user = get_raz_reg, .set_user = set_wi_reg, 2237 .access = access_pmswinc, .reset = NULL }, 2238 { PMU_SYS_REG(PMSELR_EL0), 2239 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2240 { PMU_SYS_REG(PMCEID0_EL0), 2241 .access = access_pmceid, .reset = NULL }, 2242 { PMU_SYS_REG(PMCEID1_EL0), 2243 .access = access_pmceid, .reset = NULL }, 2244 { PMU_SYS_REG(PMCCNTR_EL0), 2245 .access = access_pmu_evcntr, .reset = reset_unknown, 2246 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2247 { PMU_SYS_REG(PMXEVTYPER_EL0), 2248 .access = access_pmu_evtyper, .reset = NULL }, 2249 { PMU_SYS_REG(PMXEVCNTR_EL0), 2250 .access = access_pmu_evcntr, .reset = NULL }, 2251 /* 2252 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2253 * in 32bit mode. Here we choose to reset it as zero for consistency. 2254 */ 2255 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2256 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2257 { PMU_SYS_REG(PMOVSSET_EL0), 2258 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 2259 2260 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2261 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2262 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2263 2264 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2265 2266 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2267 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2268 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2269 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2270 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2271 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2272 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2273 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2274 AMU_AMEVCNTR0_EL0(0), 2275 AMU_AMEVCNTR0_EL0(1), 2276 AMU_AMEVCNTR0_EL0(2), 2277 AMU_AMEVCNTR0_EL0(3), 2278 AMU_AMEVCNTR0_EL0(4), 2279 AMU_AMEVCNTR0_EL0(5), 2280 AMU_AMEVCNTR0_EL0(6), 2281 AMU_AMEVCNTR0_EL0(7), 2282 AMU_AMEVCNTR0_EL0(8), 2283 AMU_AMEVCNTR0_EL0(9), 2284 AMU_AMEVCNTR0_EL0(10), 2285 AMU_AMEVCNTR0_EL0(11), 2286 AMU_AMEVCNTR0_EL0(12), 2287 AMU_AMEVCNTR0_EL0(13), 2288 AMU_AMEVCNTR0_EL0(14), 2289 AMU_AMEVCNTR0_EL0(15), 2290 AMU_AMEVTYPER0_EL0(0), 2291 AMU_AMEVTYPER0_EL0(1), 2292 AMU_AMEVTYPER0_EL0(2), 2293 AMU_AMEVTYPER0_EL0(3), 2294 AMU_AMEVTYPER0_EL0(4), 2295 AMU_AMEVTYPER0_EL0(5), 2296 AMU_AMEVTYPER0_EL0(6), 2297 AMU_AMEVTYPER0_EL0(7), 2298 AMU_AMEVTYPER0_EL0(8), 2299 AMU_AMEVTYPER0_EL0(9), 2300 AMU_AMEVTYPER0_EL0(10), 2301 AMU_AMEVTYPER0_EL0(11), 2302 AMU_AMEVTYPER0_EL0(12), 2303 AMU_AMEVTYPER0_EL0(13), 2304 AMU_AMEVTYPER0_EL0(14), 2305 AMU_AMEVTYPER0_EL0(15), 2306 AMU_AMEVCNTR1_EL0(0), 2307 AMU_AMEVCNTR1_EL0(1), 2308 AMU_AMEVCNTR1_EL0(2), 2309 AMU_AMEVCNTR1_EL0(3), 2310 AMU_AMEVCNTR1_EL0(4), 2311 AMU_AMEVCNTR1_EL0(5), 2312 AMU_AMEVCNTR1_EL0(6), 2313 AMU_AMEVCNTR1_EL0(7), 2314 AMU_AMEVCNTR1_EL0(8), 2315 AMU_AMEVCNTR1_EL0(9), 2316 AMU_AMEVCNTR1_EL0(10), 2317 AMU_AMEVCNTR1_EL0(11), 2318 AMU_AMEVCNTR1_EL0(12), 2319 AMU_AMEVCNTR1_EL0(13), 2320 AMU_AMEVCNTR1_EL0(14), 2321 AMU_AMEVCNTR1_EL0(15), 2322 AMU_AMEVTYPER1_EL0(0), 2323 AMU_AMEVTYPER1_EL0(1), 2324 AMU_AMEVTYPER1_EL0(2), 2325 AMU_AMEVTYPER1_EL0(3), 2326 AMU_AMEVTYPER1_EL0(4), 2327 AMU_AMEVTYPER1_EL0(5), 2328 AMU_AMEVTYPER1_EL0(6), 2329 AMU_AMEVTYPER1_EL0(7), 2330 AMU_AMEVTYPER1_EL0(8), 2331 AMU_AMEVTYPER1_EL0(9), 2332 AMU_AMEVTYPER1_EL0(10), 2333 AMU_AMEVTYPER1_EL0(11), 2334 AMU_AMEVTYPER1_EL0(12), 2335 AMU_AMEVTYPER1_EL0(13), 2336 AMU_AMEVTYPER1_EL0(14), 2337 AMU_AMEVTYPER1_EL0(15), 2338 2339 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 2340 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 2341 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2342 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2343 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2344 2345 /* PMEVCNTRn_EL0 */ 2346 PMU_PMEVCNTR_EL0(0), 2347 PMU_PMEVCNTR_EL0(1), 2348 PMU_PMEVCNTR_EL0(2), 2349 PMU_PMEVCNTR_EL0(3), 2350 PMU_PMEVCNTR_EL0(4), 2351 PMU_PMEVCNTR_EL0(5), 2352 PMU_PMEVCNTR_EL0(6), 2353 PMU_PMEVCNTR_EL0(7), 2354 PMU_PMEVCNTR_EL0(8), 2355 PMU_PMEVCNTR_EL0(9), 2356 PMU_PMEVCNTR_EL0(10), 2357 PMU_PMEVCNTR_EL0(11), 2358 PMU_PMEVCNTR_EL0(12), 2359 PMU_PMEVCNTR_EL0(13), 2360 PMU_PMEVCNTR_EL0(14), 2361 PMU_PMEVCNTR_EL0(15), 2362 PMU_PMEVCNTR_EL0(16), 2363 PMU_PMEVCNTR_EL0(17), 2364 PMU_PMEVCNTR_EL0(18), 2365 PMU_PMEVCNTR_EL0(19), 2366 PMU_PMEVCNTR_EL0(20), 2367 PMU_PMEVCNTR_EL0(21), 2368 PMU_PMEVCNTR_EL0(22), 2369 PMU_PMEVCNTR_EL0(23), 2370 PMU_PMEVCNTR_EL0(24), 2371 PMU_PMEVCNTR_EL0(25), 2372 PMU_PMEVCNTR_EL0(26), 2373 PMU_PMEVCNTR_EL0(27), 2374 PMU_PMEVCNTR_EL0(28), 2375 PMU_PMEVCNTR_EL0(29), 2376 PMU_PMEVCNTR_EL0(30), 2377 /* PMEVTYPERn_EL0 */ 2378 PMU_PMEVTYPER_EL0(0), 2379 PMU_PMEVTYPER_EL0(1), 2380 PMU_PMEVTYPER_EL0(2), 2381 PMU_PMEVTYPER_EL0(3), 2382 PMU_PMEVTYPER_EL0(4), 2383 PMU_PMEVTYPER_EL0(5), 2384 PMU_PMEVTYPER_EL0(6), 2385 PMU_PMEVTYPER_EL0(7), 2386 PMU_PMEVTYPER_EL0(8), 2387 PMU_PMEVTYPER_EL0(9), 2388 PMU_PMEVTYPER_EL0(10), 2389 PMU_PMEVTYPER_EL0(11), 2390 PMU_PMEVTYPER_EL0(12), 2391 PMU_PMEVTYPER_EL0(13), 2392 PMU_PMEVTYPER_EL0(14), 2393 PMU_PMEVTYPER_EL0(15), 2394 PMU_PMEVTYPER_EL0(16), 2395 PMU_PMEVTYPER_EL0(17), 2396 PMU_PMEVTYPER_EL0(18), 2397 PMU_PMEVTYPER_EL0(19), 2398 PMU_PMEVTYPER_EL0(20), 2399 PMU_PMEVTYPER_EL0(21), 2400 PMU_PMEVTYPER_EL0(22), 2401 PMU_PMEVTYPER_EL0(23), 2402 PMU_PMEVTYPER_EL0(24), 2403 PMU_PMEVTYPER_EL0(25), 2404 PMU_PMEVTYPER_EL0(26), 2405 PMU_PMEVTYPER_EL0(27), 2406 PMU_PMEVTYPER_EL0(28), 2407 PMU_PMEVTYPER_EL0(29), 2408 PMU_PMEVTYPER_EL0(30), 2409 /* 2410 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2411 * in 32bit mode. Here we choose to reset it as zero for consistency. 2412 */ 2413 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 2414 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2415 2416 EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0), 2417 EL2_REG(VMPIDR_EL2, access_rw, reset_unknown, 0), 2418 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 2419 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 2420 EL2_REG(HCR_EL2, access_rw, reset_val, 0), 2421 EL2_REG(MDCR_EL2, access_rw, reset_val, 0), 2422 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 2423 EL2_REG(HSTR_EL2, access_rw, reset_val, 0), 2424 EL2_REG(HFGRTR_EL2, access_rw, reset_val, 0), 2425 EL2_REG(HFGWTR_EL2, access_rw, reset_val, 0), 2426 EL2_REG(HFGITR_EL2, access_rw, reset_val, 0), 2427 EL2_REG(HACR_EL2, access_rw, reset_val, 0), 2428 2429 EL2_REG(HCRX_EL2, access_rw, reset_val, 0), 2430 2431 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 2432 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 2433 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 2434 EL2_REG(VTTBR_EL2, access_rw, reset_val, 0), 2435 EL2_REG(VTCR_EL2, access_rw, reset_val, 0), 2436 2437 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 2438 EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0), 2439 EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0), 2440 EL2_REG(SPSR_EL2, access_rw, reset_val, 0), 2441 EL2_REG(ELR_EL2, access_rw, reset_val, 0), 2442 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 2443 2444 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 2445 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 2446 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 2447 EL2_REG(ESR_EL2, access_rw, reset_val, 0), 2448 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 2449 2450 EL2_REG(FAR_EL2, access_rw, reset_val, 0), 2451 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 2452 2453 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 2454 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 2455 2456 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 2457 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 2458 { SYS_DESC(SYS_RMR_EL2), trap_undef }, 2459 2460 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 2461 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 2462 2463 EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0), 2464 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 2465 2466 EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078), 2467 EL12_REG(CPACR, access_rw, reset_val, 0), 2468 EL12_REG(TTBR0, access_vm_reg, reset_unknown, 0), 2469 EL12_REG(TTBR1, access_vm_reg, reset_unknown, 0), 2470 EL12_REG(TCR, access_vm_reg, reset_val, 0), 2471 { SYS_DESC(SYS_SPSR_EL12), access_spsr}, 2472 { SYS_DESC(SYS_ELR_EL12), access_elr}, 2473 EL12_REG(AFSR0, access_vm_reg, reset_unknown, 0), 2474 EL12_REG(AFSR1, access_vm_reg, reset_unknown, 0), 2475 EL12_REG(ESR, access_vm_reg, reset_unknown, 0), 2476 EL12_REG(FAR, access_vm_reg, reset_unknown, 0), 2477 EL12_REG(MAIR, access_vm_reg, reset_unknown, 0), 2478 EL12_REG(AMAIR, access_vm_reg, reset_amair_el1, 0), 2479 EL12_REG(VBAR, access_rw, reset_val, 0), 2480 EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0), 2481 EL12_REG(CNTKCTL, access_rw, reset_val, 0), 2482 2483 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 2484 }; 2485 2486 static const struct sys_reg_desc *first_idreg; 2487 2488 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 2489 struct sys_reg_params *p, 2490 const struct sys_reg_desc *r) 2491 { 2492 if (p->is_write) { 2493 return ignore_write(vcpu, p); 2494 } else { 2495 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 2496 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2497 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); 2498 2499 p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | 2500 (((dfr >> ID_AA64DFR0_EL1_BRPs_SHIFT) & 0xf) << 24) | 2501 (((dfr >> ID_AA64DFR0_EL1_CTX_CMPs_SHIFT) & 0xf) << 20) 2502 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); 2503 return true; 2504 } 2505 } 2506 2507 /* 2508 * AArch32 debug register mappings 2509 * 2510 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 2511 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 2512 * 2513 * None of the other registers share their location, so treat them as 2514 * if they were 64bit. 2515 */ 2516 #define DBG_BCR_BVR_WCR_WVR(n) \ 2517 /* DBGBVRn */ \ 2518 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 2519 /* DBGBCRn */ \ 2520 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 2521 /* DBGWVRn */ \ 2522 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 2523 /* DBGWCRn */ \ 2524 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 2525 2526 #define DBGBXVR(n) \ 2527 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 2528 2529 /* 2530 * Trapped cp14 registers. We generally ignore most of the external 2531 * debug, on the principle that they don't really make sense to a 2532 * guest. Revisit this one day, would this principle change. 2533 */ 2534 static const struct sys_reg_desc cp14_regs[] = { 2535 /* DBGDIDR */ 2536 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 2537 /* DBGDTRRXext */ 2538 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 2539 2540 DBG_BCR_BVR_WCR_WVR(0), 2541 /* DBGDSCRint */ 2542 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 2543 DBG_BCR_BVR_WCR_WVR(1), 2544 /* DBGDCCINT */ 2545 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 2546 /* DBGDSCRext */ 2547 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 2548 DBG_BCR_BVR_WCR_WVR(2), 2549 /* DBGDTR[RT]Xint */ 2550 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 2551 /* DBGDTR[RT]Xext */ 2552 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 2553 DBG_BCR_BVR_WCR_WVR(3), 2554 DBG_BCR_BVR_WCR_WVR(4), 2555 DBG_BCR_BVR_WCR_WVR(5), 2556 /* DBGWFAR */ 2557 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 2558 /* DBGOSECCR */ 2559 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 2560 DBG_BCR_BVR_WCR_WVR(6), 2561 /* DBGVCR */ 2562 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 2563 DBG_BCR_BVR_WCR_WVR(7), 2564 DBG_BCR_BVR_WCR_WVR(8), 2565 DBG_BCR_BVR_WCR_WVR(9), 2566 DBG_BCR_BVR_WCR_WVR(10), 2567 DBG_BCR_BVR_WCR_WVR(11), 2568 DBG_BCR_BVR_WCR_WVR(12), 2569 DBG_BCR_BVR_WCR_WVR(13), 2570 DBG_BCR_BVR_WCR_WVR(14), 2571 DBG_BCR_BVR_WCR_WVR(15), 2572 2573 /* DBGDRAR (32bit) */ 2574 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 2575 2576 DBGBXVR(0), 2577 /* DBGOSLAR */ 2578 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 2579 DBGBXVR(1), 2580 /* DBGOSLSR */ 2581 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 2582 DBGBXVR(2), 2583 DBGBXVR(3), 2584 /* DBGOSDLR */ 2585 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 2586 DBGBXVR(4), 2587 /* DBGPRCR */ 2588 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 2589 DBGBXVR(5), 2590 DBGBXVR(6), 2591 DBGBXVR(7), 2592 DBGBXVR(8), 2593 DBGBXVR(9), 2594 DBGBXVR(10), 2595 DBGBXVR(11), 2596 DBGBXVR(12), 2597 DBGBXVR(13), 2598 DBGBXVR(14), 2599 DBGBXVR(15), 2600 2601 /* DBGDSAR (32bit) */ 2602 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 2603 2604 /* DBGDEVID2 */ 2605 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 2606 /* DBGDEVID1 */ 2607 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 2608 /* DBGDEVID */ 2609 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 2610 /* DBGCLAIMSET */ 2611 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 2612 /* DBGCLAIMCLR */ 2613 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 2614 /* DBGAUTHSTATUS */ 2615 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 2616 }; 2617 2618 /* Trapped cp14 64bit registers */ 2619 static const struct sys_reg_desc cp14_64_regs[] = { 2620 /* DBGDRAR (64bit) */ 2621 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 2622 2623 /* DBGDSAR (64bit) */ 2624 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 2625 }; 2626 2627 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 2628 AA32(_map), \ 2629 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 2630 .visibility = pmu_visibility 2631 2632 /* Macro to expand the PMEVCNTRn register */ 2633 #define PMU_PMEVCNTR(n) \ 2634 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 2635 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 2636 .access = access_pmu_evcntr } 2637 2638 /* Macro to expand the PMEVTYPERn register */ 2639 #define PMU_PMEVTYPER(n) \ 2640 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 2641 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 2642 .access = access_pmu_evtyper } 2643 /* 2644 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 2645 * depending on the way they are accessed (as a 32bit or a 64bit 2646 * register). 2647 */ 2648 static const struct sys_reg_desc cp15_regs[] = { 2649 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 2650 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 2651 /* ACTLR */ 2652 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 2653 /* ACTLR2 */ 2654 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 2655 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2656 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 2657 /* TTBCR */ 2658 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 2659 /* TTBCR2 */ 2660 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 2661 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 2662 /* DFSR */ 2663 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 2664 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 2665 /* ADFSR */ 2666 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 2667 /* AIFSR */ 2668 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 2669 /* DFAR */ 2670 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 2671 /* IFAR */ 2672 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 2673 2674 /* 2675 * DC{C,I,CI}SW operations: 2676 */ 2677 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 2678 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 2679 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 2680 2681 /* PMU */ 2682 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 2683 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 2684 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 2685 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 2686 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 2687 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 2688 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 2689 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 2690 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 2691 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 2692 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 2693 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 2694 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 2695 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 2696 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 2697 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 2698 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 2699 /* PMMIR */ 2700 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 2701 2702 /* PRRR/MAIR0 */ 2703 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 2704 /* NMRR/MAIR1 */ 2705 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 2706 /* AMAIR0 */ 2707 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 2708 /* AMAIR1 */ 2709 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 2710 2711 /* ICC_SRE */ 2712 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 2713 2714 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 2715 2716 /* Arch Tmers */ 2717 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 2718 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 2719 2720 /* PMEVCNTRn */ 2721 PMU_PMEVCNTR(0), 2722 PMU_PMEVCNTR(1), 2723 PMU_PMEVCNTR(2), 2724 PMU_PMEVCNTR(3), 2725 PMU_PMEVCNTR(4), 2726 PMU_PMEVCNTR(5), 2727 PMU_PMEVCNTR(6), 2728 PMU_PMEVCNTR(7), 2729 PMU_PMEVCNTR(8), 2730 PMU_PMEVCNTR(9), 2731 PMU_PMEVCNTR(10), 2732 PMU_PMEVCNTR(11), 2733 PMU_PMEVCNTR(12), 2734 PMU_PMEVCNTR(13), 2735 PMU_PMEVCNTR(14), 2736 PMU_PMEVCNTR(15), 2737 PMU_PMEVCNTR(16), 2738 PMU_PMEVCNTR(17), 2739 PMU_PMEVCNTR(18), 2740 PMU_PMEVCNTR(19), 2741 PMU_PMEVCNTR(20), 2742 PMU_PMEVCNTR(21), 2743 PMU_PMEVCNTR(22), 2744 PMU_PMEVCNTR(23), 2745 PMU_PMEVCNTR(24), 2746 PMU_PMEVCNTR(25), 2747 PMU_PMEVCNTR(26), 2748 PMU_PMEVCNTR(27), 2749 PMU_PMEVCNTR(28), 2750 PMU_PMEVCNTR(29), 2751 PMU_PMEVCNTR(30), 2752 /* PMEVTYPERn */ 2753 PMU_PMEVTYPER(0), 2754 PMU_PMEVTYPER(1), 2755 PMU_PMEVTYPER(2), 2756 PMU_PMEVTYPER(3), 2757 PMU_PMEVTYPER(4), 2758 PMU_PMEVTYPER(5), 2759 PMU_PMEVTYPER(6), 2760 PMU_PMEVTYPER(7), 2761 PMU_PMEVTYPER(8), 2762 PMU_PMEVTYPER(9), 2763 PMU_PMEVTYPER(10), 2764 PMU_PMEVTYPER(11), 2765 PMU_PMEVTYPER(12), 2766 PMU_PMEVTYPER(13), 2767 PMU_PMEVTYPER(14), 2768 PMU_PMEVTYPER(15), 2769 PMU_PMEVTYPER(16), 2770 PMU_PMEVTYPER(17), 2771 PMU_PMEVTYPER(18), 2772 PMU_PMEVTYPER(19), 2773 PMU_PMEVTYPER(20), 2774 PMU_PMEVTYPER(21), 2775 PMU_PMEVTYPER(22), 2776 PMU_PMEVTYPER(23), 2777 PMU_PMEVTYPER(24), 2778 PMU_PMEVTYPER(25), 2779 PMU_PMEVTYPER(26), 2780 PMU_PMEVTYPER(27), 2781 PMU_PMEVTYPER(28), 2782 PMU_PMEVTYPER(29), 2783 PMU_PMEVTYPER(30), 2784 /* PMCCFILTR */ 2785 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 2786 2787 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2788 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2789 2790 /* CCSIDR2 */ 2791 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 2792 2793 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 2794 }; 2795 2796 static const struct sys_reg_desc cp15_64_regs[] = { 2797 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2798 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 2799 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2800 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 2801 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 2802 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2803 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2804 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2805 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 2806 }; 2807 2808 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2809 bool is_32) 2810 { 2811 unsigned int i; 2812 2813 for (i = 0; i < n; i++) { 2814 if (!is_32 && table[i].reg && !table[i].reset) { 2815 kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i); 2816 return false; 2817 } 2818 2819 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2820 kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1); 2821 return false; 2822 } 2823 } 2824 2825 return true; 2826 } 2827 2828 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2829 { 2830 kvm_inject_undefined(vcpu); 2831 return 1; 2832 } 2833 2834 static void perform_access(struct kvm_vcpu *vcpu, 2835 struct sys_reg_params *params, 2836 const struct sys_reg_desc *r) 2837 { 2838 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2839 2840 /* Check for regs disabled by runtime config */ 2841 if (sysreg_hidden(vcpu, r)) { 2842 kvm_inject_undefined(vcpu); 2843 return; 2844 } 2845 2846 /* 2847 * Not having an accessor means that we have configured a trap 2848 * that we don't know how to handle. This certainly qualifies 2849 * as a gross bug that should be fixed right away. 2850 */ 2851 BUG_ON(!r->access); 2852 2853 /* Skip instruction if instructed so */ 2854 if (likely(r->access(vcpu, params, r))) 2855 kvm_incr_pc(vcpu); 2856 } 2857 2858 /* 2859 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2860 * call the corresponding trap handler. 2861 * 2862 * @params: pointer to the descriptor of the access 2863 * @table: array of trap descriptors 2864 * @num: size of the trap descriptor array 2865 * 2866 * Return true if the access has been handled, false if not. 2867 */ 2868 static bool emulate_cp(struct kvm_vcpu *vcpu, 2869 struct sys_reg_params *params, 2870 const struct sys_reg_desc *table, 2871 size_t num) 2872 { 2873 const struct sys_reg_desc *r; 2874 2875 if (!table) 2876 return false; /* Not handled */ 2877 2878 r = find_reg(params, table, num); 2879 2880 if (r) { 2881 perform_access(vcpu, params, r); 2882 return true; 2883 } 2884 2885 /* Not handled */ 2886 return false; 2887 } 2888 2889 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2890 struct sys_reg_params *params) 2891 { 2892 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2893 int cp = -1; 2894 2895 switch (esr_ec) { 2896 case ESR_ELx_EC_CP15_32: 2897 case ESR_ELx_EC_CP15_64: 2898 cp = 15; 2899 break; 2900 case ESR_ELx_EC_CP14_MR: 2901 case ESR_ELx_EC_CP14_64: 2902 cp = 14; 2903 break; 2904 default: 2905 WARN_ON(1); 2906 } 2907 2908 print_sys_reg_msg(params, 2909 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2910 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2911 kvm_inject_undefined(vcpu); 2912 } 2913 2914 /** 2915 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2916 * @vcpu: The VCPU pointer 2917 * @run: The kvm_run struct 2918 */ 2919 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2920 const struct sys_reg_desc *global, 2921 size_t nr_global) 2922 { 2923 struct sys_reg_params params; 2924 u64 esr = kvm_vcpu_get_esr(vcpu); 2925 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2926 int Rt2 = (esr >> 10) & 0x1f; 2927 2928 params.CRm = (esr >> 1) & 0xf; 2929 params.is_write = ((esr & 1) == 0); 2930 2931 params.Op0 = 0; 2932 params.Op1 = (esr >> 16) & 0xf; 2933 params.Op2 = 0; 2934 params.CRn = 0; 2935 2936 /* 2937 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2938 * backends between AArch32 and AArch64, we get away with it. 2939 */ 2940 if (params.is_write) { 2941 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2942 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2943 } 2944 2945 /* 2946 * If the table contains a handler, handle the 2947 * potential register operation in the case of a read and return 2948 * with success. 2949 */ 2950 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 2951 /* Split up the value between registers for the read side */ 2952 if (!params.is_write) { 2953 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2954 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2955 } 2956 2957 return 1; 2958 } 2959 2960 unhandled_cp_access(vcpu, ¶ms); 2961 return 1; 2962 } 2963 2964 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 2965 2966 /* 2967 * The CP10 ID registers are architecturally mapped to AArch64 feature 2968 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 2969 * from AArch32. 2970 */ 2971 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 2972 { 2973 u8 reg_id = (esr >> 10) & 0xf; 2974 bool valid; 2975 2976 params->is_write = ((esr & 1) == 0); 2977 params->Op0 = 3; 2978 params->Op1 = 0; 2979 params->CRn = 0; 2980 params->CRm = 3; 2981 2982 /* CP10 ID registers are read-only */ 2983 valid = !params->is_write; 2984 2985 switch (reg_id) { 2986 /* MVFR0 */ 2987 case 0b0111: 2988 params->Op2 = 0; 2989 break; 2990 /* MVFR1 */ 2991 case 0b0110: 2992 params->Op2 = 1; 2993 break; 2994 /* MVFR2 */ 2995 case 0b0101: 2996 params->Op2 = 2; 2997 break; 2998 default: 2999 valid = false; 3000 } 3001 3002 if (valid) 3003 return true; 3004 3005 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 3006 params->is_write ? "write" : "read", reg_id); 3007 return false; 3008 } 3009 3010 /** 3011 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 3012 * VFP Register' from AArch32. 3013 * @vcpu: The vCPU pointer 3014 * 3015 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 3016 * Work out the correct AArch64 system register encoding and reroute to the 3017 * AArch64 system register emulation. 3018 */ 3019 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 3020 { 3021 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3022 u64 esr = kvm_vcpu_get_esr(vcpu); 3023 struct sys_reg_params params; 3024 3025 /* UNDEF on any unhandled register access */ 3026 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 3027 kvm_inject_undefined(vcpu); 3028 return 1; 3029 } 3030 3031 if (emulate_sys_reg(vcpu, ¶ms)) 3032 vcpu_set_reg(vcpu, Rt, params.regval); 3033 3034 return 1; 3035 } 3036 3037 /** 3038 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 3039 * CRn=0, which corresponds to the AArch32 feature 3040 * registers. 3041 * @vcpu: the vCPU pointer 3042 * @params: the system register access parameters. 3043 * 3044 * Our cp15 system register tables do not enumerate the AArch32 feature 3045 * registers. Conveniently, our AArch64 table does, and the AArch32 system 3046 * register encoding can be trivially remapped into the AArch64 for the feature 3047 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 3048 * 3049 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 3050 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 3051 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 3052 * treat undefined registers in this range as RAZ. 3053 */ 3054 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 3055 struct sys_reg_params *params) 3056 { 3057 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3058 3059 /* Treat impossible writes to RO registers as UNDEFINED */ 3060 if (params->is_write) { 3061 unhandled_cp_access(vcpu, params); 3062 return 1; 3063 } 3064 3065 params->Op0 = 3; 3066 3067 /* 3068 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 3069 * Avoid conflicting with future expansion of AArch64 feature registers 3070 * and simply treat them as RAZ here. 3071 */ 3072 if (params->CRm > 3) 3073 params->regval = 0; 3074 else if (!emulate_sys_reg(vcpu, params)) 3075 return 1; 3076 3077 vcpu_set_reg(vcpu, Rt, params->regval); 3078 return 1; 3079 } 3080 3081 /** 3082 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 3083 * @vcpu: The VCPU pointer 3084 * @run: The kvm_run struct 3085 */ 3086 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 3087 struct sys_reg_params *params, 3088 const struct sys_reg_desc *global, 3089 size_t nr_global) 3090 { 3091 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3092 3093 params->regval = vcpu_get_reg(vcpu, Rt); 3094 3095 if (emulate_cp(vcpu, params, global, nr_global)) { 3096 if (!params->is_write) 3097 vcpu_set_reg(vcpu, Rt, params->regval); 3098 return 1; 3099 } 3100 3101 unhandled_cp_access(vcpu, params); 3102 return 1; 3103 } 3104 3105 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 3106 { 3107 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 3108 } 3109 3110 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 3111 { 3112 struct sys_reg_params params; 3113 3114 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 3115 3116 /* 3117 * Certain AArch32 ID registers are handled by rerouting to the AArch64 3118 * system register table. Registers in the ID range where CRm=0 are 3119 * excluded from this scheme as they do not trivially map into AArch64 3120 * system register encodings. 3121 */ 3122 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 3123 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 3124 3125 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 3126 } 3127 3128 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 3129 { 3130 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 3131 } 3132 3133 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 3134 { 3135 struct sys_reg_params params; 3136 3137 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 3138 3139 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 3140 } 3141 3142 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 3143 { 3144 // See ARM DDI 0487E.a, section D12.3.2 3145 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 3146 } 3147 3148 /** 3149 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 3150 * @vcpu: The VCPU pointer 3151 * @params: Decoded system register parameters 3152 * 3153 * Return: true if the system register access was successful, false otherwise. 3154 */ 3155 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 3156 struct sys_reg_params *params) 3157 { 3158 const struct sys_reg_desc *r; 3159 3160 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3161 3162 if (likely(r)) { 3163 perform_access(vcpu, params, r); 3164 return true; 3165 } 3166 3167 if (is_imp_def_sys_reg(params)) { 3168 kvm_inject_undefined(vcpu); 3169 } else { 3170 print_sys_reg_msg(params, 3171 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 3172 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 3173 kvm_inject_undefined(vcpu); 3174 } 3175 return false; 3176 } 3177 3178 static void kvm_reset_id_regs(struct kvm_vcpu *vcpu) 3179 { 3180 const struct sys_reg_desc *idreg = first_idreg; 3181 u32 id = reg_to_encoding(idreg); 3182 struct kvm *kvm = vcpu->kvm; 3183 3184 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 3185 return; 3186 3187 lockdep_assert_held(&kvm->arch.config_lock); 3188 3189 /* Initialize all idregs */ 3190 while (is_id_reg(id)) { 3191 IDREG(kvm, id) = idreg->reset(vcpu, idreg); 3192 3193 idreg++; 3194 id = reg_to_encoding(idreg); 3195 } 3196 3197 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 3198 } 3199 3200 /** 3201 * kvm_reset_sys_regs - sets system registers to reset value 3202 * @vcpu: The VCPU pointer 3203 * 3204 * This function finds the right table above and sets the registers on the 3205 * virtual CPU struct to their architecturally defined reset values. 3206 */ 3207 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 3208 { 3209 unsigned long i; 3210 3211 kvm_reset_id_regs(vcpu); 3212 3213 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 3214 const struct sys_reg_desc *r = &sys_reg_descs[i]; 3215 3216 if (is_id_reg(reg_to_encoding(r))) 3217 continue; 3218 3219 if (r->reset) 3220 r->reset(vcpu, r); 3221 } 3222 } 3223 3224 /** 3225 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 3226 * @vcpu: The VCPU pointer 3227 */ 3228 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 3229 { 3230 struct sys_reg_params params; 3231 unsigned long esr = kvm_vcpu_get_esr(vcpu); 3232 int Rt = kvm_vcpu_sys_get_rt(vcpu); 3233 3234 trace_kvm_handle_sys_reg(esr); 3235 3236 if (__check_nv_sr_forward(vcpu)) 3237 return 1; 3238 3239 params = esr_sys64_to_params(esr); 3240 params.regval = vcpu_get_reg(vcpu, Rt); 3241 3242 if (!emulate_sys_reg(vcpu, ¶ms)) 3243 return 1; 3244 3245 if (!params.is_write) 3246 vcpu_set_reg(vcpu, Rt, params.regval); 3247 return 1; 3248 } 3249 3250 /****************************************************************************** 3251 * Userspace API 3252 *****************************************************************************/ 3253 3254 static bool index_to_params(u64 id, struct sys_reg_params *params) 3255 { 3256 switch (id & KVM_REG_SIZE_MASK) { 3257 case KVM_REG_SIZE_U64: 3258 /* Any unused index bits means it's not valid. */ 3259 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 3260 | KVM_REG_ARM_COPROC_MASK 3261 | KVM_REG_ARM64_SYSREG_OP0_MASK 3262 | KVM_REG_ARM64_SYSREG_OP1_MASK 3263 | KVM_REG_ARM64_SYSREG_CRN_MASK 3264 | KVM_REG_ARM64_SYSREG_CRM_MASK 3265 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 3266 return false; 3267 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 3268 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 3269 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 3270 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 3271 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 3272 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 3273 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 3274 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 3275 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 3276 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 3277 return true; 3278 default: 3279 return false; 3280 } 3281 } 3282 3283 const struct sys_reg_desc *get_reg_by_id(u64 id, 3284 const struct sys_reg_desc table[], 3285 unsigned int num) 3286 { 3287 struct sys_reg_params params; 3288 3289 if (!index_to_params(id, ¶ms)) 3290 return NULL; 3291 3292 return find_reg(¶ms, table, num); 3293 } 3294 3295 /* Decode an index value, and find the sys_reg_desc entry. */ 3296 static const struct sys_reg_desc * 3297 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 3298 const struct sys_reg_desc table[], unsigned int num) 3299 3300 { 3301 const struct sys_reg_desc *r; 3302 3303 /* We only do sys_reg for now. */ 3304 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 3305 return NULL; 3306 3307 r = get_reg_by_id(id, table, num); 3308 3309 /* Not saved in the sys_reg array and not otherwise accessible? */ 3310 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 3311 r = NULL; 3312 3313 return r; 3314 } 3315 3316 /* 3317 * These are the invariant sys_reg registers: we let the guest see the 3318 * host versions of these, so they're part of the guest state. 3319 * 3320 * A future CPU may provide a mechanism to present different values to 3321 * the guest, or a future kvm may trap them. 3322 */ 3323 3324 #define FUNCTION_INVARIANT(reg) \ 3325 static u64 get_##reg(struct kvm_vcpu *v, \ 3326 const struct sys_reg_desc *r) \ 3327 { \ 3328 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 3329 return ((struct sys_reg_desc *)r)->val; \ 3330 } 3331 3332 FUNCTION_INVARIANT(midr_el1) 3333 FUNCTION_INVARIANT(revidr_el1) 3334 FUNCTION_INVARIANT(aidr_el1) 3335 3336 static u64 get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 3337 { 3338 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 3339 return ((struct sys_reg_desc *)r)->val; 3340 } 3341 3342 /* ->val is filled in by kvm_sys_reg_table_init() */ 3343 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 3344 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 3345 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 3346 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 3347 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 3348 }; 3349 3350 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 3351 { 3352 const struct sys_reg_desc *r; 3353 3354 r = get_reg_by_id(id, invariant_sys_regs, 3355 ARRAY_SIZE(invariant_sys_regs)); 3356 if (!r) 3357 return -ENOENT; 3358 3359 return put_user(r->val, uaddr); 3360 } 3361 3362 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 3363 { 3364 const struct sys_reg_desc *r; 3365 u64 val; 3366 3367 r = get_reg_by_id(id, invariant_sys_regs, 3368 ARRAY_SIZE(invariant_sys_regs)); 3369 if (!r) 3370 return -ENOENT; 3371 3372 if (get_user(val, uaddr)) 3373 return -EFAULT; 3374 3375 /* This is what we mean by invariant: you can't change it. */ 3376 if (r->val != val) 3377 return -EINVAL; 3378 3379 return 0; 3380 } 3381 3382 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 3383 { 3384 u32 val; 3385 u32 __user *uval = uaddr; 3386 3387 /* Fail if we have unknown bits set. */ 3388 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 3389 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 3390 return -ENOENT; 3391 3392 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 3393 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 3394 if (KVM_REG_SIZE(id) != 4) 3395 return -ENOENT; 3396 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 3397 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 3398 if (val >= CSSELR_MAX) 3399 return -ENOENT; 3400 3401 return put_user(get_ccsidr(vcpu, val), uval); 3402 default: 3403 return -ENOENT; 3404 } 3405 } 3406 3407 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 3408 { 3409 u32 val, newval; 3410 u32 __user *uval = uaddr; 3411 3412 /* Fail if we have unknown bits set. */ 3413 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 3414 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 3415 return -ENOENT; 3416 3417 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 3418 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 3419 if (KVM_REG_SIZE(id) != 4) 3420 return -ENOENT; 3421 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 3422 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 3423 if (val >= CSSELR_MAX) 3424 return -ENOENT; 3425 3426 if (get_user(newval, uval)) 3427 return -EFAULT; 3428 3429 return set_ccsidr(vcpu, val, newval); 3430 default: 3431 return -ENOENT; 3432 } 3433 } 3434 3435 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 3436 const struct sys_reg_desc table[], unsigned int num) 3437 { 3438 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 3439 const struct sys_reg_desc *r; 3440 u64 val; 3441 int ret; 3442 3443 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 3444 if (!r || sysreg_hidden_user(vcpu, r)) 3445 return -ENOENT; 3446 3447 if (r->get_user) { 3448 ret = (r->get_user)(vcpu, r, &val); 3449 } else { 3450 val = __vcpu_sys_reg(vcpu, r->reg); 3451 ret = 0; 3452 } 3453 3454 if (!ret) 3455 ret = put_user(val, uaddr); 3456 3457 return ret; 3458 } 3459 3460 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 3461 { 3462 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 3463 int err; 3464 3465 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 3466 return demux_c15_get(vcpu, reg->id, uaddr); 3467 3468 err = get_invariant_sys_reg(reg->id, uaddr); 3469 if (err != -ENOENT) 3470 return err; 3471 3472 return kvm_sys_reg_get_user(vcpu, reg, 3473 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3474 } 3475 3476 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 3477 const struct sys_reg_desc table[], unsigned int num) 3478 { 3479 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 3480 const struct sys_reg_desc *r; 3481 u64 val; 3482 int ret; 3483 3484 if (get_user(val, uaddr)) 3485 return -EFAULT; 3486 3487 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 3488 if (!r || sysreg_hidden_user(vcpu, r)) 3489 return -ENOENT; 3490 3491 if (sysreg_user_write_ignore(vcpu, r)) 3492 return 0; 3493 3494 if (r->set_user) { 3495 ret = (r->set_user)(vcpu, r, val); 3496 } else { 3497 __vcpu_sys_reg(vcpu, r->reg) = val; 3498 ret = 0; 3499 } 3500 3501 return ret; 3502 } 3503 3504 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 3505 { 3506 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 3507 int err; 3508 3509 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 3510 return demux_c15_set(vcpu, reg->id, uaddr); 3511 3512 err = set_invariant_sys_reg(reg->id, uaddr); 3513 if (err != -ENOENT) 3514 return err; 3515 3516 return kvm_sys_reg_set_user(vcpu, reg, 3517 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3518 } 3519 3520 static unsigned int num_demux_regs(void) 3521 { 3522 return CSSELR_MAX; 3523 } 3524 3525 static int write_demux_regids(u64 __user *uindices) 3526 { 3527 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 3528 unsigned int i; 3529 3530 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 3531 for (i = 0; i < CSSELR_MAX; i++) { 3532 if (put_user(val | i, uindices)) 3533 return -EFAULT; 3534 uindices++; 3535 } 3536 return 0; 3537 } 3538 3539 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 3540 { 3541 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 3542 KVM_REG_ARM64_SYSREG | 3543 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 3544 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 3545 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 3546 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 3547 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 3548 } 3549 3550 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 3551 { 3552 if (!*uind) 3553 return true; 3554 3555 if (put_user(sys_reg_to_index(reg), *uind)) 3556 return false; 3557 3558 (*uind)++; 3559 return true; 3560 } 3561 3562 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 3563 const struct sys_reg_desc *rd, 3564 u64 __user **uind, 3565 unsigned int *total) 3566 { 3567 /* 3568 * Ignore registers we trap but don't save, 3569 * and for which no custom user accessor is provided. 3570 */ 3571 if (!(rd->reg || rd->get_user)) 3572 return 0; 3573 3574 if (sysreg_hidden_user(vcpu, rd)) 3575 return 0; 3576 3577 if (!copy_reg_to_user(rd, uind)) 3578 return -EFAULT; 3579 3580 (*total)++; 3581 return 0; 3582 } 3583 3584 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 3585 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 3586 { 3587 const struct sys_reg_desc *i2, *end2; 3588 unsigned int total = 0; 3589 int err; 3590 3591 i2 = sys_reg_descs; 3592 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 3593 3594 while (i2 != end2) { 3595 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 3596 if (err) 3597 return err; 3598 } 3599 return total; 3600 } 3601 3602 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 3603 { 3604 return ARRAY_SIZE(invariant_sys_regs) 3605 + num_demux_regs() 3606 + walk_sys_regs(vcpu, (u64 __user *)NULL); 3607 } 3608 3609 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 3610 { 3611 unsigned int i; 3612 int err; 3613 3614 /* Then give them all the invariant registers' indices. */ 3615 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 3616 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 3617 return -EFAULT; 3618 uindices++; 3619 } 3620 3621 err = walk_sys_regs(vcpu, uindices); 3622 if (err < 0) 3623 return err; 3624 uindices += err; 3625 3626 return write_demux_regids(uindices); 3627 } 3628 3629 int __init kvm_sys_reg_table_init(void) 3630 { 3631 struct sys_reg_params params; 3632 bool valid = true; 3633 unsigned int i; 3634 3635 /* Make sure tables are unique and in order. */ 3636 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 3637 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 3638 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 3639 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 3640 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 3641 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 3642 3643 if (!valid) 3644 return -EINVAL; 3645 3646 /* We abuse the reset function to overwrite the table itself. */ 3647 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 3648 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 3649 3650 /* Find the first idreg (SYS_ID_PFR0_EL1) in sys_reg_descs. */ 3651 params = encoding_to_params(SYS_ID_PFR0_EL1); 3652 first_idreg = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3653 if (!first_idreg) 3654 return -EINVAL; 3655 3656 if (kvm_get_mode() == KVM_MODE_NV) 3657 return populate_nv_trap_config(); 3658 3659 return 0; 3660 } 3661