1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/kvm_host.h> 15 #include <linux/mm.h> 16 #include <linux/printk.h> 17 #include <linux/uaccess.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/cputype.h> 21 #include <asm/debug-monitors.h> 22 #include <asm/esr.h> 23 #include <asm/kvm_arm.h> 24 #include <asm/kvm_emulate.h> 25 #include <asm/kvm_hyp.h> 26 #include <asm/kvm_mmu.h> 27 #include <asm/perf_event.h> 28 #include <asm/sysreg.h> 29 30 #include <trace/events/kvm.h> 31 32 #include "sys_regs.h" 33 34 #include "trace.h" 35 36 /* 37 * All of this file is extremely similar to the ARM coproc.c, but the 38 * types are different. My gut feeling is that it should be pretty 39 * easy to merge, but that would be an ABI breakage -- again. VFP 40 * would also need to be abstracted. 41 * 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 #define reg_to_encoding(x) \ 48 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \ 49 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2) 50 51 static bool read_from_write_only(struct kvm_vcpu *vcpu, 52 struct sys_reg_params *params, 53 const struct sys_reg_desc *r) 54 { 55 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 56 print_sys_reg_instr(params); 57 kvm_inject_undefined(vcpu); 58 return false; 59 } 60 61 static bool write_to_read_only(struct kvm_vcpu *vcpu, 62 struct sys_reg_params *params, 63 const struct sys_reg_desc *r) 64 { 65 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 66 print_sys_reg_instr(params); 67 kvm_inject_undefined(vcpu); 68 return false; 69 } 70 71 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 72 { 73 u64 val = 0x8badf00d8badf00d; 74 75 if (vcpu->arch.sysregs_loaded_on_cpu && 76 __vcpu_read_sys_reg_from_cpu(reg, &val)) 77 return val; 78 79 return __vcpu_sys_reg(vcpu, reg); 80 } 81 82 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 83 { 84 if (vcpu->arch.sysregs_loaded_on_cpu && 85 __vcpu_write_sys_reg_to_cpu(val, reg)) 86 return; 87 88 __vcpu_sys_reg(vcpu, reg) = val; 89 } 90 91 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ 92 static u32 cache_levels; 93 94 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 95 #define CSSELR_MAX 14 96 97 /* Which cache CCSIDR represents depends on CSSELR value. */ 98 static u32 get_ccsidr(u32 csselr) 99 { 100 u32 ccsidr; 101 102 /* Make sure noone else changes CSSELR during this! */ 103 local_irq_disable(); 104 write_sysreg(csselr, csselr_el1); 105 isb(); 106 ccsidr = read_sysreg(ccsidr_el1); 107 local_irq_enable(); 108 109 return ccsidr; 110 } 111 112 /* 113 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 114 */ 115 static bool access_dcsw(struct kvm_vcpu *vcpu, 116 struct sys_reg_params *p, 117 const struct sys_reg_desc *r) 118 { 119 if (!p->is_write) 120 return read_from_write_only(vcpu, p, r); 121 122 /* 123 * Only track S/W ops if we don't have FWB. It still indicates 124 * that the guest is a bit broken (S/W operations should only 125 * be done by firmware, knowing that there is only a single 126 * CPU left in the system, and certainly not from non-secure 127 * software). 128 */ 129 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 130 kvm_set_way_flush(vcpu); 131 132 return true; 133 } 134 135 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 136 { 137 switch (r->aarch32_map) { 138 case AA32_LO: 139 *mask = GENMASK_ULL(31, 0); 140 *shift = 0; 141 break; 142 case AA32_HI: 143 *mask = GENMASK_ULL(63, 32); 144 *shift = 32; 145 break; 146 default: 147 *mask = GENMASK_ULL(63, 0); 148 *shift = 0; 149 break; 150 } 151 } 152 153 /* 154 * Generic accessor for VM registers. Only called as long as HCR_TVM 155 * is set. If the guest enables the MMU, we stop trapping the VM 156 * sys_regs and leave it in complete control of the caches. 157 */ 158 static bool access_vm_reg(struct kvm_vcpu *vcpu, 159 struct sys_reg_params *p, 160 const struct sys_reg_desc *r) 161 { 162 bool was_enabled = vcpu_has_cache_enabled(vcpu); 163 u64 val, mask, shift; 164 165 BUG_ON(!p->is_write); 166 167 get_access_mask(r, &mask, &shift); 168 169 if (~mask) { 170 val = vcpu_read_sys_reg(vcpu, r->reg); 171 val &= ~mask; 172 } else { 173 val = 0; 174 } 175 176 val |= (p->regval & (mask >> shift)) << shift; 177 vcpu_write_sys_reg(vcpu, val, r->reg); 178 179 kvm_toggle_cache(vcpu, was_enabled); 180 return true; 181 } 182 183 static bool access_actlr(struct kvm_vcpu *vcpu, 184 struct sys_reg_params *p, 185 const struct sys_reg_desc *r) 186 { 187 u64 mask, shift; 188 189 if (p->is_write) 190 return ignore_write(vcpu, p); 191 192 get_access_mask(r, &mask, &shift); 193 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 194 195 return true; 196 } 197 198 /* 199 * Trap handler for the GICv3 SGI generation system register. 200 * Forward the request to the VGIC emulation. 201 * The cp15_64 code makes sure this automatically works 202 * for both AArch64 and AArch32 accesses. 203 */ 204 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 205 struct sys_reg_params *p, 206 const struct sys_reg_desc *r) 207 { 208 bool g1; 209 210 if (!p->is_write) 211 return read_from_write_only(vcpu, p, r); 212 213 /* 214 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 215 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 216 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 217 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 218 * group. 219 */ 220 if (p->Op0 == 0) { /* AArch32 */ 221 switch (p->Op1) { 222 default: /* Keep GCC quiet */ 223 case 0: /* ICC_SGI1R */ 224 g1 = true; 225 break; 226 case 1: /* ICC_ASGI1R */ 227 case 2: /* ICC_SGI0R */ 228 g1 = false; 229 break; 230 } 231 } else { /* AArch64 */ 232 switch (p->Op2) { 233 default: /* Keep GCC quiet */ 234 case 5: /* ICC_SGI1R_EL1 */ 235 g1 = true; 236 break; 237 case 6: /* ICC_ASGI1R_EL1 */ 238 case 7: /* ICC_SGI0R_EL1 */ 239 g1 = false; 240 break; 241 } 242 } 243 244 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 245 246 return true; 247 } 248 249 static bool access_gic_sre(struct kvm_vcpu *vcpu, 250 struct sys_reg_params *p, 251 const struct sys_reg_desc *r) 252 { 253 if (p->is_write) 254 return ignore_write(vcpu, p); 255 256 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 257 return true; 258 } 259 260 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 261 struct sys_reg_params *p, 262 const struct sys_reg_desc *r) 263 { 264 if (p->is_write) 265 return ignore_write(vcpu, p); 266 else 267 return read_zero(vcpu, p); 268 } 269 270 /* 271 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 272 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 273 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 274 * treat it separately. 275 */ 276 static bool trap_loregion(struct kvm_vcpu *vcpu, 277 struct sys_reg_params *p, 278 const struct sys_reg_desc *r) 279 { 280 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 281 u32 sr = reg_to_encoding(r); 282 283 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { 284 kvm_inject_undefined(vcpu); 285 return false; 286 } 287 288 if (p->is_write && sr == SYS_LORID_EL1) 289 return write_to_read_only(vcpu, p, r); 290 291 return trap_raz_wi(vcpu, p, r); 292 } 293 294 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 295 struct sys_reg_params *p, 296 const struct sys_reg_desc *r) 297 { 298 if (p->is_write) { 299 return ignore_write(vcpu, p); 300 } else { 301 p->regval = (1 << 3); 302 return true; 303 } 304 } 305 306 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 307 struct sys_reg_params *p, 308 const struct sys_reg_desc *r) 309 { 310 if (p->is_write) { 311 return ignore_write(vcpu, p); 312 } else { 313 p->regval = read_sysreg(dbgauthstatus_el1); 314 return true; 315 } 316 } 317 318 /* 319 * We want to avoid world-switching all the DBG registers all the 320 * time: 321 * 322 * - If we've touched any debug register, it is likely that we're 323 * going to touch more of them. It then makes sense to disable the 324 * traps and start doing the save/restore dance 325 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 326 * then mandatory to save/restore the registers, as the guest 327 * depends on them. 328 * 329 * For this, we use a DIRTY bit, indicating the guest has modified the 330 * debug registers, used as follow: 331 * 332 * On guest entry: 333 * - If the dirty bit is set (because we're coming back from trapping), 334 * disable the traps, save host registers, restore guest registers. 335 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 336 * set the dirty bit, disable the traps, save host registers, 337 * restore guest registers. 338 * - Otherwise, enable the traps 339 * 340 * On guest exit: 341 * - If the dirty bit is set, save guest registers, restore host 342 * registers and clear the dirty bit. This ensure that the host can 343 * now use the debug registers. 344 */ 345 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 346 struct sys_reg_params *p, 347 const struct sys_reg_desc *r) 348 { 349 if (p->is_write) { 350 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 351 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 352 } else { 353 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 354 } 355 356 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 357 358 return true; 359 } 360 361 /* 362 * reg_to_dbg/dbg_to_reg 363 * 364 * A 32 bit write to a debug register leave top bits alone 365 * A 32 bit read from a debug register only returns the bottom bits 366 * 367 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the 368 * hyp.S code switches between host and guest values in future. 369 */ 370 static void reg_to_dbg(struct kvm_vcpu *vcpu, 371 struct sys_reg_params *p, 372 const struct sys_reg_desc *rd, 373 u64 *dbg_reg) 374 { 375 u64 mask, shift, val; 376 377 get_access_mask(rd, &mask, &shift); 378 379 val = *dbg_reg; 380 val &= ~mask; 381 val |= (p->regval & (mask >> shift)) << shift; 382 *dbg_reg = val; 383 384 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 385 } 386 387 static void dbg_to_reg(struct kvm_vcpu *vcpu, 388 struct sys_reg_params *p, 389 const struct sys_reg_desc *rd, 390 u64 *dbg_reg) 391 { 392 u64 mask, shift; 393 394 get_access_mask(rd, &mask, &shift); 395 p->regval = (*dbg_reg & mask) >> shift; 396 } 397 398 static bool trap_bvr(struct kvm_vcpu *vcpu, 399 struct sys_reg_params *p, 400 const struct sys_reg_desc *rd) 401 { 402 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 403 404 if (p->is_write) 405 reg_to_dbg(vcpu, p, rd, dbg_reg); 406 else 407 dbg_to_reg(vcpu, p, rd, dbg_reg); 408 409 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 410 411 return true; 412 } 413 414 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 415 const struct kvm_one_reg *reg, void __user *uaddr) 416 { 417 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 418 419 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 420 return -EFAULT; 421 return 0; 422 } 423 424 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 425 const struct kvm_one_reg *reg, void __user *uaddr) 426 { 427 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 428 429 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 430 return -EFAULT; 431 return 0; 432 } 433 434 static void reset_bvr(struct kvm_vcpu *vcpu, 435 const struct sys_reg_desc *rd) 436 { 437 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; 438 } 439 440 static bool trap_bcr(struct kvm_vcpu *vcpu, 441 struct sys_reg_params *p, 442 const struct sys_reg_desc *rd) 443 { 444 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 445 446 if (p->is_write) 447 reg_to_dbg(vcpu, p, rd, dbg_reg); 448 else 449 dbg_to_reg(vcpu, p, rd, dbg_reg); 450 451 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 452 453 return true; 454 } 455 456 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 457 const struct kvm_one_reg *reg, void __user *uaddr) 458 { 459 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 460 461 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 462 return -EFAULT; 463 464 return 0; 465 } 466 467 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 468 const struct kvm_one_reg *reg, void __user *uaddr) 469 { 470 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 471 472 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 473 return -EFAULT; 474 return 0; 475 } 476 477 static void reset_bcr(struct kvm_vcpu *vcpu, 478 const struct sys_reg_desc *rd) 479 { 480 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; 481 } 482 483 static bool trap_wvr(struct kvm_vcpu *vcpu, 484 struct sys_reg_params *p, 485 const struct sys_reg_desc *rd) 486 { 487 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 488 489 if (p->is_write) 490 reg_to_dbg(vcpu, p, rd, dbg_reg); 491 else 492 dbg_to_reg(vcpu, p, rd, dbg_reg); 493 494 trace_trap_reg(__func__, rd->reg, p->is_write, 495 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]); 496 497 return true; 498 } 499 500 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 501 const struct kvm_one_reg *reg, void __user *uaddr) 502 { 503 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 504 505 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 506 return -EFAULT; 507 return 0; 508 } 509 510 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 511 const struct kvm_one_reg *reg, void __user *uaddr) 512 { 513 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 514 515 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 516 return -EFAULT; 517 return 0; 518 } 519 520 static void reset_wvr(struct kvm_vcpu *vcpu, 521 const struct sys_reg_desc *rd) 522 { 523 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; 524 } 525 526 static bool trap_wcr(struct kvm_vcpu *vcpu, 527 struct sys_reg_params *p, 528 const struct sys_reg_desc *rd) 529 { 530 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 531 532 if (p->is_write) 533 reg_to_dbg(vcpu, p, rd, dbg_reg); 534 else 535 dbg_to_reg(vcpu, p, rd, dbg_reg); 536 537 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 538 539 return true; 540 } 541 542 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 543 const struct kvm_one_reg *reg, void __user *uaddr) 544 { 545 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 546 547 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 548 return -EFAULT; 549 return 0; 550 } 551 552 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 553 const struct kvm_one_reg *reg, void __user *uaddr) 554 { 555 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 556 557 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 558 return -EFAULT; 559 return 0; 560 } 561 562 static void reset_wcr(struct kvm_vcpu *vcpu, 563 const struct sys_reg_desc *rd) 564 { 565 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; 566 } 567 568 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 569 { 570 u64 amair = read_sysreg(amair_el1); 571 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 572 } 573 574 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 575 { 576 u64 actlr = read_sysreg(actlr_el1); 577 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 578 } 579 580 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 581 { 582 u64 mpidr; 583 584 /* 585 * Map the vcpu_id into the first three affinity level fields of 586 * the MPIDR. We limit the number of VCPUs in level 0 due to a 587 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 588 * of the GICv3 to be able to address each CPU directly when 589 * sending IPIs. 590 */ 591 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 592 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 593 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 594 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 595 } 596 597 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 598 const struct sys_reg_desc *r) 599 { 600 if (kvm_vcpu_has_pmu(vcpu)) 601 return 0; 602 603 return REG_HIDDEN; 604 } 605 606 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 607 { 608 u64 pmcr, val; 609 610 /* No PMU available, PMCR_EL0 may UNDEF... */ 611 if (!kvm_arm_support_pmu_v3()) 612 return; 613 614 pmcr = read_sysreg(pmcr_el0); 615 /* 616 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN 617 * except PMCR.E resetting to zero. 618 */ 619 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) 620 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); 621 if (!system_supports_32bit_el0()) 622 val |= ARMV8_PMU_PMCR_LC; 623 __vcpu_sys_reg(vcpu, r->reg) = val; 624 } 625 626 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 627 { 628 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 629 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 630 631 if (!enabled) 632 kvm_inject_undefined(vcpu); 633 634 return !enabled; 635 } 636 637 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 638 { 639 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 640 } 641 642 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 643 { 644 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 645 } 646 647 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 648 { 649 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 650 } 651 652 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 653 { 654 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 655 } 656 657 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 658 const struct sys_reg_desc *r) 659 { 660 u64 val; 661 662 if (pmu_access_el0_disabled(vcpu)) 663 return false; 664 665 if (p->is_write) { 666 /* Only update writeable bits of PMCR */ 667 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 668 val &= ~ARMV8_PMU_PMCR_MASK; 669 val |= p->regval & ARMV8_PMU_PMCR_MASK; 670 if (!system_supports_32bit_el0()) 671 val |= ARMV8_PMU_PMCR_LC; 672 __vcpu_sys_reg(vcpu, PMCR_EL0) = val; 673 kvm_pmu_handle_pmcr(vcpu, val); 674 kvm_vcpu_pmu_restore_guest(vcpu); 675 } else { 676 /* PMCR.P & PMCR.C are RAZ */ 677 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 678 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 679 p->regval = val; 680 } 681 682 return true; 683 } 684 685 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 686 const struct sys_reg_desc *r) 687 { 688 if (pmu_access_event_counter_el0_disabled(vcpu)) 689 return false; 690 691 if (p->is_write) 692 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 693 else 694 /* return PMSELR.SEL field */ 695 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 696 & ARMV8_PMU_COUNTER_MASK; 697 698 return true; 699 } 700 701 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 702 const struct sys_reg_desc *r) 703 { 704 u64 pmceid, mask, shift; 705 706 BUG_ON(p->is_write); 707 708 if (pmu_access_el0_disabled(vcpu)) 709 return false; 710 711 get_access_mask(r, &mask, &shift); 712 713 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 714 pmceid &= mask; 715 pmceid >>= shift; 716 717 p->regval = pmceid; 718 719 return true; 720 } 721 722 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 723 { 724 u64 pmcr, val; 725 726 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 727 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 728 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 729 kvm_inject_undefined(vcpu); 730 return false; 731 } 732 733 return true; 734 } 735 736 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 737 struct sys_reg_params *p, 738 const struct sys_reg_desc *r) 739 { 740 u64 idx = ~0UL; 741 742 if (r->CRn == 9 && r->CRm == 13) { 743 if (r->Op2 == 2) { 744 /* PMXEVCNTR_EL0 */ 745 if (pmu_access_event_counter_el0_disabled(vcpu)) 746 return false; 747 748 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 749 & ARMV8_PMU_COUNTER_MASK; 750 } else if (r->Op2 == 0) { 751 /* PMCCNTR_EL0 */ 752 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 753 return false; 754 755 idx = ARMV8_PMU_CYCLE_IDX; 756 } 757 } else if (r->CRn == 0 && r->CRm == 9) { 758 /* PMCCNTR */ 759 if (pmu_access_event_counter_el0_disabled(vcpu)) 760 return false; 761 762 idx = ARMV8_PMU_CYCLE_IDX; 763 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 764 /* PMEVCNTRn_EL0 */ 765 if (pmu_access_event_counter_el0_disabled(vcpu)) 766 return false; 767 768 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 769 } 770 771 /* Catch any decoding mistake */ 772 WARN_ON(idx == ~0UL); 773 774 if (!pmu_counter_idx_valid(vcpu, idx)) 775 return false; 776 777 if (p->is_write) { 778 if (pmu_access_el0_disabled(vcpu)) 779 return false; 780 781 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 782 } else { 783 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 784 } 785 786 return true; 787 } 788 789 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 790 const struct sys_reg_desc *r) 791 { 792 u64 idx, reg; 793 794 if (pmu_access_el0_disabled(vcpu)) 795 return false; 796 797 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 798 /* PMXEVTYPER_EL0 */ 799 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 800 reg = PMEVTYPER0_EL0 + idx; 801 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 802 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 803 if (idx == ARMV8_PMU_CYCLE_IDX) 804 reg = PMCCFILTR_EL0; 805 else 806 /* PMEVTYPERn_EL0 */ 807 reg = PMEVTYPER0_EL0 + idx; 808 } else { 809 BUG(); 810 } 811 812 if (!pmu_counter_idx_valid(vcpu, idx)) 813 return false; 814 815 if (p->is_write) { 816 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 817 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 818 kvm_vcpu_pmu_restore_guest(vcpu); 819 } else { 820 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 821 } 822 823 return true; 824 } 825 826 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 827 const struct sys_reg_desc *r) 828 { 829 u64 val, mask; 830 831 if (pmu_access_el0_disabled(vcpu)) 832 return false; 833 834 mask = kvm_pmu_valid_counter_mask(vcpu); 835 if (p->is_write) { 836 val = p->regval & mask; 837 if (r->Op2 & 0x1) { 838 /* accessing PMCNTENSET_EL0 */ 839 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 840 kvm_pmu_enable_counter_mask(vcpu, val); 841 kvm_vcpu_pmu_restore_guest(vcpu); 842 } else { 843 /* accessing PMCNTENCLR_EL0 */ 844 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 845 kvm_pmu_disable_counter_mask(vcpu, val); 846 } 847 } else { 848 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; 849 } 850 851 return true; 852 } 853 854 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 855 const struct sys_reg_desc *r) 856 { 857 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 858 859 if (check_pmu_access_disabled(vcpu, 0)) 860 return false; 861 862 if (p->is_write) { 863 u64 val = p->regval & mask; 864 865 if (r->Op2 & 0x1) 866 /* accessing PMINTENSET_EL1 */ 867 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 868 else 869 /* accessing PMINTENCLR_EL1 */ 870 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 871 } else { 872 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; 873 } 874 875 return true; 876 } 877 878 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 879 const struct sys_reg_desc *r) 880 { 881 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 882 883 if (pmu_access_el0_disabled(vcpu)) 884 return false; 885 886 if (p->is_write) { 887 if (r->CRm & 0x2) 888 /* accessing PMOVSSET_EL0 */ 889 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 890 else 891 /* accessing PMOVSCLR_EL0 */ 892 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 893 } else { 894 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; 895 } 896 897 return true; 898 } 899 900 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 901 const struct sys_reg_desc *r) 902 { 903 u64 mask; 904 905 if (!p->is_write) 906 return read_from_write_only(vcpu, p, r); 907 908 if (pmu_write_swinc_el0_disabled(vcpu)) 909 return false; 910 911 mask = kvm_pmu_valid_counter_mask(vcpu); 912 kvm_pmu_software_increment(vcpu, p->regval & mask); 913 return true; 914 } 915 916 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 917 const struct sys_reg_desc *r) 918 { 919 if (p->is_write) { 920 if (!vcpu_mode_priv(vcpu)) { 921 kvm_inject_undefined(vcpu); 922 return false; 923 } 924 925 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 926 p->regval & ARMV8_PMU_USERENR_MASK; 927 } else { 928 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 929 & ARMV8_PMU_USERENR_MASK; 930 } 931 932 return true; 933 } 934 935 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 936 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 937 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 938 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 939 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 940 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 941 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 942 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 943 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 944 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 945 946 #define PMU_SYS_REG(r) \ 947 SYS_DESC(r), .reset = reset_unknown, .visibility = pmu_visibility 948 949 /* Macro to expand the PMEVCNTRn_EL0 register */ 950 #define PMU_PMEVCNTR_EL0(n) \ 951 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \ 952 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 953 954 /* Macro to expand the PMEVTYPERn_EL0 register */ 955 #define PMU_PMEVTYPER_EL0(n) \ 956 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \ 957 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 958 959 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 960 const struct sys_reg_desc *r) 961 { 962 kvm_inject_undefined(vcpu); 963 964 return false; 965 } 966 967 /* Macro to expand the AMU counter and type registers*/ 968 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 969 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 970 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 971 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 972 973 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 974 const struct sys_reg_desc *rd) 975 { 976 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 977 } 978 979 /* 980 * If we land here on a PtrAuth access, that is because we didn't 981 * fixup the access on exit by allowing the PtrAuth sysregs. The only 982 * way this happens is when the guest does not have PtrAuth support 983 * enabled. 984 */ 985 #define __PTRAUTH_KEY(k) \ 986 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 987 .visibility = ptrauth_visibility} 988 989 #define PTRAUTH_KEY(k) \ 990 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 991 __PTRAUTH_KEY(k ## KEYHI_EL1) 992 993 static bool access_arch_timer(struct kvm_vcpu *vcpu, 994 struct sys_reg_params *p, 995 const struct sys_reg_desc *r) 996 { 997 enum kvm_arch_timers tmr; 998 enum kvm_arch_timer_regs treg; 999 u64 reg = reg_to_encoding(r); 1000 1001 switch (reg) { 1002 case SYS_CNTP_TVAL_EL0: 1003 case SYS_AARCH32_CNTP_TVAL: 1004 tmr = TIMER_PTIMER; 1005 treg = TIMER_REG_TVAL; 1006 break; 1007 case SYS_CNTP_CTL_EL0: 1008 case SYS_AARCH32_CNTP_CTL: 1009 tmr = TIMER_PTIMER; 1010 treg = TIMER_REG_CTL; 1011 break; 1012 case SYS_CNTP_CVAL_EL0: 1013 case SYS_AARCH32_CNTP_CVAL: 1014 tmr = TIMER_PTIMER; 1015 treg = TIMER_REG_CVAL; 1016 break; 1017 default: 1018 BUG(); 1019 } 1020 1021 if (p->is_write) 1022 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1023 else 1024 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1025 1026 return true; 1027 } 1028 1029 #define FEATURE(x) (GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT)) 1030 1031 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1032 static u64 read_id_reg(const struct kvm_vcpu *vcpu, 1033 struct sys_reg_desc const *r, bool raz) 1034 { 1035 u32 id = reg_to_encoding(r); 1036 u64 val = raz ? 0 : read_sanitised_ftr_reg(id); 1037 1038 switch (id) { 1039 case SYS_ID_AA64PFR0_EL1: 1040 if (!vcpu_has_sve(vcpu)) 1041 val &= ~FEATURE(ID_AA64PFR0_SVE); 1042 val &= ~FEATURE(ID_AA64PFR0_AMU); 1043 val &= ~FEATURE(ID_AA64PFR0_CSV2); 1044 val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); 1045 val &= ~FEATURE(ID_AA64PFR0_CSV3); 1046 val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); 1047 break; 1048 case SYS_ID_AA64PFR1_EL1: 1049 val &= ~FEATURE(ID_AA64PFR1_MTE); 1050 break; 1051 case SYS_ID_AA64ISAR1_EL1: 1052 if (!vcpu_has_ptrauth(vcpu)) 1053 val &= ~(FEATURE(ID_AA64ISAR1_APA) | 1054 FEATURE(ID_AA64ISAR1_API) | 1055 FEATURE(ID_AA64ISAR1_GPA) | 1056 FEATURE(ID_AA64ISAR1_GPI)); 1057 break; 1058 case SYS_ID_AA64DFR0_EL1: 1059 /* Limit debug to ARMv8.0 */ 1060 val &= ~FEATURE(ID_AA64DFR0_DEBUGVER); 1061 val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6); 1062 /* Limit guests to PMUv3 for ARMv8.4 */ 1063 val = cpuid_feature_cap_perfmon_field(val, 1064 ID_AA64DFR0_PMUVER_SHIFT, 1065 kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); 1066 break; 1067 case SYS_ID_DFR0_EL1: 1068 /* Limit guests to PMUv3 for ARMv8.4 */ 1069 val = cpuid_feature_cap_perfmon_field(val, 1070 ID_DFR0_PERFMON_SHIFT, 1071 kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); 1072 break; 1073 } 1074 1075 return val; 1076 } 1077 1078 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1079 const struct sys_reg_desc *r) 1080 { 1081 u32 id = reg_to_encoding(r); 1082 1083 switch (id) { 1084 case SYS_ID_AA64ZFR0_EL1: 1085 if (!vcpu_has_sve(vcpu)) 1086 return REG_RAZ; 1087 break; 1088 } 1089 1090 return 0; 1091 } 1092 1093 /* cpufeature ID register access trap handlers */ 1094 1095 static bool __access_id_reg(struct kvm_vcpu *vcpu, 1096 struct sys_reg_params *p, 1097 const struct sys_reg_desc *r, 1098 bool raz) 1099 { 1100 if (p->is_write) 1101 return write_to_read_only(vcpu, p, r); 1102 1103 p->regval = read_id_reg(vcpu, r, raz); 1104 return true; 1105 } 1106 1107 static bool access_id_reg(struct kvm_vcpu *vcpu, 1108 struct sys_reg_params *p, 1109 const struct sys_reg_desc *r) 1110 { 1111 bool raz = sysreg_visible_as_raz(vcpu, r); 1112 1113 return __access_id_reg(vcpu, p, r, raz); 1114 } 1115 1116 static bool access_raz_id_reg(struct kvm_vcpu *vcpu, 1117 struct sys_reg_params *p, 1118 const struct sys_reg_desc *r) 1119 { 1120 return __access_id_reg(vcpu, p, r, true); 1121 } 1122 1123 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); 1124 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); 1125 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 1126 1127 /* Visibility overrides for SVE-specific control registers */ 1128 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1129 const struct sys_reg_desc *rd) 1130 { 1131 if (vcpu_has_sve(vcpu)) 1132 return 0; 1133 1134 return REG_HIDDEN; 1135 } 1136 1137 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1138 const struct sys_reg_desc *rd, 1139 const struct kvm_one_reg *reg, void __user *uaddr) 1140 { 1141 const u64 id = sys_reg_to_index(rd); 1142 u8 csv2, csv3; 1143 int err; 1144 u64 val; 1145 1146 err = reg_from_user(&val, uaddr, id); 1147 if (err) 1148 return err; 1149 1150 /* 1151 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as 1152 * it doesn't promise more than what is actually provided (the 1153 * guest could otherwise be covered in ectoplasmic residue). 1154 */ 1155 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT); 1156 if (csv2 > 1 || 1157 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) 1158 return -EINVAL; 1159 1160 /* Same thing for CSV3 */ 1161 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT); 1162 if (csv3 > 1 || 1163 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) 1164 return -EINVAL; 1165 1166 /* We can only differ with CSV[23], and anything else is an error */ 1167 val ^= read_id_reg(vcpu, rd, false); 1168 val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) | 1169 (0xFUL << ID_AA64PFR0_CSV3_SHIFT)); 1170 if (val) 1171 return -EINVAL; 1172 1173 vcpu->kvm->arch.pfr0_csv2 = csv2; 1174 vcpu->kvm->arch.pfr0_csv3 = csv3 ; 1175 1176 return 0; 1177 } 1178 1179 /* 1180 * cpufeature ID register user accessors 1181 * 1182 * For now, these registers are immutable for userspace, so no values 1183 * are stored, and for set_id_reg() we don't allow the effective value 1184 * to be changed. 1185 */ 1186 static int __get_id_reg(const struct kvm_vcpu *vcpu, 1187 const struct sys_reg_desc *rd, void __user *uaddr, 1188 bool raz) 1189 { 1190 const u64 id = sys_reg_to_index(rd); 1191 const u64 val = read_id_reg(vcpu, rd, raz); 1192 1193 return reg_to_user(uaddr, &val, id); 1194 } 1195 1196 static int __set_id_reg(const struct kvm_vcpu *vcpu, 1197 const struct sys_reg_desc *rd, void __user *uaddr, 1198 bool raz) 1199 { 1200 const u64 id = sys_reg_to_index(rd); 1201 int err; 1202 u64 val; 1203 1204 err = reg_from_user(&val, uaddr, id); 1205 if (err) 1206 return err; 1207 1208 /* This is what we mean by invariant: you can't change it. */ 1209 if (val != read_id_reg(vcpu, rd, raz)) 1210 return -EINVAL; 1211 1212 return 0; 1213 } 1214 1215 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1216 const struct kvm_one_reg *reg, void __user *uaddr) 1217 { 1218 bool raz = sysreg_visible_as_raz(vcpu, rd); 1219 1220 return __get_id_reg(vcpu, rd, uaddr, raz); 1221 } 1222 1223 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1224 const struct kvm_one_reg *reg, void __user *uaddr) 1225 { 1226 bool raz = sysreg_visible_as_raz(vcpu, rd); 1227 1228 return __set_id_reg(vcpu, rd, uaddr, raz); 1229 } 1230 1231 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1232 const struct kvm_one_reg *reg, void __user *uaddr) 1233 { 1234 return __get_id_reg(vcpu, rd, uaddr, true); 1235 } 1236 1237 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1238 const struct kvm_one_reg *reg, void __user *uaddr) 1239 { 1240 return __set_id_reg(vcpu, rd, uaddr, true); 1241 } 1242 1243 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1244 const struct sys_reg_desc *r) 1245 { 1246 if (p->is_write) 1247 return write_to_read_only(vcpu, p, r); 1248 1249 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1250 return true; 1251 } 1252 1253 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1254 const struct sys_reg_desc *r) 1255 { 1256 if (p->is_write) 1257 return write_to_read_only(vcpu, p, r); 1258 1259 p->regval = read_sysreg(clidr_el1); 1260 return true; 1261 } 1262 1263 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1264 const struct sys_reg_desc *r) 1265 { 1266 int reg = r->reg; 1267 1268 if (p->is_write) 1269 vcpu_write_sys_reg(vcpu, p->regval, reg); 1270 else 1271 p->regval = vcpu_read_sys_reg(vcpu, reg); 1272 return true; 1273 } 1274 1275 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1276 const struct sys_reg_desc *r) 1277 { 1278 u32 csselr; 1279 1280 if (p->is_write) 1281 return write_to_read_only(vcpu, p, r); 1282 1283 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1284 p->regval = get_ccsidr(csselr); 1285 1286 /* 1287 * Guests should not be doing cache operations by set/way at all, and 1288 * for this reason, we trap them and attempt to infer the intent, so 1289 * that we can flush the entire guest's address space at the appropriate 1290 * time. 1291 * To prevent this trapping from causing performance problems, let's 1292 * expose the geometry of all data and unified caches (which are 1293 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. 1294 * [If guests should attempt to infer aliasing properties from the 1295 * geometry (which is not permitted by the architecture), they would 1296 * only do so for virtually indexed caches.] 1297 */ 1298 if (!(csselr & 1)) // data or unified cache 1299 p->regval &= ~GENMASK(27, 3); 1300 return true; 1301 } 1302 1303 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1304 #define ID_SANITISED(name) { \ 1305 SYS_DESC(SYS_##name), \ 1306 .access = access_id_reg, \ 1307 .get_user = get_id_reg, \ 1308 .set_user = set_id_reg, \ 1309 .visibility = id_visibility, \ 1310 } 1311 1312 /* 1313 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1314 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1315 * (1 <= crm < 8, 0 <= Op2 < 8). 1316 */ 1317 #define ID_UNALLOCATED(crm, op2) { \ 1318 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1319 .access = access_raz_id_reg, \ 1320 .get_user = get_raz_id_reg, \ 1321 .set_user = set_raz_id_reg, \ 1322 } 1323 1324 /* 1325 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1326 * For now, these are exposed just like unallocated ID regs: they appear 1327 * RAZ for the guest. 1328 */ 1329 #define ID_HIDDEN(name) { \ 1330 SYS_DESC(SYS_##name), \ 1331 .access = access_raz_id_reg, \ 1332 .get_user = get_raz_id_reg, \ 1333 .set_user = set_raz_id_reg, \ 1334 } 1335 1336 /* 1337 * Architected system registers. 1338 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1339 * 1340 * Debug handling: We do trap most, if not all debug related system 1341 * registers. The implementation is good enough to ensure that a guest 1342 * can use these with minimal performance degradation. The drawback is 1343 * that we don't implement any of the external debug, none of the 1344 * OSlock protocol. This should be revisited if we ever encounter a 1345 * more demanding guest... 1346 */ 1347 static const struct sys_reg_desc sys_reg_descs[] = { 1348 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1349 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1350 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1351 1352 DBG_BCR_BVR_WCR_WVR_EL1(0), 1353 DBG_BCR_BVR_WCR_WVR_EL1(1), 1354 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1355 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1356 DBG_BCR_BVR_WCR_WVR_EL1(2), 1357 DBG_BCR_BVR_WCR_WVR_EL1(3), 1358 DBG_BCR_BVR_WCR_WVR_EL1(4), 1359 DBG_BCR_BVR_WCR_WVR_EL1(5), 1360 DBG_BCR_BVR_WCR_WVR_EL1(6), 1361 DBG_BCR_BVR_WCR_WVR_EL1(7), 1362 DBG_BCR_BVR_WCR_WVR_EL1(8), 1363 DBG_BCR_BVR_WCR_WVR_EL1(9), 1364 DBG_BCR_BVR_WCR_WVR_EL1(10), 1365 DBG_BCR_BVR_WCR_WVR_EL1(11), 1366 DBG_BCR_BVR_WCR_WVR_EL1(12), 1367 DBG_BCR_BVR_WCR_WVR_EL1(13), 1368 DBG_BCR_BVR_WCR_WVR_EL1(14), 1369 DBG_BCR_BVR_WCR_WVR_EL1(15), 1370 1371 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1372 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, 1373 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, 1374 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1375 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1376 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1377 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1378 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1379 1380 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1381 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1382 // DBGDTR[TR]X_EL0 share the same encoding 1383 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1384 1385 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1386 1387 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1388 1389 /* 1390 * ID regs: all ID_SANITISED() entries here must have corresponding 1391 * entries in arm64_ftr_regs[]. 1392 */ 1393 1394 /* AArch64 mappings of the AArch32 ID registers */ 1395 /* CRm=1 */ 1396 ID_SANITISED(ID_PFR0_EL1), 1397 ID_SANITISED(ID_PFR1_EL1), 1398 ID_SANITISED(ID_DFR0_EL1), 1399 ID_HIDDEN(ID_AFR0_EL1), 1400 ID_SANITISED(ID_MMFR0_EL1), 1401 ID_SANITISED(ID_MMFR1_EL1), 1402 ID_SANITISED(ID_MMFR2_EL1), 1403 ID_SANITISED(ID_MMFR3_EL1), 1404 1405 /* CRm=2 */ 1406 ID_SANITISED(ID_ISAR0_EL1), 1407 ID_SANITISED(ID_ISAR1_EL1), 1408 ID_SANITISED(ID_ISAR2_EL1), 1409 ID_SANITISED(ID_ISAR3_EL1), 1410 ID_SANITISED(ID_ISAR4_EL1), 1411 ID_SANITISED(ID_ISAR5_EL1), 1412 ID_SANITISED(ID_MMFR4_EL1), 1413 ID_SANITISED(ID_ISAR6_EL1), 1414 1415 /* CRm=3 */ 1416 ID_SANITISED(MVFR0_EL1), 1417 ID_SANITISED(MVFR1_EL1), 1418 ID_SANITISED(MVFR2_EL1), 1419 ID_UNALLOCATED(3,3), 1420 ID_SANITISED(ID_PFR2_EL1), 1421 ID_HIDDEN(ID_DFR1_EL1), 1422 ID_SANITISED(ID_MMFR5_EL1), 1423 ID_UNALLOCATED(3,7), 1424 1425 /* AArch64 ID registers */ 1426 /* CRm=4 */ 1427 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, 1428 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, 1429 ID_SANITISED(ID_AA64PFR1_EL1), 1430 ID_UNALLOCATED(4,2), 1431 ID_UNALLOCATED(4,3), 1432 ID_SANITISED(ID_AA64ZFR0_EL1), 1433 ID_UNALLOCATED(4,5), 1434 ID_UNALLOCATED(4,6), 1435 ID_UNALLOCATED(4,7), 1436 1437 /* CRm=5 */ 1438 ID_SANITISED(ID_AA64DFR0_EL1), 1439 ID_SANITISED(ID_AA64DFR1_EL1), 1440 ID_UNALLOCATED(5,2), 1441 ID_UNALLOCATED(5,3), 1442 ID_HIDDEN(ID_AA64AFR0_EL1), 1443 ID_HIDDEN(ID_AA64AFR1_EL1), 1444 ID_UNALLOCATED(5,6), 1445 ID_UNALLOCATED(5,7), 1446 1447 /* CRm=6 */ 1448 ID_SANITISED(ID_AA64ISAR0_EL1), 1449 ID_SANITISED(ID_AA64ISAR1_EL1), 1450 ID_UNALLOCATED(6,2), 1451 ID_UNALLOCATED(6,3), 1452 ID_UNALLOCATED(6,4), 1453 ID_UNALLOCATED(6,5), 1454 ID_UNALLOCATED(6,6), 1455 ID_UNALLOCATED(6,7), 1456 1457 /* CRm=7 */ 1458 ID_SANITISED(ID_AA64MMFR0_EL1), 1459 ID_SANITISED(ID_AA64MMFR1_EL1), 1460 ID_SANITISED(ID_AA64MMFR2_EL1), 1461 ID_UNALLOCATED(7,3), 1462 ID_UNALLOCATED(7,4), 1463 ID_UNALLOCATED(7,5), 1464 ID_UNALLOCATED(7,6), 1465 ID_UNALLOCATED(7,7), 1466 1467 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1468 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1469 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1470 1471 { SYS_DESC(SYS_RGSR_EL1), undef_access }, 1472 { SYS_DESC(SYS_GCR_EL1), undef_access }, 1473 1474 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1475 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1476 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1477 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1478 1479 PTRAUTH_KEY(APIA), 1480 PTRAUTH_KEY(APIB), 1481 PTRAUTH_KEY(APDA), 1482 PTRAUTH_KEY(APDB), 1483 PTRAUTH_KEY(APGA), 1484 1485 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1486 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1487 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1488 1489 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1490 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1491 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1492 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1493 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1494 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1495 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1496 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1497 1498 { SYS_DESC(SYS_TFSR_EL1), undef_access }, 1499 { SYS_DESC(SYS_TFSRE0_EL1), undef_access }, 1500 1501 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1502 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1503 1504 { PMU_SYS_REG(SYS_PMINTENSET_EL1), 1505 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1506 { PMU_SYS_REG(SYS_PMINTENCLR_EL1), 1507 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1508 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 1509 1510 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1511 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1512 1513 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1514 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1515 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1516 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1517 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1518 1519 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, 1520 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1521 1522 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1523 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1524 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1525 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1526 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1527 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1528 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1529 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1530 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1531 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1532 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1533 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1534 1535 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1536 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1537 1538 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 1539 1540 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1541 1542 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1543 { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, 1544 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1545 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1546 1547 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, 1548 .reset = reset_pmcr, .reg = PMCR_EL0 }, 1549 { PMU_SYS_REG(SYS_PMCNTENSET_EL0), 1550 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1551 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0), 1552 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1553 { PMU_SYS_REG(SYS_PMOVSCLR_EL0), 1554 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1555 { PMU_SYS_REG(SYS_PMSWINC_EL0), 1556 .access = access_pmswinc, .reg = PMSWINC_EL0 }, 1557 { PMU_SYS_REG(SYS_PMSELR_EL0), 1558 .access = access_pmselr, .reg = PMSELR_EL0 }, 1559 { PMU_SYS_REG(SYS_PMCEID0_EL0), 1560 .access = access_pmceid, .reset = NULL }, 1561 { PMU_SYS_REG(SYS_PMCEID1_EL0), 1562 .access = access_pmceid, .reset = NULL }, 1563 { PMU_SYS_REG(SYS_PMCCNTR_EL0), 1564 .access = access_pmu_evcntr, .reg = PMCCNTR_EL0 }, 1565 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0), 1566 .access = access_pmu_evtyper, .reset = NULL }, 1567 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0), 1568 .access = access_pmu_evcntr, .reset = NULL }, 1569 /* 1570 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1571 * in 32bit mode. Here we choose to reset it as zero for consistency. 1572 */ 1573 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr, 1574 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 1575 { PMU_SYS_REG(SYS_PMOVSSET_EL0), 1576 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1577 1578 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 1579 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 1580 1581 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 1582 1583 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 1584 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 1585 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 1586 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 1587 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 1588 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 1589 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 1590 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 1591 AMU_AMEVCNTR0_EL0(0), 1592 AMU_AMEVCNTR0_EL0(1), 1593 AMU_AMEVCNTR0_EL0(2), 1594 AMU_AMEVCNTR0_EL0(3), 1595 AMU_AMEVCNTR0_EL0(4), 1596 AMU_AMEVCNTR0_EL0(5), 1597 AMU_AMEVCNTR0_EL0(6), 1598 AMU_AMEVCNTR0_EL0(7), 1599 AMU_AMEVCNTR0_EL0(8), 1600 AMU_AMEVCNTR0_EL0(9), 1601 AMU_AMEVCNTR0_EL0(10), 1602 AMU_AMEVCNTR0_EL0(11), 1603 AMU_AMEVCNTR0_EL0(12), 1604 AMU_AMEVCNTR0_EL0(13), 1605 AMU_AMEVCNTR0_EL0(14), 1606 AMU_AMEVCNTR0_EL0(15), 1607 AMU_AMEVTYPER0_EL0(0), 1608 AMU_AMEVTYPER0_EL0(1), 1609 AMU_AMEVTYPER0_EL0(2), 1610 AMU_AMEVTYPER0_EL0(3), 1611 AMU_AMEVTYPER0_EL0(4), 1612 AMU_AMEVTYPER0_EL0(5), 1613 AMU_AMEVTYPER0_EL0(6), 1614 AMU_AMEVTYPER0_EL0(7), 1615 AMU_AMEVTYPER0_EL0(8), 1616 AMU_AMEVTYPER0_EL0(9), 1617 AMU_AMEVTYPER0_EL0(10), 1618 AMU_AMEVTYPER0_EL0(11), 1619 AMU_AMEVTYPER0_EL0(12), 1620 AMU_AMEVTYPER0_EL0(13), 1621 AMU_AMEVTYPER0_EL0(14), 1622 AMU_AMEVTYPER0_EL0(15), 1623 AMU_AMEVCNTR1_EL0(0), 1624 AMU_AMEVCNTR1_EL0(1), 1625 AMU_AMEVCNTR1_EL0(2), 1626 AMU_AMEVCNTR1_EL0(3), 1627 AMU_AMEVCNTR1_EL0(4), 1628 AMU_AMEVCNTR1_EL0(5), 1629 AMU_AMEVCNTR1_EL0(6), 1630 AMU_AMEVCNTR1_EL0(7), 1631 AMU_AMEVCNTR1_EL0(8), 1632 AMU_AMEVCNTR1_EL0(9), 1633 AMU_AMEVCNTR1_EL0(10), 1634 AMU_AMEVCNTR1_EL0(11), 1635 AMU_AMEVCNTR1_EL0(12), 1636 AMU_AMEVCNTR1_EL0(13), 1637 AMU_AMEVCNTR1_EL0(14), 1638 AMU_AMEVCNTR1_EL0(15), 1639 AMU_AMEVTYPER1_EL0(0), 1640 AMU_AMEVTYPER1_EL0(1), 1641 AMU_AMEVTYPER1_EL0(2), 1642 AMU_AMEVTYPER1_EL0(3), 1643 AMU_AMEVTYPER1_EL0(4), 1644 AMU_AMEVTYPER1_EL0(5), 1645 AMU_AMEVTYPER1_EL0(6), 1646 AMU_AMEVTYPER1_EL0(7), 1647 AMU_AMEVTYPER1_EL0(8), 1648 AMU_AMEVTYPER1_EL0(9), 1649 AMU_AMEVTYPER1_EL0(10), 1650 AMU_AMEVTYPER1_EL0(11), 1651 AMU_AMEVTYPER1_EL0(12), 1652 AMU_AMEVTYPER1_EL0(13), 1653 AMU_AMEVTYPER1_EL0(14), 1654 AMU_AMEVTYPER1_EL0(15), 1655 1656 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 1657 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 1658 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 1659 1660 /* PMEVCNTRn_EL0 */ 1661 PMU_PMEVCNTR_EL0(0), 1662 PMU_PMEVCNTR_EL0(1), 1663 PMU_PMEVCNTR_EL0(2), 1664 PMU_PMEVCNTR_EL0(3), 1665 PMU_PMEVCNTR_EL0(4), 1666 PMU_PMEVCNTR_EL0(5), 1667 PMU_PMEVCNTR_EL0(6), 1668 PMU_PMEVCNTR_EL0(7), 1669 PMU_PMEVCNTR_EL0(8), 1670 PMU_PMEVCNTR_EL0(9), 1671 PMU_PMEVCNTR_EL0(10), 1672 PMU_PMEVCNTR_EL0(11), 1673 PMU_PMEVCNTR_EL0(12), 1674 PMU_PMEVCNTR_EL0(13), 1675 PMU_PMEVCNTR_EL0(14), 1676 PMU_PMEVCNTR_EL0(15), 1677 PMU_PMEVCNTR_EL0(16), 1678 PMU_PMEVCNTR_EL0(17), 1679 PMU_PMEVCNTR_EL0(18), 1680 PMU_PMEVCNTR_EL0(19), 1681 PMU_PMEVCNTR_EL0(20), 1682 PMU_PMEVCNTR_EL0(21), 1683 PMU_PMEVCNTR_EL0(22), 1684 PMU_PMEVCNTR_EL0(23), 1685 PMU_PMEVCNTR_EL0(24), 1686 PMU_PMEVCNTR_EL0(25), 1687 PMU_PMEVCNTR_EL0(26), 1688 PMU_PMEVCNTR_EL0(27), 1689 PMU_PMEVCNTR_EL0(28), 1690 PMU_PMEVCNTR_EL0(29), 1691 PMU_PMEVCNTR_EL0(30), 1692 /* PMEVTYPERn_EL0 */ 1693 PMU_PMEVTYPER_EL0(0), 1694 PMU_PMEVTYPER_EL0(1), 1695 PMU_PMEVTYPER_EL0(2), 1696 PMU_PMEVTYPER_EL0(3), 1697 PMU_PMEVTYPER_EL0(4), 1698 PMU_PMEVTYPER_EL0(5), 1699 PMU_PMEVTYPER_EL0(6), 1700 PMU_PMEVTYPER_EL0(7), 1701 PMU_PMEVTYPER_EL0(8), 1702 PMU_PMEVTYPER_EL0(9), 1703 PMU_PMEVTYPER_EL0(10), 1704 PMU_PMEVTYPER_EL0(11), 1705 PMU_PMEVTYPER_EL0(12), 1706 PMU_PMEVTYPER_EL0(13), 1707 PMU_PMEVTYPER_EL0(14), 1708 PMU_PMEVTYPER_EL0(15), 1709 PMU_PMEVTYPER_EL0(16), 1710 PMU_PMEVTYPER_EL0(17), 1711 PMU_PMEVTYPER_EL0(18), 1712 PMU_PMEVTYPER_EL0(19), 1713 PMU_PMEVTYPER_EL0(20), 1714 PMU_PMEVTYPER_EL0(21), 1715 PMU_PMEVTYPER_EL0(22), 1716 PMU_PMEVTYPER_EL0(23), 1717 PMU_PMEVTYPER_EL0(24), 1718 PMU_PMEVTYPER_EL0(25), 1719 PMU_PMEVTYPER_EL0(26), 1720 PMU_PMEVTYPER_EL0(27), 1721 PMU_PMEVTYPER_EL0(28), 1722 PMU_PMEVTYPER_EL0(29), 1723 PMU_PMEVTYPER_EL0(30), 1724 /* 1725 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 1726 * in 32bit mode. Here we choose to reset it as zero for consistency. 1727 */ 1728 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper, 1729 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 1730 1731 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 1732 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 1733 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 1734 }; 1735 1736 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 1737 struct sys_reg_params *p, 1738 const struct sys_reg_desc *r) 1739 { 1740 if (p->is_write) { 1741 return ignore_write(vcpu, p); 1742 } else { 1743 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1744 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1745 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); 1746 1747 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | 1748 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | 1749 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) 1750 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); 1751 return true; 1752 } 1753 } 1754 1755 /* 1756 * AArch32 debug register mappings 1757 * 1758 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 1759 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 1760 * 1761 * None of the other registers share their location, so treat them as 1762 * if they were 64bit. 1763 */ 1764 #define DBG_BCR_BVR_WCR_WVR(n) \ 1765 /* DBGBVRn */ \ 1766 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 1767 /* DBGBCRn */ \ 1768 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 1769 /* DBGWVRn */ \ 1770 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 1771 /* DBGWCRn */ \ 1772 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 1773 1774 #define DBGBXVR(n) \ 1775 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 1776 1777 /* 1778 * Trapped cp14 registers. We generally ignore most of the external 1779 * debug, on the principle that they don't really make sense to a 1780 * guest. Revisit this one day, would this principle change. 1781 */ 1782 static const struct sys_reg_desc cp14_regs[] = { 1783 /* DBGDIDR */ 1784 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 1785 /* DBGDTRRXext */ 1786 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 1787 1788 DBG_BCR_BVR_WCR_WVR(0), 1789 /* DBGDSCRint */ 1790 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 1791 DBG_BCR_BVR_WCR_WVR(1), 1792 /* DBGDCCINT */ 1793 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 1794 /* DBGDSCRext */ 1795 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 1796 DBG_BCR_BVR_WCR_WVR(2), 1797 /* DBGDTR[RT]Xint */ 1798 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 1799 /* DBGDTR[RT]Xext */ 1800 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 1801 DBG_BCR_BVR_WCR_WVR(3), 1802 DBG_BCR_BVR_WCR_WVR(4), 1803 DBG_BCR_BVR_WCR_WVR(5), 1804 /* DBGWFAR */ 1805 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 1806 /* DBGOSECCR */ 1807 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 1808 DBG_BCR_BVR_WCR_WVR(6), 1809 /* DBGVCR */ 1810 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 1811 DBG_BCR_BVR_WCR_WVR(7), 1812 DBG_BCR_BVR_WCR_WVR(8), 1813 DBG_BCR_BVR_WCR_WVR(9), 1814 DBG_BCR_BVR_WCR_WVR(10), 1815 DBG_BCR_BVR_WCR_WVR(11), 1816 DBG_BCR_BVR_WCR_WVR(12), 1817 DBG_BCR_BVR_WCR_WVR(13), 1818 DBG_BCR_BVR_WCR_WVR(14), 1819 DBG_BCR_BVR_WCR_WVR(15), 1820 1821 /* DBGDRAR (32bit) */ 1822 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 1823 1824 DBGBXVR(0), 1825 /* DBGOSLAR */ 1826 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, 1827 DBGBXVR(1), 1828 /* DBGOSLSR */ 1829 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, 1830 DBGBXVR(2), 1831 DBGBXVR(3), 1832 /* DBGOSDLR */ 1833 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 1834 DBGBXVR(4), 1835 /* DBGPRCR */ 1836 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 1837 DBGBXVR(5), 1838 DBGBXVR(6), 1839 DBGBXVR(7), 1840 DBGBXVR(8), 1841 DBGBXVR(9), 1842 DBGBXVR(10), 1843 DBGBXVR(11), 1844 DBGBXVR(12), 1845 DBGBXVR(13), 1846 DBGBXVR(14), 1847 DBGBXVR(15), 1848 1849 /* DBGDSAR (32bit) */ 1850 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 1851 1852 /* DBGDEVID2 */ 1853 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 1854 /* DBGDEVID1 */ 1855 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 1856 /* DBGDEVID */ 1857 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 1858 /* DBGCLAIMSET */ 1859 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 1860 /* DBGCLAIMCLR */ 1861 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 1862 /* DBGAUTHSTATUS */ 1863 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 1864 }; 1865 1866 /* Trapped cp14 64bit registers */ 1867 static const struct sys_reg_desc cp14_64_regs[] = { 1868 /* DBGDRAR (64bit) */ 1869 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 1870 1871 /* DBGDSAR (64bit) */ 1872 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 1873 }; 1874 1875 /* Macro to expand the PMEVCNTRn register */ 1876 #define PMU_PMEVCNTR(n) \ 1877 /* PMEVCNTRn */ \ 1878 { Op1(0), CRn(0b1110), \ 1879 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1880 access_pmu_evcntr } 1881 1882 /* Macro to expand the PMEVTYPERn register */ 1883 #define PMU_PMEVTYPER(n) \ 1884 /* PMEVTYPERn */ \ 1885 { Op1(0), CRn(0b1110), \ 1886 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1887 access_pmu_evtyper } 1888 1889 /* 1890 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 1891 * depending on the way they are accessed (as a 32bit or a 64bit 1892 * register). 1893 */ 1894 static const struct sys_reg_desc cp15_regs[] = { 1895 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 1896 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 1897 /* ACTLR */ 1898 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 1899 /* ACTLR2 */ 1900 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 1901 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 1902 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 1903 /* TTBCR */ 1904 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 1905 /* TTBCR2 */ 1906 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 1907 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 1908 /* DFSR */ 1909 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 1910 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 1911 /* ADFSR */ 1912 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 1913 /* AIFSR */ 1914 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 1915 /* DFAR */ 1916 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 1917 /* IFAR */ 1918 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 1919 1920 /* 1921 * DC{C,I,CI}SW operations: 1922 */ 1923 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 1924 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 1925 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 1926 1927 /* PMU */ 1928 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, 1929 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, 1930 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, 1931 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, 1932 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, 1933 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, 1934 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, 1935 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, 1936 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, 1937 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, 1938 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, 1939 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, 1940 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, 1941 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, 1942 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, 1943 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid }, 1944 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid }, 1945 /* PMMIR */ 1946 { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi }, 1947 1948 /* PRRR/MAIR0 */ 1949 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 1950 /* NMRR/MAIR1 */ 1951 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 1952 /* AMAIR0 */ 1953 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 1954 /* AMAIR1 */ 1955 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 1956 1957 /* ICC_SRE */ 1958 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 1959 1960 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 1961 1962 /* Arch Tmers */ 1963 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 1964 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 1965 1966 /* PMEVCNTRn */ 1967 PMU_PMEVCNTR(0), 1968 PMU_PMEVCNTR(1), 1969 PMU_PMEVCNTR(2), 1970 PMU_PMEVCNTR(3), 1971 PMU_PMEVCNTR(4), 1972 PMU_PMEVCNTR(5), 1973 PMU_PMEVCNTR(6), 1974 PMU_PMEVCNTR(7), 1975 PMU_PMEVCNTR(8), 1976 PMU_PMEVCNTR(9), 1977 PMU_PMEVCNTR(10), 1978 PMU_PMEVCNTR(11), 1979 PMU_PMEVCNTR(12), 1980 PMU_PMEVCNTR(13), 1981 PMU_PMEVCNTR(14), 1982 PMU_PMEVCNTR(15), 1983 PMU_PMEVCNTR(16), 1984 PMU_PMEVCNTR(17), 1985 PMU_PMEVCNTR(18), 1986 PMU_PMEVCNTR(19), 1987 PMU_PMEVCNTR(20), 1988 PMU_PMEVCNTR(21), 1989 PMU_PMEVCNTR(22), 1990 PMU_PMEVCNTR(23), 1991 PMU_PMEVCNTR(24), 1992 PMU_PMEVCNTR(25), 1993 PMU_PMEVCNTR(26), 1994 PMU_PMEVCNTR(27), 1995 PMU_PMEVCNTR(28), 1996 PMU_PMEVCNTR(29), 1997 PMU_PMEVCNTR(30), 1998 /* PMEVTYPERn */ 1999 PMU_PMEVTYPER(0), 2000 PMU_PMEVTYPER(1), 2001 PMU_PMEVTYPER(2), 2002 PMU_PMEVTYPER(3), 2003 PMU_PMEVTYPER(4), 2004 PMU_PMEVTYPER(5), 2005 PMU_PMEVTYPER(6), 2006 PMU_PMEVTYPER(7), 2007 PMU_PMEVTYPER(8), 2008 PMU_PMEVTYPER(9), 2009 PMU_PMEVTYPER(10), 2010 PMU_PMEVTYPER(11), 2011 PMU_PMEVTYPER(12), 2012 PMU_PMEVTYPER(13), 2013 PMU_PMEVTYPER(14), 2014 PMU_PMEVTYPER(15), 2015 PMU_PMEVTYPER(16), 2016 PMU_PMEVTYPER(17), 2017 PMU_PMEVTYPER(18), 2018 PMU_PMEVTYPER(19), 2019 PMU_PMEVTYPER(20), 2020 PMU_PMEVTYPER(21), 2021 PMU_PMEVTYPER(22), 2022 PMU_PMEVTYPER(23), 2023 PMU_PMEVTYPER(24), 2024 PMU_PMEVTYPER(25), 2025 PMU_PMEVTYPER(26), 2026 PMU_PMEVTYPER(27), 2027 PMU_PMEVTYPER(28), 2028 PMU_PMEVTYPER(29), 2029 PMU_PMEVTYPER(30), 2030 /* PMCCFILTR */ 2031 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, 2032 2033 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2034 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2035 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 2036 }; 2037 2038 static const struct sys_reg_desc cp15_64_regs[] = { 2039 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2040 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, 2041 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2042 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 2043 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2044 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2045 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2046 }; 2047 2048 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2049 bool is_32) 2050 { 2051 unsigned int i; 2052 2053 for (i = 0; i < n; i++) { 2054 if (!is_32 && table[i].reg && !table[i].reset) { 2055 kvm_err("sys_reg table %p entry %d has lacks reset\n", 2056 table, i); 2057 return 1; 2058 } 2059 2060 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2061 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); 2062 return 1; 2063 } 2064 } 2065 2066 return 0; 2067 } 2068 2069 static int match_sys_reg(const void *key, const void *elt) 2070 { 2071 const unsigned long pval = (unsigned long)key; 2072 const struct sys_reg_desc *r = elt; 2073 2074 return pval - reg_to_encoding(r); 2075 } 2076 2077 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params, 2078 const struct sys_reg_desc table[], 2079 unsigned int num) 2080 { 2081 unsigned long pval = reg_to_encoding(params); 2082 2083 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg); 2084 } 2085 2086 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2087 { 2088 kvm_inject_undefined(vcpu); 2089 return 1; 2090 } 2091 2092 static void perform_access(struct kvm_vcpu *vcpu, 2093 struct sys_reg_params *params, 2094 const struct sys_reg_desc *r) 2095 { 2096 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2097 2098 /* Check for regs disabled by runtime config */ 2099 if (sysreg_hidden(vcpu, r)) { 2100 kvm_inject_undefined(vcpu); 2101 return; 2102 } 2103 2104 /* 2105 * Not having an accessor means that we have configured a trap 2106 * that we don't know how to handle. This certainly qualifies 2107 * as a gross bug that should be fixed right away. 2108 */ 2109 BUG_ON(!r->access); 2110 2111 /* Skip instruction if instructed so */ 2112 if (likely(r->access(vcpu, params, r))) 2113 kvm_incr_pc(vcpu); 2114 } 2115 2116 /* 2117 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2118 * call the corresponding trap handler. 2119 * 2120 * @params: pointer to the descriptor of the access 2121 * @table: array of trap descriptors 2122 * @num: size of the trap descriptor array 2123 * 2124 * Return 0 if the access has been handled, and -1 if not. 2125 */ 2126 static int emulate_cp(struct kvm_vcpu *vcpu, 2127 struct sys_reg_params *params, 2128 const struct sys_reg_desc *table, 2129 size_t num) 2130 { 2131 const struct sys_reg_desc *r; 2132 2133 if (!table) 2134 return -1; /* Not handled */ 2135 2136 r = find_reg(params, table, num); 2137 2138 if (r) { 2139 perform_access(vcpu, params, r); 2140 return 0; 2141 } 2142 2143 /* Not handled */ 2144 return -1; 2145 } 2146 2147 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2148 struct sys_reg_params *params) 2149 { 2150 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2151 int cp = -1; 2152 2153 switch (esr_ec) { 2154 case ESR_ELx_EC_CP15_32: 2155 case ESR_ELx_EC_CP15_64: 2156 cp = 15; 2157 break; 2158 case ESR_ELx_EC_CP14_MR: 2159 case ESR_ELx_EC_CP14_64: 2160 cp = 14; 2161 break; 2162 default: 2163 WARN_ON(1); 2164 } 2165 2166 print_sys_reg_msg(params, 2167 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2168 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2169 kvm_inject_undefined(vcpu); 2170 } 2171 2172 /** 2173 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2174 * @vcpu: The VCPU pointer 2175 * @run: The kvm_run struct 2176 */ 2177 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2178 const struct sys_reg_desc *global, 2179 size_t nr_global) 2180 { 2181 struct sys_reg_params params; 2182 u32 esr = kvm_vcpu_get_esr(vcpu); 2183 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2184 int Rt2 = (esr >> 10) & 0x1f; 2185 2186 params.CRm = (esr >> 1) & 0xf; 2187 params.is_write = ((esr & 1) == 0); 2188 2189 params.Op0 = 0; 2190 params.Op1 = (esr >> 16) & 0xf; 2191 params.Op2 = 0; 2192 params.CRn = 0; 2193 2194 /* 2195 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2196 * backends between AArch32 and AArch64, we get away with it. 2197 */ 2198 if (params.is_write) { 2199 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2200 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2201 } 2202 2203 /* 2204 * If the table contains a handler, handle the 2205 * potential register operation in the case of a read and return 2206 * with success. 2207 */ 2208 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2209 /* Split up the value between registers for the read side */ 2210 if (!params.is_write) { 2211 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2212 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2213 } 2214 2215 return 1; 2216 } 2217 2218 unhandled_cp_access(vcpu, ¶ms); 2219 return 1; 2220 } 2221 2222 /** 2223 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2224 * @vcpu: The VCPU pointer 2225 * @run: The kvm_run struct 2226 */ 2227 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2228 const struct sys_reg_desc *global, 2229 size_t nr_global) 2230 { 2231 struct sys_reg_params params; 2232 u32 esr = kvm_vcpu_get_esr(vcpu); 2233 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2234 2235 params.CRm = (esr >> 1) & 0xf; 2236 params.regval = vcpu_get_reg(vcpu, Rt); 2237 params.is_write = ((esr & 1) == 0); 2238 params.CRn = (esr >> 10) & 0xf; 2239 params.Op0 = 0; 2240 params.Op1 = (esr >> 14) & 0x7; 2241 params.Op2 = (esr >> 17) & 0x7; 2242 2243 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2244 if (!params.is_write) 2245 vcpu_set_reg(vcpu, Rt, params.regval); 2246 return 1; 2247 } 2248 2249 unhandled_cp_access(vcpu, ¶ms); 2250 return 1; 2251 } 2252 2253 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2254 { 2255 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2256 } 2257 2258 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2259 { 2260 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); 2261 } 2262 2263 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2264 { 2265 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2266 } 2267 2268 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2269 { 2270 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs)); 2271 } 2272 2273 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2274 { 2275 // See ARM DDI 0487E.a, section D12.3.2 2276 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2277 } 2278 2279 static int emulate_sys_reg(struct kvm_vcpu *vcpu, 2280 struct sys_reg_params *params) 2281 { 2282 const struct sys_reg_desc *r; 2283 2284 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2285 2286 if (likely(r)) { 2287 perform_access(vcpu, params, r); 2288 } else if (is_imp_def_sys_reg(params)) { 2289 kvm_inject_undefined(vcpu); 2290 } else { 2291 print_sys_reg_msg(params, 2292 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2293 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2294 kvm_inject_undefined(vcpu); 2295 } 2296 return 1; 2297 } 2298 2299 /** 2300 * kvm_reset_sys_regs - sets system registers to reset value 2301 * @vcpu: The VCPU pointer 2302 * 2303 * This function finds the right table above and sets the registers on the 2304 * virtual CPU struct to their architecturally defined reset values. 2305 */ 2306 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2307 { 2308 unsigned long i; 2309 2310 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2311 if (sys_reg_descs[i].reset) 2312 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2313 } 2314 2315 /** 2316 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2317 * @vcpu: The VCPU pointer 2318 */ 2319 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2320 { 2321 struct sys_reg_params params; 2322 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2323 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2324 int ret; 2325 2326 trace_kvm_handle_sys_reg(esr); 2327 2328 params.Op0 = (esr >> 20) & 3; 2329 params.Op1 = (esr >> 14) & 0x7; 2330 params.CRn = (esr >> 10) & 0xf; 2331 params.CRm = (esr >> 1) & 0xf; 2332 params.Op2 = (esr >> 17) & 0x7; 2333 params.regval = vcpu_get_reg(vcpu, Rt); 2334 params.is_write = !(esr & 1); 2335 2336 ret = emulate_sys_reg(vcpu, ¶ms); 2337 2338 if (!params.is_write) 2339 vcpu_set_reg(vcpu, Rt, params.regval); 2340 return ret; 2341 } 2342 2343 /****************************************************************************** 2344 * Userspace API 2345 *****************************************************************************/ 2346 2347 static bool index_to_params(u64 id, struct sys_reg_params *params) 2348 { 2349 switch (id & KVM_REG_SIZE_MASK) { 2350 case KVM_REG_SIZE_U64: 2351 /* Any unused index bits means it's not valid. */ 2352 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2353 | KVM_REG_ARM_COPROC_MASK 2354 | KVM_REG_ARM64_SYSREG_OP0_MASK 2355 | KVM_REG_ARM64_SYSREG_OP1_MASK 2356 | KVM_REG_ARM64_SYSREG_CRN_MASK 2357 | KVM_REG_ARM64_SYSREG_CRM_MASK 2358 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2359 return false; 2360 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2361 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2362 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2363 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2364 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2365 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2366 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2367 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2368 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2369 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2370 return true; 2371 default: 2372 return false; 2373 } 2374 } 2375 2376 const struct sys_reg_desc *find_reg_by_id(u64 id, 2377 struct sys_reg_params *params, 2378 const struct sys_reg_desc table[], 2379 unsigned int num) 2380 { 2381 if (!index_to_params(id, params)) 2382 return NULL; 2383 2384 return find_reg(params, table, num); 2385 } 2386 2387 /* Decode an index value, and find the sys_reg_desc entry. */ 2388 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, 2389 u64 id) 2390 { 2391 const struct sys_reg_desc *r; 2392 struct sys_reg_params params; 2393 2394 /* We only do sys_reg for now. */ 2395 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2396 return NULL; 2397 2398 if (!index_to_params(id, ¶ms)) 2399 return NULL; 2400 2401 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2402 2403 /* Not saved in the sys_reg array and not otherwise accessible? */ 2404 if (r && !(r->reg || r->get_user)) 2405 r = NULL; 2406 2407 return r; 2408 } 2409 2410 /* 2411 * These are the invariant sys_reg registers: we let the guest see the 2412 * host versions of these, so they're part of the guest state. 2413 * 2414 * A future CPU may provide a mechanism to present different values to 2415 * the guest, or a future kvm may trap them. 2416 */ 2417 2418 #define FUNCTION_INVARIANT(reg) \ 2419 static void get_##reg(struct kvm_vcpu *v, \ 2420 const struct sys_reg_desc *r) \ 2421 { \ 2422 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 2423 } 2424 2425 FUNCTION_INVARIANT(midr_el1) 2426 FUNCTION_INVARIANT(revidr_el1) 2427 FUNCTION_INVARIANT(clidr_el1) 2428 FUNCTION_INVARIANT(aidr_el1) 2429 2430 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 2431 { 2432 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 2433 } 2434 2435 /* ->val is filled in by kvm_sys_reg_table_init() */ 2436 static struct sys_reg_desc invariant_sys_regs[] = { 2437 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 2438 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 2439 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, 2440 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 2441 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 2442 }; 2443 2444 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) 2445 { 2446 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) 2447 return -EFAULT; 2448 return 0; 2449 } 2450 2451 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) 2452 { 2453 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) 2454 return -EFAULT; 2455 return 0; 2456 } 2457 2458 static int get_invariant_sys_reg(u64 id, void __user *uaddr) 2459 { 2460 struct sys_reg_params params; 2461 const struct sys_reg_desc *r; 2462 2463 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2464 ARRAY_SIZE(invariant_sys_regs)); 2465 if (!r) 2466 return -ENOENT; 2467 2468 return reg_to_user(uaddr, &r->val, id); 2469 } 2470 2471 static int set_invariant_sys_reg(u64 id, void __user *uaddr) 2472 { 2473 struct sys_reg_params params; 2474 const struct sys_reg_desc *r; 2475 int err; 2476 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ 2477 2478 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2479 ARRAY_SIZE(invariant_sys_regs)); 2480 if (!r) 2481 return -ENOENT; 2482 2483 err = reg_from_user(&val, uaddr, id); 2484 if (err) 2485 return err; 2486 2487 /* This is what we mean by invariant: you can't change it. */ 2488 if (r->val != val) 2489 return -EINVAL; 2490 2491 return 0; 2492 } 2493 2494 static bool is_valid_cache(u32 val) 2495 { 2496 u32 level, ctype; 2497 2498 if (val >= CSSELR_MAX) 2499 return false; 2500 2501 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 2502 level = (val >> 1); 2503 ctype = (cache_levels >> (level * 3)) & 7; 2504 2505 switch (ctype) { 2506 case 0: /* No cache */ 2507 return false; 2508 case 1: /* Instruction cache only */ 2509 return (val & 1); 2510 case 2: /* Data cache only */ 2511 case 4: /* Unified cache */ 2512 return !(val & 1); 2513 case 3: /* Separate instruction and data caches */ 2514 return true; 2515 default: /* Reserved: we can't know instruction or data. */ 2516 return false; 2517 } 2518 } 2519 2520 static int demux_c15_get(u64 id, void __user *uaddr) 2521 { 2522 u32 val; 2523 u32 __user *uval = uaddr; 2524 2525 /* Fail if we have unknown bits set. */ 2526 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2527 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2528 return -ENOENT; 2529 2530 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2531 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2532 if (KVM_REG_SIZE(id) != 4) 2533 return -ENOENT; 2534 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2535 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2536 if (!is_valid_cache(val)) 2537 return -ENOENT; 2538 2539 return put_user(get_ccsidr(val), uval); 2540 default: 2541 return -ENOENT; 2542 } 2543 } 2544 2545 static int demux_c15_set(u64 id, void __user *uaddr) 2546 { 2547 u32 val, newval; 2548 u32 __user *uval = uaddr; 2549 2550 /* Fail if we have unknown bits set. */ 2551 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2552 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2553 return -ENOENT; 2554 2555 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2556 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2557 if (KVM_REG_SIZE(id) != 4) 2558 return -ENOENT; 2559 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2560 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2561 if (!is_valid_cache(val)) 2562 return -ENOENT; 2563 2564 if (get_user(newval, uval)) 2565 return -EFAULT; 2566 2567 /* This is also invariant: you can't change it. */ 2568 if (newval != get_ccsidr(val)) 2569 return -EINVAL; 2570 return 0; 2571 default: 2572 return -ENOENT; 2573 } 2574 } 2575 2576 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2577 { 2578 const struct sys_reg_desc *r; 2579 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2580 2581 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2582 return demux_c15_get(reg->id, uaddr); 2583 2584 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2585 return -ENOENT; 2586 2587 r = index_to_sys_reg_desc(vcpu, reg->id); 2588 if (!r) 2589 return get_invariant_sys_reg(reg->id, uaddr); 2590 2591 /* Check for regs disabled by runtime config */ 2592 if (sysreg_hidden(vcpu, r)) 2593 return -ENOENT; 2594 2595 if (r->get_user) 2596 return (r->get_user)(vcpu, r, reg, uaddr); 2597 2598 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); 2599 } 2600 2601 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2602 { 2603 const struct sys_reg_desc *r; 2604 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2605 2606 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2607 return demux_c15_set(reg->id, uaddr); 2608 2609 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2610 return -ENOENT; 2611 2612 r = index_to_sys_reg_desc(vcpu, reg->id); 2613 if (!r) 2614 return set_invariant_sys_reg(reg->id, uaddr); 2615 2616 /* Check for regs disabled by runtime config */ 2617 if (sysreg_hidden(vcpu, r)) 2618 return -ENOENT; 2619 2620 if (r->set_user) 2621 return (r->set_user)(vcpu, r, reg, uaddr); 2622 2623 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); 2624 } 2625 2626 static unsigned int num_demux_regs(void) 2627 { 2628 unsigned int i, count = 0; 2629 2630 for (i = 0; i < CSSELR_MAX; i++) 2631 if (is_valid_cache(i)) 2632 count++; 2633 2634 return count; 2635 } 2636 2637 static int write_demux_regids(u64 __user *uindices) 2638 { 2639 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 2640 unsigned int i; 2641 2642 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 2643 for (i = 0; i < CSSELR_MAX; i++) { 2644 if (!is_valid_cache(i)) 2645 continue; 2646 if (put_user(val | i, uindices)) 2647 return -EFAULT; 2648 uindices++; 2649 } 2650 return 0; 2651 } 2652 2653 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 2654 { 2655 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 2656 KVM_REG_ARM64_SYSREG | 2657 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 2658 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 2659 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 2660 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 2661 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 2662 } 2663 2664 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 2665 { 2666 if (!*uind) 2667 return true; 2668 2669 if (put_user(sys_reg_to_index(reg), *uind)) 2670 return false; 2671 2672 (*uind)++; 2673 return true; 2674 } 2675 2676 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 2677 const struct sys_reg_desc *rd, 2678 u64 __user **uind, 2679 unsigned int *total) 2680 { 2681 /* 2682 * Ignore registers we trap but don't save, 2683 * and for which no custom user accessor is provided. 2684 */ 2685 if (!(rd->reg || rd->get_user)) 2686 return 0; 2687 2688 if (sysreg_hidden(vcpu, rd)) 2689 return 0; 2690 2691 if (!copy_reg_to_user(rd, uind)) 2692 return -EFAULT; 2693 2694 (*total)++; 2695 return 0; 2696 } 2697 2698 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 2699 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 2700 { 2701 const struct sys_reg_desc *i2, *end2; 2702 unsigned int total = 0; 2703 int err; 2704 2705 i2 = sys_reg_descs; 2706 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 2707 2708 while (i2 != end2) { 2709 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 2710 if (err) 2711 return err; 2712 } 2713 return total; 2714 } 2715 2716 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 2717 { 2718 return ARRAY_SIZE(invariant_sys_regs) 2719 + num_demux_regs() 2720 + walk_sys_regs(vcpu, (u64 __user *)NULL); 2721 } 2722 2723 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 2724 { 2725 unsigned int i; 2726 int err; 2727 2728 /* Then give them all the invariant registers' indices. */ 2729 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 2730 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 2731 return -EFAULT; 2732 uindices++; 2733 } 2734 2735 err = walk_sys_regs(vcpu, uindices); 2736 if (err < 0) 2737 return err; 2738 uindices += err; 2739 2740 return write_demux_regids(uindices); 2741 } 2742 2743 void kvm_sys_reg_table_init(void) 2744 { 2745 unsigned int i; 2746 struct sys_reg_desc clidr; 2747 2748 /* Make sure tables are unique and in order. */ 2749 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false)); 2750 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true)); 2751 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true)); 2752 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true)); 2753 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true)); 2754 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false)); 2755 2756 /* We abuse the reset function to overwrite the table itself. */ 2757 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 2758 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 2759 2760 /* 2761 * CLIDR format is awkward, so clean it up. See ARM B4.1.20: 2762 * 2763 * If software reads the Cache Type fields from Ctype1 2764 * upwards, once it has seen a value of 0b000, no caches 2765 * exist at further-out levels of the hierarchy. So, for 2766 * example, if Ctype3 is the first Cache Type field with a 2767 * value of 0b000, the values of Ctype4 to Ctype7 must be 2768 * ignored. 2769 */ 2770 get_clidr_el1(NULL, &clidr); /* Ugly... */ 2771 cache_levels = clidr.val; 2772 for (i = 0; i < 7; i++) 2773 if (((cache_levels >> (i*3)) & 7) == 0) 2774 break; 2775 /* Clear all higher bits. */ 2776 cache_levels &= (1 << (i*3))-1; 2777 } 2778