1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/kvm_host.h> 16 #include <linux/mm.h> 17 #include <linux/printk.h> 18 #include <linux/uaccess.h> 19 20 #include <asm/cacheflush.h> 21 #include <asm/cputype.h> 22 #include <asm/debug-monitors.h> 23 #include <asm/esr.h> 24 #include <asm/kvm_arm.h> 25 #include <asm/kvm_emulate.h> 26 #include <asm/kvm_hyp.h> 27 #include <asm/kvm_mmu.h> 28 #include <asm/kvm_nested.h> 29 #include <asm/perf_event.h> 30 #include <asm/sysreg.h> 31 32 #include <trace/events/kvm.h> 33 34 #include "sys_regs.h" 35 36 #include "trace.h" 37 38 /* 39 * For AArch32, we only take care of what is being trapped. Anything 40 * that has to do with init and userspace access has to go via the 41 * 64bit interface. 42 */ 43 44 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 45 46 static bool read_from_write_only(struct kvm_vcpu *vcpu, 47 struct sys_reg_params *params, 48 const struct sys_reg_desc *r) 49 { 50 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 51 print_sys_reg_instr(params); 52 kvm_inject_undefined(vcpu); 53 return false; 54 } 55 56 static bool write_to_read_only(struct kvm_vcpu *vcpu, 57 struct sys_reg_params *params, 58 const struct sys_reg_desc *r) 59 { 60 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 61 print_sys_reg_instr(params); 62 kvm_inject_undefined(vcpu); 63 return false; 64 } 65 66 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 67 { 68 u64 val = 0x8badf00d8badf00d; 69 70 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 71 __vcpu_read_sys_reg_from_cpu(reg, &val)) 72 return val; 73 74 return __vcpu_sys_reg(vcpu, reg); 75 } 76 77 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 78 { 79 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 80 __vcpu_write_sys_reg_to_cpu(val, reg)) 81 return; 82 83 __vcpu_sys_reg(vcpu, reg) = val; 84 } 85 86 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 87 #define CSSELR_MAX 14 88 89 /* 90 * Returns the minimum line size for the selected cache, expressed as 91 * Log2(bytes). 92 */ 93 static u8 get_min_cache_line_size(bool icache) 94 { 95 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 96 u8 field; 97 98 if (icache) 99 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 100 else 101 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 102 103 /* 104 * Cache line size is represented as Log2(words) in CTR_EL0. 105 * Log2(bytes) can be derived with the following: 106 * 107 * Log2(words) + 2 = Log2(bytes / 4) + 2 108 * = Log2(bytes) - 2 + 2 109 * = Log2(bytes) 110 */ 111 return field + 2; 112 } 113 114 /* Which cache CCSIDR represents depends on CSSELR value. */ 115 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 116 { 117 u8 line_size; 118 119 if (vcpu->arch.ccsidr) 120 return vcpu->arch.ccsidr[csselr]; 121 122 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 123 124 /* 125 * Fabricate a CCSIDR value as the overriding value does not exist. 126 * The real CCSIDR value will not be used as it can vary by the 127 * physical CPU which the vcpu currently resides in. 128 * 129 * The line size is determined with get_min_cache_line_size(), which 130 * should be valid for all CPUs even if they have different cache 131 * configuration. 132 * 133 * The associativity bits are cleared, meaning the geometry of all data 134 * and unified caches (which are guaranteed to be PIPT and thus 135 * non-aliasing) are 1 set and 1 way. 136 * Guests should not be doing cache operations by set/way at all, and 137 * for this reason, we trap them and attempt to infer the intent, so 138 * that we can flush the entire guest's address space at the appropriate 139 * time. The exposed geometry minimizes the number of the traps. 140 * [If guests should attempt to infer aliasing properties from the 141 * geometry (which is not permitted by the architecture), they would 142 * only do so for virtually indexed caches.] 143 * 144 * We don't check if the cache level exists as it is allowed to return 145 * an UNKNOWN value if not. 146 */ 147 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 148 } 149 150 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 151 { 152 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 153 u32 *ccsidr = vcpu->arch.ccsidr; 154 u32 i; 155 156 if ((val & CCSIDR_EL1_RES0) || 157 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 158 return -EINVAL; 159 160 if (!ccsidr) { 161 if (val == get_ccsidr(vcpu, csselr)) 162 return 0; 163 164 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 165 if (!ccsidr) 166 return -ENOMEM; 167 168 for (i = 0; i < CSSELR_MAX; i++) 169 ccsidr[i] = get_ccsidr(vcpu, i); 170 171 vcpu->arch.ccsidr = ccsidr; 172 } 173 174 ccsidr[csselr] = val; 175 176 return 0; 177 } 178 179 static bool access_rw(struct kvm_vcpu *vcpu, 180 struct sys_reg_params *p, 181 const struct sys_reg_desc *r) 182 { 183 if (p->is_write) 184 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 185 else 186 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 187 188 return true; 189 } 190 191 /* 192 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 193 */ 194 static bool access_dcsw(struct kvm_vcpu *vcpu, 195 struct sys_reg_params *p, 196 const struct sys_reg_desc *r) 197 { 198 if (!p->is_write) 199 return read_from_write_only(vcpu, p, r); 200 201 /* 202 * Only track S/W ops if we don't have FWB. It still indicates 203 * that the guest is a bit broken (S/W operations should only 204 * be done by firmware, knowing that there is only a single 205 * CPU left in the system, and certainly not from non-secure 206 * software). 207 */ 208 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 209 kvm_set_way_flush(vcpu); 210 211 return true; 212 } 213 214 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 215 { 216 switch (r->aarch32_map) { 217 case AA32_LO: 218 *mask = GENMASK_ULL(31, 0); 219 *shift = 0; 220 break; 221 case AA32_HI: 222 *mask = GENMASK_ULL(63, 32); 223 *shift = 32; 224 break; 225 default: 226 *mask = GENMASK_ULL(63, 0); 227 *shift = 0; 228 break; 229 } 230 } 231 232 /* 233 * Generic accessor for VM registers. Only called as long as HCR_TVM 234 * is set. If the guest enables the MMU, we stop trapping the VM 235 * sys_regs and leave it in complete control of the caches. 236 */ 237 static bool access_vm_reg(struct kvm_vcpu *vcpu, 238 struct sys_reg_params *p, 239 const struct sys_reg_desc *r) 240 { 241 bool was_enabled = vcpu_has_cache_enabled(vcpu); 242 u64 val, mask, shift; 243 244 BUG_ON(!p->is_write); 245 246 get_access_mask(r, &mask, &shift); 247 248 if (~mask) { 249 val = vcpu_read_sys_reg(vcpu, r->reg); 250 val &= ~mask; 251 } else { 252 val = 0; 253 } 254 255 val |= (p->regval & (mask >> shift)) << shift; 256 vcpu_write_sys_reg(vcpu, val, r->reg); 257 258 kvm_toggle_cache(vcpu, was_enabled); 259 return true; 260 } 261 262 static bool access_actlr(struct kvm_vcpu *vcpu, 263 struct sys_reg_params *p, 264 const struct sys_reg_desc *r) 265 { 266 u64 mask, shift; 267 268 if (p->is_write) 269 return ignore_write(vcpu, p); 270 271 get_access_mask(r, &mask, &shift); 272 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 273 274 return true; 275 } 276 277 /* 278 * Trap handler for the GICv3 SGI generation system register. 279 * Forward the request to the VGIC emulation. 280 * The cp15_64 code makes sure this automatically works 281 * for both AArch64 and AArch32 accesses. 282 */ 283 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 284 struct sys_reg_params *p, 285 const struct sys_reg_desc *r) 286 { 287 bool g1; 288 289 if (!p->is_write) 290 return read_from_write_only(vcpu, p, r); 291 292 /* 293 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 294 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 295 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 296 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 297 * group. 298 */ 299 if (p->Op0 == 0) { /* AArch32 */ 300 switch (p->Op1) { 301 default: /* Keep GCC quiet */ 302 case 0: /* ICC_SGI1R */ 303 g1 = true; 304 break; 305 case 1: /* ICC_ASGI1R */ 306 case 2: /* ICC_SGI0R */ 307 g1 = false; 308 break; 309 } 310 } else { /* AArch64 */ 311 switch (p->Op2) { 312 default: /* Keep GCC quiet */ 313 case 5: /* ICC_SGI1R_EL1 */ 314 g1 = true; 315 break; 316 case 6: /* ICC_ASGI1R_EL1 */ 317 case 7: /* ICC_SGI0R_EL1 */ 318 g1 = false; 319 break; 320 } 321 } 322 323 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 324 325 return true; 326 } 327 328 static bool access_gic_sre(struct kvm_vcpu *vcpu, 329 struct sys_reg_params *p, 330 const struct sys_reg_desc *r) 331 { 332 if (p->is_write) 333 return ignore_write(vcpu, p); 334 335 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 336 return true; 337 } 338 339 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 340 struct sys_reg_params *p, 341 const struct sys_reg_desc *r) 342 { 343 if (p->is_write) 344 return ignore_write(vcpu, p); 345 else 346 return read_zero(vcpu, p); 347 } 348 349 static bool trap_undef(struct kvm_vcpu *vcpu, 350 struct sys_reg_params *p, 351 const struct sys_reg_desc *r) 352 { 353 kvm_inject_undefined(vcpu); 354 return false; 355 } 356 357 /* 358 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 359 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 360 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 361 * treat it separately. 362 */ 363 static bool trap_loregion(struct kvm_vcpu *vcpu, 364 struct sys_reg_params *p, 365 const struct sys_reg_desc *r) 366 { 367 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 368 u32 sr = reg_to_encoding(r); 369 370 if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { 371 kvm_inject_undefined(vcpu); 372 return false; 373 } 374 375 if (p->is_write && sr == SYS_LORID_EL1) 376 return write_to_read_only(vcpu, p, r); 377 378 return trap_raz_wi(vcpu, p, r); 379 } 380 381 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 382 struct sys_reg_params *p, 383 const struct sys_reg_desc *r) 384 { 385 u64 oslsr; 386 387 if (!p->is_write) 388 return read_from_write_only(vcpu, p, r); 389 390 /* Forward the OSLK bit to OSLSR */ 391 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK; 392 if (p->regval & SYS_OSLAR_OSLK) 393 oslsr |= SYS_OSLSR_OSLK; 394 395 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 396 return true; 397 } 398 399 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 400 struct sys_reg_params *p, 401 const struct sys_reg_desc *r) 402 { 403 if (p->is_write) 404 return write_to_read_only(vcpu, p, r); 405 406 p->regval = __vcpu_sys_reg(vcpu, r->reg); 407 return true; 408 } 409 410 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 411 u64 val) 412 { 413 /* 414 * The only modifiable bit is the OSLK bit. Refuse the write if 415 * userspace attempts to change any other bit in the register. 416 */ 417 if ((val ^ rd->val) & ~SYS_OSLSR_OSLK) 418 return -EINVAL; 419 420 __vcpu_sys_reg(vcpu, rd->reg) = val; 421 return 0; 422 } 423 424 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 425 struct sys_reg_params *p, 426 const struct sys_reg_desc *r) 427 { 428 if (p->is_write) { 429 return ignore_write(vcpu, p); 430 } else { 431 p->regval = read_sysreg(dbgauthstatus_el1); 432 return true; 433 } 434 } 435 436 /* 437 * We want to avoid world-switching all the DBG registers all the 438 * time: 439 * 440 * - If we've touched any debug register, it is likely that we're 441 * going to touch more of them. It then makes sense to disable the 442 * traps and start doing the save/restore dance 443 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 444 * then mandatory to save/restore the registers, as the guest 445 * depends on them. 446 * 447 * For this, we use a DIRTY bit, indicating the guest has modified the 448 * debug registers, used as follow: 449 * 450 * On guest entry: 451 * - If the dirty bit is set (because we're coming back from trapping), 452 * disable the traps, save host registers, restore guest registers. 453 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 454 * set the dirty bit, disable the traps, save host registers, 455 * restore guest registers. 456 * - Otherwise, enable the traps 457 * 458 * On guest exit: 459 * - If the dirty bit is set, save guest registers, restore host 460 * registers and clear the dirty bit. This ensure that the host can 461 * now use the debug registers. 462 */ 463 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 464 struct sys_reg_params *p, 465 const struct sys_reg_desc *r) 466 { 467 access_rw(vcpu, p, r); 468 if (p->is_write) 469 vcpu_set_flag(vcpu, DEBUG_DIRTY); 470 471 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 472 473 return true; 474 } 475 476 /* 477 * reg_to_dbg/dbg_to_reg 478 * 479 * A 32 bit write to a debug register leave top bits alone 480 * A 32 bit read from a debug register only returns the bottom bits 481 * 482 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 483 * switches between host and guest values in future. 484 */ 485 static void reg_to_dbg(struct kvm_vcpu *vcpu, 486 struct sys_reg_params *p, 487 const struct sys_reg_desc *rd, 488 u64 *dbg_reg) 489 { 490 u64 mask, shift, val; 491 492 get_access_mask(rd, &mask, &shift); 493 494 val = *dbg_reg; 495 val &= ~mask; 496 val |= (p->regval & (mask >> shift)) << shift; 497 *dbg_reg = val; 498 499 vcpu_set_flag(vcpu, DEBUG_DIRTY); 500 } 501 502 static void dbg_to_reg(struct kvm_vcpu *vcpu, 503 struct sys_reg_params *p, 504 const struct sys_reg_desc *rd, 505 u64 *dbg_reg) 506 { 507 u64 mask, shift; 508 509 get_access_mask(rd, &mask, &shift); 510 p->regval = (*dbg_reg & mask) >> shift; 511 } 512 513 static bool trap_bvr(struct kvm_vcpu *vcpu, 514 struct sys_reg_params *p, 515 const struct sys_reg_desc *rd) 516 { 517 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 518 519 if (p->is_write) 520 reg_to_dbg(vcpu, p, rd, dbg_reg); 521 else 522 dbg_to_reg(vcpu, p, rd, dbg_reg); 523 524 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 525 526 return true; 527 } 528 529 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 530 u64 val) 531 { 532 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 533 return 0; 534 } 535 536 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 537 u64 *val) 538 { 539 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 540 return 0; 541 } 542 543 static void reset_bvr(struct kvm_vcpu *vcpu, 544 const struct sys_reg_desc *rd) 545 { 546 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 547 } 548 549 static bool trap_bcr(struct kvm_vcpu *vcpu, 550 struct sys_reg_params *p, 551 const struct sys_reg_desc *rd) 552 { 553 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 554 555 if (p->is_write) 556 reg_to_dbg(vcpu, p, rd, dbg_reg); 557 else 558 dbg_to_reg(vcpu, p, rd, dbg_reg); 559 560 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 561 562 return true; 563 } 564 565 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 566 u64 val) 567 { 568 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 569 return 0; 570 } 571 572 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 573 u64 *val) 574 { 575 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 576 return 0; 577 } 578 579 static void reset_bcr(struct kvm_vcpu *vcpu, 580 const struct sys_reg_desc *rd) 581 { 582 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 583 } 584 585 static bool trap_wvr(struct kvm_vcpu *vcpu, 586 struct sys_reg_params *p, 587 const struct sys_reg_desc *rd) 588 { 589 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 590 591 if (p->is_write) 592 reg_to_dbg(vcpu, p, rd, dbg_reg); 593 else 594 dbg_to_reg(vcpu, p, rd, dbg_reg); 595 596 trace_trap_reg(__func__, rd->CRm, p->is_write, 597 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 598 599 return true; 600 } 601 602 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 603 u64 val) 604 { 605 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 606 return 0; 607 } 608 609 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 610 u64 *val) 611 { 612 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 613 return 0; 614 } 615 616 static void reset_wvr(struct kvm_vcpu *vcpu, 617 const struct sys_reg_desc *rd) 618 { 619 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 620 } 621 622 static bool trap_wcr(struct kvm_vcpu *vcpu, 623 struct sys_reg_params *p, 624 const struct sys_reg_desc *rd) 625 { 626 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 627 628 if (p->is_write) 629 reg_to_dbg(vcpu, p, rd, dbg_reg); 630 else 631 dbg_to_reg(vcpu, p, rd, dbg_reg); 632 633 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 634 635 return true; 636 } 637 638 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 639 u64 val) 640 { 641 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 642 return 0; 643 } 644 645 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 646 u64 *val) 647 { 648 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 649 return 0; 650 } 651 652 static void reset_wcr(struct kvm_vcpu *vcpu, 653 const struct sys_reg_desc *rd) 654 { 655 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 656 } 657 658 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 659 { 660 u64 amair = read_sysreg(amair_el1); 661 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 662 } 663 664 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 665 { 666 u64 actlr = read_sysreg(actlr_el1); 667 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 668 } 669 670 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 671 { 672 u64 mpidr; 673 674 /* 675 * Map the vcpu_id into the first three affinity level fields of 676 * the MPIDR. We limit the number of VCPUs in level 0 due to a 677 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 678 * of the GICv3 to be able to address each CPU directly when 679 * sending IPIs. 680 */ 681 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 682 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 683 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 684 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 685 } 686 687 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 688 const struct sys_reg_desc *r) 689 { 690 if (kvm_vcpu_has_pmu(vcpu)) 691 return 0; 692 693 return REG_HIDDEN; 694 } 695 696 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 697 { 698 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); 699 700 /* No PMU available, any PMU reg may UNDEF... */ 701 if (!kvm_arm_support_pmu_v3()) 702 return; 703 704 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; 705 n &= ARMV8_PMU_PMCR_N_MASK; 706 if (n) 707 mask |= GENMASK(n - 1, 0); 708 709 reset_unknown(vcpu, r); 710 __vcpu_sys_reg(vcpu, r->reg) &= mask; 711 } 712 713 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 714 { 715 reset_unknown(vcpu, r); 716 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 717 } 718 719 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 720 { 721 reset_unknown(vcpu, r); 722 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK; 723 } 724 725 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 726 { 727 reset_unknown(vcpu, r); 728 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; 729 } 730 731 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 732 { 733 u64 pmcr; 734 735 /* No PMU available, PMCR_EL0 may UNDEF... */ 736 if (!kvm_arm_support_pmu_v3()) 737 return; 738 739 /* Only preserve PMCR_EL0.N, and reset the rest to 0 */ 740 pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT); 741 if (!kvm_supports_32bit_el0()) 742 pmcr |= ARMV8_PMU_PMCR_LC; 743 744 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 745 } 746 747 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 748 { 749 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 750 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 751 752 if (!enabled) 753 kvm_inject_undefined(vcpu); 754 755 return !enabled; 756 } 757 758 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 759 { 760 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 761 } 762 763 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 764 { 765 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 766 } 767 768 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 769 { 770 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 771 } 772 773 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 774 { 775 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 776 } 777 778 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 779 const struct sys_reg_desc *r) 780 { 781 u64 val; 782 783 if (pmu_access_el0_disabled(vcpu)) 784 return false; 785 786 if (p->is_write) { 787 /* 788 * Only update writeable bits of PMCR (continuing into 789 * kvm_pmu_handle_pmcr() as well) 790 */ 791 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 792 val &= ~ARMV8_PMU_PMCR_MASK; 793 val |= p->regval & ARMV8_PMU_PMCR_MASK; 794 if (!kvm_supports_32bit_el0()) 795 val |= ARMV8_PMU_PMCR_LC; 796 kvm_pmu_handle_pmcr(vcpu, val); 797 } else { 798 /* PMCR.P & PMCR.C are RAZ */ 799 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 800 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 801 p->regval = val; 802 } 803 804 return true; 805 } 806 807 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 808 const struct sys_reg_desc *r) 809 { 810 if (pmu_access_event_counter_el0_disabled(vcpu)) 811 return false; 812 813 if (p->is_write) 814 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 815 else 816 /* return PMSELR.SEL field */ 817 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 818 & ARMV8_PMU_COUNTER_MASK; 819 820 return true; 821 } 822 823 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 824 const struct sys_reg_desc *r) 825 { 826 u64 pmceid, mask, shift; 827 828 BUG_ON(p->is_write); 829 830 if (pmu_access_el0_disabled(vcpu)) 831 return false; 832 833 get_access_mask(r, &mask, &shift); 834 835 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 836 pmceid &= mask; 837 pmceid >>= shift; 838 839 p->regval = pmceid; 840 841 return true; 842 } 843 844 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 845 { 846 u64 pmcr, val; 847 848 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 849 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 850 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 851 kvm_inject_undefined(vcpu); 852 return false; 853 } 854 855 return true; 856 } 857 858 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 859 u64 *val) 860 { 861 u64 idx; 862 863 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 864 /* PMCCNTR_EL0 */ 865 idx = ARMV8_PMU_CYCLE_IDX; 866 else 867 /* PMEVCNTRn_EL0 */ 868 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 869 870 *val = kvm_pmu_get_counter_value(vcpu, idx); 871 return 0; 872 } 873 874 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 875 struct sys_reg_params *p, 876 const struct sys_reg_desc *r) 877 { 878 u64 idx = ~0UL; 879 880 if (r->CRn == 9 && r->CRm == 13) { 881 if (r->Op2 == 2) { 882 /* PMXEVCNTR_EL0 */ 883 if (pmu_access_event_counter_el0_disabled(vcpu)) 884 return false; 885 886 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 887 & ARMV8_PMU_COUNTER_MASK; 888 } else if (r->Op2 == 0) { 889 /* PMCCNTR_EL0 */ 890 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 891 return false; 892 893 idx = ARMV8_PMU_CYCLE_IDX; 894 } 895 } else if (r->CRn == 0 && r->CRm == 9) { 896 /* PMCCNTR */ 897 if (pmu_access_event_counter_el0_disabled(vcpu)) 898 return false; 899 900 idx = ARMV8_PMU_CYCLE_IDX; 901 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 902 /* PMEVCNTRn_EL0 */ 903 if (pmu_access_event_counter_el0_disabled(vcpu)) 904 return false; 905 906 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 907 } 908 909 /* Catch any decoding mistake */ 910 WARN_ON(idx == ~0UL); 911 912 if (!pmu_counter_idx_valid(vcpu, idx)) 913 return false; 914 915 if (p->is_write) { 916 if (pmu_access_el0_disabled(vcpu)) 917 return false; 918 919 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 920 } else { 921 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 922 } 923 924 return true; 925 } 926 927 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 928 const struct sys_reg_desc *r) 929 { 930 u64 idx, reg; 931 932 if (pmu_access_el0_disabled(vcpu)) 933 return false; 934 935 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 936 /* PMXEVTYPER_EL0 */ 937 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 938 reg = PMEVTYPER0_EL0 + idx; 939 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 940 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 941 if (idx == ARMV8_PMU_CYCLE_IDX) 942 reg = PMCCFILTR_EL0; 943 else 944 /* PMEVTYPERn_EL0 */ 945 reg = PMEVTYPER0_EL0 + idx; 946 } else { 947 BUG(); 948 } 949 950 if (!pmu_counter_idx_valid(vcpu, idx)) 951 return false; 952 953 if (p->is_write) { 954 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 955 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 956 kvm_vcpu_pmu_restore_guest(vcpu); 957 } else { 958 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 959 } 960 961 return true; 962 } 963 964 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 965 const struct sys_reg_desc *r) 966 { 967 u64 val, mask; 968 969 if (pmu_access_el0_disabled(vcpu)) 970 return false; 971 972 mask = kvm_pmu_valid_counter_mask(vcpu); 973 if (p->is_write) { 974 val = p->regval & mask; 975 if (r->Op2 & 0x1) { 976 /* accessing PMCNTENSET_EL0 */ 977 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 978 kvm_pmu_enable_counter_mask(vcpu, val); 979 kvm_vcpu_pmu_restore_guest(vcpu); 980 } else { 981 /* accessing PMCNTENCLR_EL0 */ 982 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 983 kvm_pmu_disable_counter_mask(vcpu, val); 984 } 985 } else { 986 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 987 } 988 989 return true; 990 } 991 992 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 993 const struct sys_reg_desc *r) 994 { 995 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 996 997 if (check_pmu_access_disabled(vcpu, 0)) 998 return false; 999 1000 if (p->is_write) { 1001 u64 val = p->regval & mask; 1002 1003 if (r->Op2 & 0x1) 1004 /* accessing PMINTENSET_EL1 */ 1005 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1006 else 1007 /* accessing PMINTENCLR_EL1 */ 1008 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1009 } else { 1010 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1011 } 1012 1013 return true; 1014 } 1015 1016 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1017 const struct sys_reg_desc *r) 1018 { 1019 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1020 1021 if (pmu_access_el0_disabled(vcpu)) 1022 return false; 1023 1024 if (p->is_write) { 1025 if (r->CRm & 0x2) 1026 /* accessing PMOVSSET_EL0 */ 1027 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1028 else 1029 /* accessing PMOVSCLR_EL0 */ 1030 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1031 } else { 1032 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1033 } 1034 1035 return true; 1036 } 1037 1038 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1039 const struct sys_reg_desc *r) 1040 { 1041 u64 mask; 1042 1043 if (!p->is_write) 1044 return read_from_write_only(vcpu, p, r); 1045 1046 if (pmu_write_swinc_el0_disabled(vcpu)) 1047 return false; 1048 1049 mask = kvm_pmu_valid_counter_mask(vcpu); 1050 kvm_pmu_software_increment(vcpu, p->regval & mask); 1051 return true; 1052 } 1053 1054 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1055 const struct sys_reg_desc *r) 1056 { 1057 if (p->is_write) { 1058 if (!vcpu_mode_priv(vcpu)) { 1059 kvm_inject_undefined(vcpu); 1060 return false; 1061 } 1062 1063 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1064 p->regval & ARMV8_PMU_USERENR_MASK; 1065 } else { 1066 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1067 & ARMV8_PMU_USERENR_MASK; 1068 } 1069 1070 return true; 1071 } 1072 1073 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1074 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1075 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1076 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1077 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1078 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1079 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1080 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1081 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1082 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1083 1084 #define PMU_SYS_REG(r) \ 1085 SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility 1086 1087 /* Macro to expand the PMEVCNTRn_EL0 register */ 1088 #define PMU_PMEVCNTR_EL0(n) \ 1089 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \ 1090 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1091 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1092 1093 /* Macro to expand the PMEVTYPERn_EL0 register */ 1094 #define PMU_PMEVTYPER_EL0(n) \ 1095 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \ 1096 .reset = reset_pmevtyper, \ 1097 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1098 1099 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1100 const struct sys_reg_desc *r) 1101 { 1102 kvm_inject_undefined(vcpu); 1103 1104 return false; 1105 } 1106 1107 /* Macro to expand the AMU counter and type registers*/ 1108 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1109 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1110 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1111 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1112 1113 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1114 const struct sys_reg_desc *rd) 1115 { 1116 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1117 } 1118 1119 /* 1120 * If we land here on a PtrAuth access, that is because we didn't 1121 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1122 * way this happens is when the guest does not have PtrAuth support 1123 * enabled. 1124 */ 1125 #define __PTRAUTH_KEY(k) \ 1126 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1127 .visibility = ptrauth_visibility} 1128 1129 #define PTRAUTH_KEY(k) \ 1130 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1131 __PTRAUTH_KEY(k ## KEYHI_EL1) 1132 1133 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1134 struct sys_reg_params *p, 1135 const struct sys_reg_desc *r) 1136 { 1137 enum kvm_arch_timers tmr; 1138 enum kvm_arch_timer_regs treg; 1139 u64 reg = reg_to_encoding(r); 1140 1141 switch (reg) { 1142 case SYS_CNTP_TVAL_EL0: 1143 case SYS_AARCH32_CNTP_TVAL: 1144 tmr = TIMER_PTIMER; 1145 treg = TIMER_REG_TVAL; 1146 break; 1147 case SYS_CNTP_CTL_EL0: 1148 case SYS_AARCH32_CNTP_CTL: 1149 tmr = TIMER_PTIMER; 1150 treg = TIMER_REG_CTL; 1151 break; 1152 case SYS_CNTP_CVAL_EL0: 1153 case SYS_AARCH32_CNTP_CVAL: 1154 tmr = TIMER_PTIMER; 1155 treg = TIMER_REG_CVAL; 1156 break; 1157 default: 1158 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1159 kvm_inject_undefined(vcpu); 1160 return false; 1161 } 1162 1163 if (p->is_write) 1164 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1165 else 1166 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1167 1168 return true; 1169 } 1170 1171 static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu) 1172 { 1173 if (kvm_vcpu_has_pmu(vcpu)) 1174 return vcpu->kvm->arch.dfr0_pmuver.imp; 1175 1176 return vcpu->kvm->arch.dfr0_pmuver.unimp; 1177 } 1178 1179 static u8 perfmon_to_pmuver(u8 perfmon) 1180 { 1181 switch (perfmon) { 1182 case ID_DFR0_EL1_PerfMon_PMUv3: 1183 return ID_AA64DFR0_EL1_PMUVer_IMP; 1184 case ID_DFR0_EL1_PerfMon_IMPDEF: 1185 return ID_AA64DFR0_EL1_PMUVer_IMP_DEF; 1186 default: 1187 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1188 return perfmon; 1189 } 1190 } 1191 1192 static u8 pmuver_to_perfmon(u8 pmuver) 1193 { 1194 switch (pmuver) { 1195 case ID_AA64DFR0_EL1_PMUVer_IMP: 1196 return ID_DFR0_EL1_PerfMon_PMUv3; 1197 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1198 return ID_DFR0_EL1_PerfMon_IMPDEF; 1199 default: 1200 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1201 return pmuver; 1202 } 1203 } 1204 1205 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1206 static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r) 1207 { 1208 u32 id = reg_to_encoding(r); 1209 u64 val; 1210 1211 if (sysreg_visible_as_raz(vcpu, r)) 1212 return 0; 1213 1214 val = read_sanitised_ftr_reg(id); 1215 1216 switch (id) { 1217 case SYS_ID_AA64PFR0_EL1: 1218 if (!vcpu_has_sve(vcpu)) 1219 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); 1220 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); 1221 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); 1222 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); 1223 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); 1224 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); 1225 if (kvm_vgic_global_state.type == VGIC_V3) { 1226 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); 1227 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1); 1228 } 1229 break; 1230 case SYS_ID_AA64PFR1_EL1: 1231 if (!kvm_has_mte(vcpu->kvm)) 1232 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1233 1234 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1235 break; 1236 case SYS_ID_AA64ISAR1_EL1: 1237 if (!vcpu_has_ptrauth(vcpu)) 1238 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1239 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1240 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1241 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1242 break; 1243 case SYS_ID_AA64ISAR2_EL1: 1244 if (!vcpu_has_ptrauth(vcpu)) 1245 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1246 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1247 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1248 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1249 break; 1250 case SYS_ID_AA64DFR0_EL1: 1251 /* Limit debug to ARMv8.0 */ 1252 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); 1253 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6); 1254 /* Set PMUver to the required version */ 1255 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); 1256 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), 1257 vcpu_pmuver(vcpu)); 1258 /* Hide SPE from guests */ 1259 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); 1260 break; 1261 case SYS_ID_DFR0_EL1: 1262 val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); 1263 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), 1264 pmuver_to_perfmon(vcpu_pmuver(vcpu))); 1265 break; 1266 case SYS_ID_AA64MMFR2_EL1: 1267 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1268 break; 1269 case SYS_ID_MMFR4_EL1: 1270 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1271 break; 1272 } 1273 1274 return val; 1275 } 1276 1277 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1278 const struct sys_reg_desc *r) 1279 { 1280 u32 id = reg_to_encoding(r); 1281 1282 switch (id) { 1283 case SYS_ID_AA64ZFR0_EL1: 1284 if (!vcpu_has_sve(vcpu)) 1285 return REG_RAZ; 1286 break; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1293 const struct sys_reg_desc *r) 1294 { 1295 /* 1296 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1297 * EL. Promote to RAZ/WI in order to guarantee consistency between 1298 * systems. 1299 */ 1300 if (!kvm_supports_32bit_el0()) 1301 return REG_RAZ | REG_USER_WI; 1302 1303 return id_visibility(vcpu, r); 1304 } 1305 1306 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1307 const struct sys_reg_desc *r) 1308 { 1309 return REG_RAZ; 1310 } 1311 1312 /* cpufeature ID register access trap handlers */ 1313 1314 static bool access_id_reg(struct kvm_vcpu *vcpu, 1315 struct sys_reg_params *p, 1316 const struct sys_reg_desc *r) 1317 { 1318 if (p->is_write) 1319 return write_to_read_only(vcpu, p, r); 1320 1321 p->regval = read_id_reg(vcpu, r); 1322 if (vcpu_has_nv(vcpu)) 1323 access_nested_id_reg(vcpu, p, r); 1324 1325 return true; 1326 } 1327 1328 /* Visibility overrides for SVE-specific control registers */ 1329 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1330 const struct sys_reg_desc *rd) 1331 { 1332 if (vcpu_has_sve(vcpu)) 1333 return 0; 1334 1335 return REG_HIDDEN; 1336 } 1337 1338 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1339 const struct sys_reg_desc *rd, 1340 u64 val) 1341 { 1342 u8 csv2, csv3; 1343 1344 /* 1345 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as 1346 * it doesn't promise more than what is actually provided (the 1347 * guest could otherwise be covered in ectoplasmic residue). 1348 */ 1349 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV2_SHIFT); 1350 if (csv2 > 1 || 1351 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) 1352 return -EINVAL; 1353 1354 /* Same thing for CSV3 */ 1355 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV3_SHIFT); 1356 if (csv3 > 1 || 1357 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) 1358 return -EINVAL; 1359 1360 /* We can only differ with CSV[23], and anything else is an error */ 1361 val ^= read_id_reg(vcpu, rd); 1362 val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) | 1363 ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3)); 1364 if (val) 1365 return -EINVAL; 1366 1367 vcpu->kvm->arch.pfr0_csv2 = csv2; 1368 vcpu->kvm->arch.pfr0_csv3 = csv3; 1369 1370 return 0; 1371 } 1372 1373 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1374 const struct sys_reg_desc *rd, 1375 u64 val) 1376 { 1377 u8 pmuver, host_pmuver; 1378 bool valid_pmu; 1379 1380 host_pmuver = kvm_arm_pmu_get_pmuver_limit(); 1381 1382 /* 1383 * Allow AA64DFR0_EL1.PMUver to be set from userspace as long 1384 * as it doesn't promise more than what the HW gives us. We 1385 * allow an IMPDEF PMU though, only if no PMU is supported 1386 * (KVM backward compatibility handling). 1387 */ 1388 pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val); 1389 if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver)) 1390 return -EINVAL; 1391 1392 valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF); 1393 1394 /* Make sure view register and PMU support do match */ 1395 if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) 1396 return -EINVAL; 1397 1398 /* We can only differ with PMUver, and anything else is an error */ 1399 val ^= read_id_reg(vcpu, rd); 1400 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); 1401 if (val) 1402 return -EINVAL; 1403 1404 if (valid_pmu) 1405 vcpu->kvm->arch.dfr0_pmuver.imp = pmuver; 1406 else 1407 vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver; 1408 1409 return 0; 1410 } 1411 1412 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1413 const struct sys_reg_desc *rd, 1414 u64 val) 1415 { 1416 u8 perfmon, host_perfmon; 1417 bool valid_pmu; 1418 1419 host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1420 1421 /* 1422 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1423 * it doesn't promise more than what the HW gives us on the 1424 * AArch64 side (as everything is emulated with that), and 1425 * that this is a PMUv3. 1426 */ 1427 perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val); 1428 if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) || 1429 (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)) 1430 return -EINVAL; 1431 1432 valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_EL1_PerfMon_IMPDEF); 1433 1434 /* Make sure view register and PMU support do match */ 1435 if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) 1436 return -EINVAL; 1437 1438 /* We can only differ with PerfMon, and anything else is an error */ 1439 val ^= read_id_reg(vcpu, rd); 1440 val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); 1441 if (val) 1442 return -EINVAL; 1443 1444 if (valid_pmu) 1445 vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon); 1446 else 1447 vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon); 1448 1449 return 0; 1450 } 1451 1452 /* 1453 * cpufeature ID register user accessors 1454 * 1455 * For now, these registers are immutable for userspace, so no values 1456 * are stored, and for set_id_reg() we don't allow the effective value 1457 * to be changed. 1458 */ 1459 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1460 u64 *val) 1461 { 1462 *val = read_id_reg(vcpu, rd); 1463 return 0; 1464 } 1465 1466 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1467 u64 val) 1468 { 1469 /* This is what we mean by invariant: you can't change it. */ 1470 if (val != read_id_reg(vcpu, rd)) 1471 return -EINVAL; 1472 1473 return 0; 1474 } 1475 1476 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1477 u64 *val) 1478 { 1479 *val = 0; 1480 return 0; 1481 } 1482 1483 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1484 u64 val) 1485 { 1486 return 0; 1487 } 1488 1489 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1490 const struct sys_reg_desc *r) 1491 { 1492 if (p->is_write) 1493 return write_to_read_only(vcpu, p, r); 1494 1495 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1496 return true; 1497 } 1498 1499 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1500 const struct sys_reg_desc *r) 1501 { 1502 if (p->is_write) 1503 return write_to_read_only(vcpu, p, r); 1504 1505 p->regval = __vcpu_sys_reg(vcpu, r->reg); 1506 return true; 1507 } 1508 1509 /* 1510 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 1511 * by the physical CPU which the vcpu currently resides in. 1512 */ 1513 static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1514 { 1515 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1516 u64 clidr; 1517 u8 loc; 1518 1519 if ((ctr_el0 & CTR_EL0_IDC)) { 1520 /* 1521 * Data cache clean to the PoU is not required so LoUU and LoUIS 1522 * will not be set and a unified cache, which will be marked as 1523 * LoC, will be added. 1524 * 1525 * If not DIC, let the unified cache L2 so that an instruction 1526 * cache can be added as L1 later. 1527 */ 1528 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 1529 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 1530 } else { 1531 /* 1532 * Data cache clean to the PoU is required so let L1 have a data 1533 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 1534 * it can be marked as LoC too. 1535 */ 1536 loc = 1; 1537 clidr = 1 << CLIDR_LOUU_SHIFT; 1538 clidr |= 1 << CLIDR_LOUIS_SHIFT; 1539 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 1540 } 1541 1542 /* 1543 * Instruction cache invalidation to the PoU is required so let L1 have 1544 * an instruction cache. If L1 already has a data cache, it will be 1545 * CACHE_TYPE_SEPARATE. 1546 */ 1547 if (!(ctr_el0 & CTR_EL0_DIC)) 1548 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 1549 1550 clidr |= loc << CLIDR_LOC_SHIFT; 1551 1552 /* 1553 * Add tag cache unified to data cache. Allocation tags and data are 1554 * unified in a cache line so that it looks valid even if there is only 1555 * one cache line. 1556 */ 1557 if (kvm_has_mte(vcpu->kvm)) 1558 clidr |= 2 << CLIDR_TTYPE_SHIFT(loc); 1559 1560 __vcpu_sys_reg(vcpu, r->reg) = clidr; 1561 } 1562 1563 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1564 u64 val) 1565 { 1566 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1567 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 1568 1569 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 1570 return -EINVAL; 1571 1572 __vcpu_sys_reg(vcpu, rd->reg) = val; 1573 1574 return 0; 1575 } 1576 1577 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1578 const struct sys_reg_desc *r) 1579 { 1580 int reg = r->reg; 1581 1582 if (p->is_write) 1583 vcpu_write_sys_reg(vcpu, p->regval, reg); 1584 else 1585 p->regval = vcpu_read_sys_reg(vcpu, reg); 1586 return true; 1587 } 1588 1589 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1590 const struct sys_reg_desc *r) 1591 { 1592 u32 csselr; 1593 1594 if (p->is_write) 1595 return write_to_read_only(vcpu, p, r); 1596 1597 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1598 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 1599 if (csselr < CSSELR_MAX) 1600 p->regval = get_ccsidr(vcpu, csselr); 1601 1602 return true; 1603 } 1604 1605 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 1606 const struct sys_reg_desc *rd) 1607 { 1608 if (kvm_has_mte(vcpu->kvm)) 1609 return 0; 1610 1611 return REG_HIDDEN; 1612 } 1613 1614 #define MTE_REG(name) { \ 1615 SYS_DESC(SYS_##name), \ 1616 .access = undef_access, \ 1617 .reset = reset_unknown, \ 1618 .reg = name, \ 1619 .visibility = mte_visibility, \ 1620 } 1621 1622 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 1623 const struct sys_reg_desc *rd) 1624 { 1625 if (vcpu_has_nv(vcpu)) 1626 return 0; 1627 1628 return REG_HIDDEN; 1629 } 1630 1631 #define EL2_REG(name, acc, rst, v) { \ 1632 SYS_DESC(SYS_##name), \ 1633 .access = acc, \ 1634 .reset = rst, \ 1635 .reg = name, \ 1636 .visibility = el2_visibility, \ 1637 .val = v, \ 1638 } 1639 1640 /* 1641 * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when 1642 * HCR_EL2.E2H==1, and only in the sysreg table for convenience of 1643 * handling traps. Given that, they are always hidden from userspace. 1644 */ 1645 static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, 1646 const struct sys_reg_desc *rd) 1647 { 1648 return REG_HIDDEN_USER; 1649 } 1650 1651 #define EL12_REG(name, acc, rst, v) { \ 1652 SYS_DESC(SYS_##name##_EL12), \ 1653 .access = acc, \ 1654 .reset = rst, \ 1655 .reg = name##_EL1, \ 1656 .val = v, \ 1657 .visibility = elx2_visibility, \ 1658 } 1659 1660 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1661 #define ID_SANITISED(name) { \ 1662 SYS_DESC(SYS_##name), \ 1663 .access = access_id_reg, \ 1664 .get_user = get_id_reg, \ 1665 .set_user = set_id_reg, \ 1666 .visibility = id_visibility, \ 1667 } 1668 1669 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1670 #define AA32_ID_SANITISED(name) { \ 1671 SYS_DESC(SYS_##name), \ 1672 .access = access_id_reg, \ 1673 .get_user = get_id_reg, \ 1674 .set_user = set_id_reg, \ 1675 .visibility = aa32_id_visibility, \ 1676 } 1677 1678 /* 1679 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1680 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1681 * (1 <= crm < 8, 0 <= Op2 < 8). 1682 */ 1683 #define ID_UNALLOCATED(crm, op2) { \ 1684 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1685 .access = access_id_reg, \ 1686 .get_user = get_id_reg, \ 1687 .set_user = set_id_reg, \ 1688 .visibility = raz_visibility \ 1689 } 1690 1691 /* 1692 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1693 * For now, these are exposed just like unallocated ID regs: they appear 1694 * RAZ for the guest. 1695 */ 1696 #define ID_HIDDEN(name) { \ 1697 SYS_DESC(SYS_##name), \ 1698 .access = access_id_reg, \ 1699 .get_user = get_id_reg, \ 1700 .set_user = set_id_reg, \ 1701 .visibility = raz_visibility, \ 1702 } 1703 1704 static bool access_sp_el1(struct kvm_vcpu *vcpu, 1705 struct sys_reg_params *p, 1706 const struct sys_reg_desc *r) 1707 { 1708 if (p->is_write) 1709 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 1710 else 1711 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 1712 1713 return true; 1714 } 1715 1716 static bool access_elr(struct kvm_vcpu *vcpu, 1717 struct sys_reg_params *p, 1718 const struct sys_reg_desc *r) 1719 { 1720 if (p->is_write) 1721 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 1722 else 1723 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 1724 1725 return true; 1726 } 1727 1728 static bool access_spsr(struct kvm_vcpu *vcpu, 1729 struct sys_reg_params *p, 1730 const struct sys_reg_desc *r) 1731 { 1732 if (p->is_write) 1733 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 1734 else 1735 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 1736 1737 return true; 1738 } 1739 1740 /* 1741 * Architected system registers. 1742 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1743 * 1744 * Debug handling: We do trap most, if not all debug related system 1745 * registers. The implementation is good enough to ensure that a guest 1746 * can use these with minimal performance degradation. The drawback is 1747 * that we don't implement any of the external debug architecture. 1748 * This should be revisited if we ever encounter a more demanding 1749 * guest... 1750 */ 1751 static const struct sys_reg_desc sys_reg_descs[] = { 1752 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1753 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1754 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1755 1756 DBG_BCR_BVR_WCR_WVR_EL1(0), 1757 DBG_BCR_BVR_WCR_WVR_EL1(1), 1758 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1759 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1760 DBG_BCR_BVR_WCR_WVR_EL1(2), 1761 DBG_BCR_BVR_WCR_WVR_EL1(3), 1762 DBG_BCR_BVR_WCR_WVR_EL1(4), 1763 DBG_BCR_BVR_WCR_WVR_EL1(5), 1764 DBG_BCR_BVR_WCR_WVR_EL1(6), 1765 DBG_BCR_BVR_WCR_WVR_EL1(7), 1766 DBG_BCR_BVR_WCR_WVR_EL1(8), 1767 DBG_BCR_BVR_WCR_WVR_EL1(9), 1768 DBG_BCR_BVR_WCR_WVR_EL1(10), 1769 DBG_BCR_BVR_WCR_WVR_EL1(11), 1770 DBG_BCR_BVR_WCR_WVR_EL1(12), 1771 DBG_BCR_BVR_WCR_WVR_EL1(13), 1772 DBG_BCR_BVR_WCR_WVR_EL1(14), 1773 DBG_BCR_BVR_WCR_WVR_EL1(15), 1774 1775 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1776 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 1777 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 1778 SYS_OSLSR_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 1779 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1780 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1781 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1782 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1783 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1784 1785 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1786 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1787 // DBGDTR[TR]X_EL0 share the same encoding 1788 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1789 1790 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1791 1792 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1793 1794 /* 1795 * ID regs: all ID_SANITISED() entries here must have corresponding 1796 * entries in arm64_ftr_regs[]. 1797 */ 1798 1799 /* AArch64 mappings of the AArch32 ID registers */ 1800 /* CRm=1 */ 1801 AA32_ID_SANITISED(ID_PFR0_EL1), 1802 AA32_ID_SANITISED(ID_PFR1_EL1), 1803 { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg, 1804 .get_user = get_id_reg, .set_user = set_id_dfr0_el1, 1805 .visibility = aa32_id_visibility, }, 1806 ID_HIDDEN(ID_AFR0_EL1), 1807 AA32_ID_SANITISED(ID_MMFR0_EL1), 1808 AA32_ID_SANITISED(ID_MMFR1_EL1), 1809 AA32_ID_SANITISED(ID_MMFR2_EL1), 1810 AA32_ID_SANITISED(ID_MMFR3_EL1), 1811 1812 /* CRm=2 */ 1813 AA32_ID_SANITISED(ID_ISAR0_EL1), 1814 AA32_ID_SANITISED(ID_ISAR1_EL1), 1815 AA32_ID_SANITISED(ID_ISAR2_EL1), 1816 AA32_ID_SANITISED(ID_ISAR3_EL1), 1817 AA32_ID_SANITISED(ID_ISAR4_EL1), 1818 AA32_ID_SANITISED(ID_ISAR5_EL1), 1819 AA32_ID_SANITISED(ID_MMFR4_EL1), 1820 AA32_ID_SANITISED(ID_ISAR6_EL1), 1821 1822 /* CRm=3 */ 1823 AA32_ID_SANITISED(MVFR0_EL1), 1824 AA32_ID_SANITISED(MVFR1_EL1), 1825 AA32_ID_SANITISED(MVFR2_EL1), 1826 ID_UNALLOCATED(3,3), 1827 AA32_ID_SANITISED(ID_PFR2_EL1), 1828 ID_HIDDEN(ID_DFR1_EL1), 1829 AA32_ID_SANITISED(ID_MMFR5_EL1), 1830 ID_UNALLOCATED(3,7), 1831 1832 /* AArch64 ID registers */ 1833 /* CRm=4 */ 1834 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, 1835 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, 1836 ID_SANITISED(ID_AA64PFR1_EL1), 1837 ID_UNALLOCATED(4,2), 1838 ID_UNALLOCATED(4,3), 1839 ID_SANITISED(ID_AA64ZFR0_EL1), 1840 ID_HIDDEN(ID_AA64SMFR0_EL1), 1841 ID_UNALLOCATED(4,6), 1842 ID_UNALLOCATED(4,7), 1843 1844 /* CRm=5 */ 1845 { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg, 1846 .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, }, 1847 ID_SANITISED(ID_AA64DFR1_EL1), 1848 ID_UNALLOCATED(5,2), 1849 ID_UNALLOCATED(5,3), 1850 ID_HIDDEN(ID_AA64AFR0_EL1), 1851 ID_HIDDEN(ID_AA64AFR1_EL1), 1852 ID_UNALLOCATED(5,6), 1853 ID_UNALLOCATED(5,7), 1854 1855 /* CRm=6 */ 1856 ID_SANITISED(ID_AA64ISAR0_EL1), 1857 ID_SANITISED(ID_AA64ISAR1_EL1), 1858 ID_SANITISED(ID_AA64ISAR2_EL1), 1859 ID_UNALLOCATED(6,3), 1860 ID_UNALLOCATED(6,4), 1861 ID_UNALLOCATED(6,5), 1862 ID_UNALLOCATED(6,6), 1863 ID_UNALLOCATED(6,7), 1864 1865 /* CRm=7 */ 1866 ID_SANITISED(ID_AA64MMFR0_EL1), 1867 ID_SANITISED(ID_AA64MMFR1_EL1), 1868 ID_SANITISED(ID_AA64MMFR2_EL1), 1869 ID_UNALLOCATED(7,3), 1870 ID_UNALLOCATED(7,4), 1871 ID_UNALLOCATED(7,5), 1872 ID_UNALLOCATED(7,6), 1873 ID_UNALLOCATED(7,7), 1874 1875 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1876 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1877 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1878 1879 MTE_REG(RGSR_EL1), 1880 MTE_REG(GCR_EL1), 1881 1882 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1883 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 1884 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 1885 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 1886 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1887 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1888 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1889 1890 PTRAUTH_KEY(APIA), 1891 PTRAUTH_KEY(APIB), 1892 PTRAUTH_KEY(APDA), 1893 PTRAUTH_KEY(APDB), 1894 PTRAUTH_KEY(APGA), 1895 1896 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 1897 { SYS_DESC(SYS_ELR_EL1), access_elr}, 1898 1899 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1900 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1901 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1902 1903 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1904 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1905 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1906 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1907 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1908 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1909 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1910 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1911 1912 MTE_REG(TFSR_EL1), 1913 MTE_REG(TFSRE0_EL1), 1914 1915 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1916 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1917 1918 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 1919 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 1920 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 1921 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 1922 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 1923 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 1924 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 1925 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 1926 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 1927 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 1928 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 1929 /* PMBIDR_EL1 is not trapped */ 1930 1931 { PMU_SYS_REG(SYS_PMINTENSET_EL1), 1932 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1933 { PMU_SYS_REG(SYS_PMINTENCLR_EL1), 1934 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1935 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 1936 1937 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1938 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1939 1940 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1941 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1942 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1943 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1944 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1945 1946 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 1947 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1948 1949 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1950 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1951 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1952 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1953 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1954 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1955 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1956 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1957 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1958 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1959 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1960 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1961 1962 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1963 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1964 1965 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 1966 1967 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1968 1969 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1970 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 1971 .set_user = set_clidr }, 1972 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 1973 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 1974 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1975 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1976 { SYS_DESC(SYS_SVCR), undef_access }, 1977 1978 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, 1979 .reset = reset_pmcr, .reg = PMCR_EL0 }, 1980 { PMU_SYS_REG(SYS_PMCNTENSET_EL0), 1981 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1982 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0), 1983 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1984 { PMU_SYS_REG(SYS_PMOVSCLR_EL0), 1985 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1986 /* 1987 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 1988 * previously (and pointlessly) advertised in the past... 1989 */ 1990 { PMU_SYS_REG(SYS_PMSWINC_EL0), 1991 .get_user = get_raz_reg, .set_user = set_wi_reg, 1992 .access = access_pmswinc, .reset = NULL }, 1993 { PMU_SYS_REG(SYS_PMSELR_EL0), 1994 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 1995 { PMU_SYS_REG(SYS_PMCEID0_EL0), 1996 .access = access_pmceid, .reset = NULL }, 1997 { PMU_SYS_REG(SYS_PMCEID1_EL0), 1998 .access = access_pmceid, .reset = NULL }, 1999 { PMU_SYS_REG(SYS_PMCCNTR_EL0), 2000 .access = access_pmu_evcntr, .reset = reset_unknown, 2001 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2002 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0), 2003 .access = access_pmu_evtyper, .reset = NULL }, 2004 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0), 2005 .access = access_pmu_evcntr, .reset = NULL }, 2006 /* 2007 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2008 * in 32bit mode. Here we choose to reset it as zero for consistency. 2009 */ 2010 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr, 2011 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2012 { PMU_SYS_REG(SYS_PMOVSSET_EL0), 2013 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 2014 2015 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2016 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2017 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2018 2019 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2020 2021 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2022 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2023 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2024 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2025 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2026 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2027 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2028 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2029 AMU_AMEVCNTR0_EL0(0), 2030 AMU_AMEVCNTR0_EL0(1), 2031 AMU_AMEVCNTR0_EL0(2), 2032 AMU_AMEVCNTR0_EL0(3), 2033 AMU_AMEVCNTR0_EL0(4), 2034 AMU_AMEVCNTR0_EL0(5), 2035 AMU_AMEVCNTR0_EL0(6), 2036 AMU_AMEVCNTR0_EL0(7), 2037 AMU_AMEVCNTR0_EL0(8), 2038 AMU_AMEVCNTR0_EL0(9), 2039 AMU_AMEVCNTR0_EL0(10), 2040 AMU_AMEVCNTR0_EL0(11), 2041 AMU_AMEVCNTR0_EL0(12), 2042 AMU_AMEVCNTR0_EL0(13), 2043 AMU_AMEVCNTR0_EL0(14), 2044 AMU_AMEVCNTR0_EL0(15), 2045 AMU_AMEVTYPER0_EL0(0), 2046 AMU_AMEVTYPER0_EL0(1), 2047 AMU_AMEVTYPER0_EL0(2), 2048 AMU_AMEVTYPER0_EL0(3), 2049 AMU_AMEVTYPER0_EL0(4), 2050 AMU_AMEVTYPER0_EL0(5), 2051 AMU_AMEVTYPER0_EL0(6), 2052 AMU_AMEVTYPER0_EL0(7), 2053 AMU_AMEVTYPER0_EL0(8), 2054 AMU_AMEVTYPER0_EL0(9), 2055 AMU_AMEVTYPER0_EL0(10), 2056 AMU_AMEVTYPER0_EL0(11), 2057 AMU_AMEVTYPER0_EL0(12), 2058 AMU_AMEVTYPER0_EL0(13), 2059 AMU_AMEVTYPER0_EL0(14), 2060 AMU_AMEVTYPER0_EL0(15), 2061 AMU_AMEVCNTR1_EL0(0), 2062 AMU_AMEVCNTR1_EL0(1), 2063 AMU_AMEVCNTR1_EL0(2), 2064 AMU_AMEVCNTR1_EL0(3), 2065 AMU_AMEVCNTR1_EL0(4), 2066 AMU_AMEVCNTR1_EL0(5), 2067 AMU_AMEVCNTR1_EL0(6), 2068 AMU_AMEVCNTR1_EL0(7), 2069 AMU_AMEVCNTR1_EL0(8), 2070 AMU_AMEVCNTR1_EL0(9), 2071 AMU_AMEVCNTR1_EL0(10), 2072 AMU_AMEVCNTR1_EL0(11), 2073 AMU_AMEVCNTR1_EL0(12), 2074 AMU_AMEVCNTR1_EL0(13), 2075 AMU_AMEVCNTR1_EL0(14), 2076 AMU_AMEVCNTR1_EL0(15), 2077 AMU_AMEVTYPER1_EL0(0), 2078 AMU_AMEVTYPER1_EL0(1), 2079 AMU_AMEVTYPER1_EL0(2), 2080 AMU_AMEVTYPER1_EL0(3), 2081 AMU_AMEVTYPER1_EL0(4), 2082 AMU_AMEVTYPER1_EL0(5), 2083 AMU_AMEVTYPER1_EL0(6), 2084 AMU_AMEVTYPER1_EL0(7), 2085 AMU_AMEVTYPER1_EL0(8), 2086 AMU_AMEVTYPER1_EL0(9), 2087 AMU_AMEVTYPER1_EL0(10), 2088 AMU_AMEVTYPER1_EL0(11), 2089 AMU_AMEVTYPER1_EL0(12), 2090 AMU_AMEVTYPER1_EL0(13), 2091 AMU_AMEVTYPER1_EL0(14), 2092 AMU_AMEVTYPER1_EL0(15), 2093 2094 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2095 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2096 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2097 2098 /* PMEVCNTRn_EL0 */ 2099 PMU_PMEVCNTR_EL0(0), 2100 PMU_PMEVCNTR_EL0(1), 2101 PMU_PMEVCNTR_EL0(2), 2102 PMU_PMEVCNTR_EL0(3), 2103 PMU_PMEVCNTR_EL0(4), 2104 PMU_PMEVCNTR_EL0(5), 2105 PMU_PMEVCNTR_EL0(6), 2106 PMU_PMEVCNTR_EL0(7), 2107 PMU_PMEVCNTR_EL0(8), 2108 PMU_PMEVCNTR_EL0(9), 2109 PMU_PMEVCNTR_EL0(10), 2110 PMU_PMEVCNTR_EL0(11), 2111 PMU_PMEVCNTR_EL0(12), 2112 PMU_PMEVCNTR_EL0(13), 2113 PMU_PMEVCNTR_EL0(14), 2114 PMU_PMEVCNTR_EL0(15), 2115 PMU_PMEVCNTR_EL0(16), 2116 PMU_PMEVCNTR_EL0(17), 2117 PMU_PMEVCNTR_EL0(18), 2118 PMU_PMEVCNTR_EL0(19), 2119 PMU_PMEVCNTR_EL0(20), 2120 PMU_PMEVCNTR_EL0(21), 2121 PMU_PMEVCNTR_EL0(22), 2122 PMU_PMEVCNTR_EL0(23), 2123 PMU_PMEVCNTR_EL0(24), 2124 PMU_PMEVCNTR_EL0(25), 2125 PMU_PMEVCNTR_EL0(26), 2126 PMU_PMEVCNTR_EL0(27), 2127 PMU_PMEVCNTR_EL0(28), 2128 PMU_PMEVCNTR_EL0(29), 2129 PMU_PMEVCNTR_EL0(30), 2130 /* PMEVTYPERn_EL0 */ 2131 PMU_PMEVTYPER_EL0(0), 2132 PMU_PMEVTYPER_EL0(1), 2133 PMU_PMEVTYPER_EL0(2), 2134 PMU_PMEVTYPER_EL0(3), 2135 PMU_PMEVTYPER_EL0(4), 2136 PMU_PMEVTYPER_EL0(5), 2137 PMU_PMEVTYPER_EL0(6), 2138 PMU_PMEVTYPER_EL0(7), 2139 PMU_PMEVTYPER_EL0(8), 2140 PMU_PMEVTYPER_EL0(9), 2141 PMU_PMEVTYPER_EL0(10), 2142 PMU_PMEVTYPER_EL0(11), 2143 PMU_PMEVTYPER_EL0(12), 2144 PMU_PMEVTYPER_EL0(13), 2145 PMU_PMEVTYPER_EL0(14), 2146 PMU_PMEVTYPER_EL0(15), 2147 PMU_PMEVTYPER_EL0(16), 2148 PMU_PMEVTYPER_EL0(17), 2149 PMU_PMEVTYPER_EL0(18), 2150 PMU_PMEVTYPER_EL0(19), 2151 PMU_PMEVTYPER_EL0(20), 2152 PMU_PMEVTYPER_EL0(21), 2153 PMU_PMEVTYPER_EL0(22), 2154 PMU_PMEVTYPER_EL0(23), 2155 PMU_PMEVTYPER_EL0(24), 2156 PMU_PMEVTYPER_EL0(25), 2157 PMU_PMEVTYPER_EL0(26), 2158 PMU_PMEVTYPER_EL0(27), 2159 PMU_PMEVTYPER_EL0(28), 2160 PMU_PMEVTYPER_EL0(29), 2161 PMU_PMEVTYPER_EL0(30), 2162 /* 2163 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2164 * in 32bit mode. Here we choose to reset it as zero for consistency. 2165 */ 2166 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper, 2167 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2168 2169 EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0), 2170 EL2_REG(VMPIDR_EL2, access_rw, reset_unknown, 0), 2171 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 2172 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 2173 EL2_REG(HCR_EL2, access_rw, reset_val, 0), 2174 EL2_REG(MDCR_EL2, access_rw, reset_val, 0), 2175 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_EL2_DEFAULT ), 2176 EL2_REG(HSTR_EL2, access_rw, reset_val, 0), 2177 EL2_REG(HACR_EL2, access_rw, reset_val, 0), 2178 2179 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 2180 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 2181 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 2182 EL2_REG(VTTBR_EL2, access_rw, reset_val, 0), 2183 EL2_REG(VTCR_EL2, access_rw, reset_val, 0), 2184 2185 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 2186 EL2_REG(SPSR_EL2, access_rw, reset_val, 0), 2187 EL2_REG(ELR_EL2, access_rw, reset_val, 0), 2188 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 2189 2190 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 2191 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 2192 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 2193 EL2_REG(ESR_EL2, access_rw, reset_val, 0), 2194 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 2195 2196 EL2_REG(FAR_EL2, access_rw, reset_val, 0), 2197 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 2198 2199 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 2200 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 2201 2202 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 2203 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 2204 { SYS_DESC(SYS_RMR_EL2), trap_undef }, 2205 2206 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 2207 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 2208 2209 EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0), 2210 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 2211 2212 EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078), 2213 EL12_REG(CPACR, access_rw, reset_val, 0), 2214 EL12_REG(TTBR0, access_vm_reg, reset_unknown, 0), 2215 EL12_REG(TTBR1, access_vm_reg, reset_unknown, 0), 2216 EL12_REG(TCR, access_vm_reg, reset_val, 0), 2217 { SYS_DESC(SYS_SPSR_EL12), access_spsr}, 2218 { SYS_DESC(SYS_ELR_EL12), access_elr}, 2219 EL12_REG(AFSR0, access_vm_reg, reset_unknown, 0), 2220 EL12_REG(AFSR1, access_vm_reg, reset_unknown, 0), 2221 EL12_REG(ESR, access_vm_reg, reset_unknown, 0), 2222 EL12_REG(FAR, access_vm_reg, reset_unknown, 0), 2223 EL12_REG(MAIR, access_vm_reg, reset_unknown, 0), 2224 EL12_REG(AMAIR, access_vm_reg, reset_amair_el1, 0), 2225 EL12_REG(VBAR, access_rw, reset_val, 0), 2226 EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0), 2227 EL12_REG(CNTKCTL, access_rw, reset_val, 0), 2228 2229 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 2230 }; 2231 2232 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 2233 struct sys_reg_params *p, 2234 const struct sys_reg_desc *r) 2235 { 2236 if (p->is_write) { 2237 return ignore_write(vcpu, p); 2238 } else { 2239 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 2240 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2241 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); 2242 2243 p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | 2244 (((dfr >> ID_AA64DFR0_EL1_BRPs_SHIFT) & 0xf) << 24) | 2245 (((dfr >> ID_AA64DFR0_EL1_CTX_CMPs_SHIFT) & 0xf) << 20) 2246 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); 2247 return true; 2248 } 2249 } 2250 2251 /* 2252 * AArch32 debug register mappings 2253 * 2254 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 2255 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 2256 * 2257 * None of the other registers share their location, so treat them as 2258 * if they were 64bit. 2259 */ 2260 #define DBG_BCR_BVR_WCR_WVR(n) \ 2261 /* DBGBVRn */ \ 2262 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 2263 /* DBGBCRn */ \ 2264 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 2265 /* DBGWVRn */ \ 2266 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 2267 /* DBGWCRn */ \ 2268 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 2269 2270 #define DBGBXVR(n) \ 2271 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 2272 2273 /* 2274 * Trapped cp14 registers. We generally ignore most of the external 2275 * debug, on the principle that they don't really make sense to a 2276 * guest. Revisit this one day, would this principle change. 2277 */ 2278 static const struct sys_reg_desc cp14_regs[] = { 2279 /* DBGDIDR */ 2280 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 2281 /* DBGDTRRXext */ 2282 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 2283 2284 DBG_BCR_BVR_WCR_WVR(0), 2285 /* DBGDSCRint */ 2286 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 2287 DBG_BCR_BVR_WCR_WVR(1), 2288 /* DBGDCCINT */ 2289 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 2290 /* DBGDSCRext */ 2291 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 2292 DBG_BCR_BVR_WCR_WVR(2), 2293 /* DBGDTR[RT]Xint */ 2294 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 2295 /* DBGDTR[RT]Xext */ 2296 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 2297 DBG_BCR_BVR_WCR_WVR(3), 2298 DBG_BCR_BVR_WCR_WVR(4), 2299 DBG_BCR_BVR_WCR_WVR(5), 2300 /* DBGWFAR */ 2301 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 2302 /* DBGOSECCR */ 2303 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 2304 DBG_BCR_BVR_WCR_WVR(6), 2305 /* DBGVCR */ 2306 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 2307 DBG_BCR_BVR_WCR_WVR(7), 2308 DBG_BCR_BVR_WCR_WVR(8), 2309 DBG_BCR_BVR_WCR_WVR(9), 2310 DBG_BCR_BVR_WCR_WVR(10), 2311 DBG_BCR_BVR_WCR_WVR(11), 2312 DBG_BCR_BVR_WCR_WVR(12), 2313 DBG_BCR_BVR_WCR_WVR(13), 2314 DBG_BCR_BVR_WCR_WVR(14), 2315 DBG_BCR_BVR_WCR_WVR(15), 2316 2317 /* DBGDRAR (32bit) */ 2318 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 2319 2320 DBGBXVR(0), 2321 /* DBGOSLAR */ 2322 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 2323 DBGBXVR(1), 2324 /* DBGOSLSR */ 2325 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 2326 DBGBXVR(2), 2327 DBGBXVR(3), 2328 /* DBGOSDLR */ 2329 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 2330 DBGBXVR(4), 2331 /* DBGPRCR */ 2332 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 2333 DBGBXVR(5), 2334 DBGBXVR(6), 2335 DBGBXVR(7), 2336 DBGBXVR(8), 2337 DBGBXVR(9), 2338 DBGBXVR(10), 2339 DBGBXVR(11), 2340 DBGBXVR(12), 2341 DBGBXVR(13), 2342 DBGBXVR(14), 2343 DBGBXVR(15), 2344 2345 /* DBGDSAR (32bit) */ 2346 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 2347 2348 /* DBGDEVID2 */ 2349 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 2350 /* DBGDEVID1 */ 2351 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 2352 /* DBGDEVID */ 2353 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 2354 /* DBGCLAIMSET */ 2355 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 2356 /* DBGCLAIMCLR */ 2357 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 2358 /* DBGAUTHSTATUS */ 2359 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 2360 }; 2361 2362 /* Trapped cp14 64bit registers */ 2363 static const struct sys_reg_desc cp14_64_regs[] = { 2364 /* DBGDRAR (64bit) */ 2365 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 2366 2367 /* DBGDSAR (64bit) */ 2368 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 2369 }; 2370 2371 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 2372 AA32(_map), \ 2373 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 2374 .visibility = pmu_visibility 2375 2376 /* Macro to expand the PMEVCNTRn register */ 2377 #define PMU_PMEVCNTR(n) \ 2378 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 2379 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 2380 .access = access_pmu_evcntr } 2381 2382 /* Macro to expand the PMEVTYPERn register */ 2383 #define PMU_PMEVTYPER(n) \ 2384 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 2385 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 2386 .access = access_pmu_evtyper } 2387 /* 2388 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 2389 * depending on the way they are accessed (as a 32bit or a 64bit 2390 * register). 2391 */ 2392 static const struct sys_reg_desc cp15_regs[] = { 2393 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 2394 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 2395 /* ACTLR */ 2396 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 2397 /* ACTLR2 */ 2398 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 2399 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2400 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 2401 /* TTBCR */ 2402 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 2403 /* TTBCR2 */ 2404 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 2405 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 2406 /* DFSR */ 2407 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 2408 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 2409 /* ADFSR */ 2410 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 2411 /* AIFSR */ 2412 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 2413 /* DFAR */ 2414 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 2415 /* IFAR */ 2416 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 2417 2418 /* 2419 * DC{C,I,CI}SW operations: 2420 */ 2421 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 2422 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 2423 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 2424 2425 /* PMU */ 2426 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 2427 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 2428 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 2429 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 2430 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 2431 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 2432 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 2433 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 2434 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 2435 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 2436 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 2437 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 2438 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 2439 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 2440 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 2441 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 2442 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 2443 /* PMMIR */ 2444 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 2445 2446 /* PRRR/MAIR0 */ 2447 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 2448 /* NMRR/MAIR1 */ 2449 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 2450 /* AMAIR0 */ 2451 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 2452 /* AMAIR1 */ 2453 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 2454 2455 /* ICC_SRE */ 2456 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 2457 2458 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 2459 2460 /* Arch Tmers */ 2461 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 2462 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 2463 2464 /* PMEVCNTRn */ 2465 PMU_PMEVCNTR(0), 2466 PMU_PMEVCNTR(1), 2467 PMU_PMEVCNTR(2), 2468 PMU_PMEVCNTR(3), 2469 PMU_PMEVCNTR(4), 2470 PMU_PMEVCNTR(5), 2471 PMU_PMEVCNTR(6), 2472 PMU_PMEVCNTR(7), 2473 PMU_PMEVCNTR(8), 2474 PMU_PMEVCNTR(9), 2475 PMU_PMEVCNTR(10), 2476 PMU_PMEVCNTR(11), 2477 PMU_PMEVCNTR(12), 2478 PMU_PMEVCNTR(13), 2479 PMU_PMEVCNTR(14), 2480 PMU_PMEVCNTR(15), 2481 PMU_PMEVCNTR(16), 2482 PMU_PMEVCNTR(17), 2483 PMU_PMEVCNTR(18), 2484 PMU_PMEVCNTR(19), 2485 PMU_PMEVCNTR(20), 2486 PMU_PMEVCNTR(21), 2487 PMU_PMEVCNTR(22), 2488 PMU_PMEVCNTR(23), 2489 PMU_PMEVCNTR(24), 2490 PMU_PMEVCNTR(25), 2491 PMU_PMEVCNTR(26), 2492 PMU_PMEVCNTR(27), 2493 PMU_PMEVCNTR(28), 2494 PMU_PMEVCNTR(29), 2495 PMU_PMEVCNTR(30), 2496 /* PMEVTYPERn */ 2497 PMU_PMEVTYPER(0), 2498 PMU_PMEVTYPER(1), 2499 PMU_PMEVTYPER(2), 2500 PMU_PMEVTYPER(3), 2501 PMU_PMEVTYPER(4), 2502 PMU_PMEVTYPER(5), 2503 PMU_PMEVTYPER(6), 2504 PMU_PMEVTYPER(7), 2505 PMU_PMEVTYPER(8), 2506 PMU_PMEVTYPER(9), 2507 PMU_PMEVTYPER(10), 2508 PMU_PMEVTYPER(11), 2509 PMU_PMEVTYPER(12), 2510 PMU_PMEVTYPER(13), 2511 PMU_PMEVTYPER(14), 2512 PMU_PMEVTYPER(15), 2513 PMU_PMEVTYPER(16), 2514 PMU_PMEVTYPER(17), 2515 PMU_PMEVTYPER(18), 2516 PMU_PMEVTYPER(19), 2517 PMU_PMEVTYPER(20), 2518 PMU_PMEVTYPER(21), 2519 PMU_PMEVTYPER(22), 2520 PMU_PMEVTYPER(23), 2521 PMU_PMEVTYPER(24), 2522 PMU_PMEVTYPER(25), 2523 PMU_PMEVTYPER(26), 2524 PMU_PMEVTYPER(27), 2525 PMU_PMEVTYPER(28), 2526 PMU_PMEVTYPER(29), 2527 PMU_PMEVTYPER(30), 2528 /* PMCCFILTR */ 2529 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 2530 2531 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2532 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2533 2534 /* CCSIDR2 */ 2535 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 2536 2537 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 2538 }; 2539 2540 static const struct sys_reg_desc cp15_64_regs[] = { 2541 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2542 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 2543 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2544 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 2545 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2546 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2547 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2548 }; 2549 2550 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2551 bool is_32) 2552 { 2553 unsigned int i; 2554 2555 for (i = 0; i < n; i++) { 2556 if (!is_32 && table[i].reg && !table[i].reset) { 2557 kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i); 2558 return false; 2559 } 2560 2561 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2562 kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1); 2563 return false; 2564 } 2565 } 2566 2567 return true; 2568 } 2569 2570 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2571 { 2572 kvm_inject_undefined(vcpu); 2573 return 1; 2574 } 2575 2576 static void perform_access(struct kvm_vcpu *vcpu, 2577 struct sys_reg_params *params, 2578 const struct sys_reg_desc *r) 2579 { 2580 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2581 2582 /* Check for regs disabled by runtime config */ 2583 if (sysreg_hidden(vcpu, r)) { 2584 kvm_inject_undefined(vcpu); 2585 return; 2586 } 2587 2588 /* 2589 * Not having an accessor means that we have configured a trap 2590 * that we don't know how to handle. This certainly qualifies 2591 * as a gross bug that should be fixed right away. 2592 */ 2593 BUG_ON(!r->access); 2594 2595 /* Skip instruction if instructed so */ 2596 if (likely(r->access(vcpu, params, r))) 2597 kvm_incr_pc(vcpu); 2598 } 2599 2600 /* 2601 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2602 * call the corresponding trap handler. 2603 * 2604 * @params: pointer to the descriptor of the access 2605 * @table: array of trap descriptors 2606 * @num: size of the trap descriptor array 2607 * 2608 * Return true if the access has been handled, false if not. 2609 */ 2610 static bool emulate_cp(struct kvm_vcpu *vcpu, 2611 struct sys_reg_params *params, 2612 const struct sys_reg_desc *table, 2613 size_t num) 2614 { 2615 const struct sys_reg_desc *r; 2616 2617 if (!table) 2618 return false; /* Not handled */ 2619 2620 r = find_reg(params, table, num); 2621 2622 if (r) { 2623 perform_access(vcpu, params, r); 2624 return true; 2625 } 2626 2627 /* Not handled */ 2628 return false; 2629 } 2630 2631 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2632 struct sys_reg_params *params) 2633 { 2634 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2635 int cp = -1; 2636 2637 switch (esr_ec) { 2638 case ESR_ELx_EC_CP15_32: 2639 case ESR_ELx_EC_CP15_64: 2640 cp = 15; 2641 break; 2642 case ESR_ELx_EC_CP14_MR: 2643 case ESR_ELx_EC_CP14_64: 2644 cp = 14; 2645 break; 2646 default: 2647 WARN_ON(1); 2648 } 2649 2650 print_sys_reg_msg(params, 2651 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2652 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2653 kvm_inject_undefined(vcpu); 2654 } 2655 2656 /** 2657 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2658 * @vcpu: The VCPU pointer 2659 * @run: The kvm_run struct 2660 */ 2661 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2662 const struct sys_reg_desc *global, 2663 size_t nr_global) 2664 { 2665 struct sys_reg_params params; 2666 u64 esr = kvm_vcpu_get_esr(vcpu); 2667 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2668 int Rt2 = (esr >> 10) & 0x1f; 2669 2670 params.CRm = (esr >> 1) & 0xf; 2671 params.is_write = ((esr & 1) == 0); 2672 2673 params.Op0 = 0; 2674 params.Op1 = (esr >> 16) & 0xf; 2675 params.Op2 = 0; 2676 params.CRn = 0; 2677 2678 /* 2679 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2680 * backends between AArch32 and AArch64, we get away with it. 2681 */ 2682 if (params.is_write) { 2683 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2684 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2685 } 2686 2687 /* 2688 * If the table contains a handler, handle the 2689 * potential register operation in the case of a read and return 2690 * with success. 2691 */ 2692 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 2693 /* Split up the value between registers for the read side */ 2694 if (!params.is_write) { 2695 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2696 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2697 } 2698 2699 return 1; 2700 } 2701 2702 unhandled_cp_access(vcpu, ¶ms); 2703 return 1; 2704 } 2705 2706 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 2707 2708 /* 2709 * The CP10 ID registers are architecturally mapped to AArch64 feature 2710 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 2711 * from AArch32. 2712 */ 2713 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 2714 { 2715 u8 reg_id = (esr >> 10) & 0xf; 2716 bool valid; 2717 2718 params->is_write = ((esr & 1) == 0); 2719 params->Op0 = 3; 2720 params->Op1 = 0; 2721 params->CRn = 0; 2722 params->CRm = 3; 2723 2724 /* CP10 ID registers are read-only */ 2725 valid = !params->is_write; 2726 2727 switch (reg_id) { 2728 /* MVFR0 */ 2729 case 0b0111: 2730 params->Op2 = 0; 2731 break; 2732 /* MVFR1 */ 2733 case 0b0110: 2734 params->Op2 = 1; 2735 break; 2736 /* MVFR2 */ 2737 case 0b0101: 2738 params->Op2 = 2; 2739 break; 2740 default: 2741 valid = false; 2742 } 2743 2744 if (valid) 2745 return true; 2746 2747 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 2748 params->is_write ? "write" : "read", reg_id); 2749 return false; 2750 } 2751 2752 /** 2753 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 2754 * VFP Register' from AArch32. 2755 * @vcpu: The vCPU pointer 2756 * 2757 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 2758 * Work out the correct AArch64 system register encoding and reroute to the 2759 * AArch64 system register emulation. 2760 */ 2761 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 2762 { 2763 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2764 u64 esr = kvm_vcpu_get_esr(vcpu); 2765 struct sys_reg_params params; 2766 2767 /* UNDEF on any unhandled register access */ 2768 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 2769 kvm_inject_undefined(vcpu); 2770 return 1; 2771 } 2772 2773 if (emulate_sys_reg(vcpu, ¶ms)) 2774 vcpu_set_reg(vcpu, Rt, params.regval); 2775 2776 return 1; 2777 } 2778 2779 /** 2780 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 2781 * CRn=0, which corresponds to the AArch32 feature 2782 * registers. 2783 * @vcpu: the vCPU pointer 2784 * @params: the system register access parameters. 2785 * 2786 * Our cp15 system register tables do not enumerate the AArch32 feature 2787 * registers. Conveniently, our AArch64 table does, and the AArch32 system 2788 * register encoding can be trivially remapped into the AArch64 for the feature 2789 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 2790 * 2791 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 2792 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 2793 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 2794 * treat undefined registers in this range as RAZ. 2795 */ 2796 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 2797 struct sys_reg_params *params) 2798 { 2799 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2800 2801 /* Treat impossible writes to RO registers as UNDEFINED */ 2802 if (params->is_write) { 2803 unhandled_cp_access(vcpu, params); 2804 return 1; 2805 } 2806 2807 params->Op0 = 3; 2808 2809 /* 2810 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 2811 * Avoid conflicting with future expansion of AArch64 feature registers 2812 * and simply treat them as RAZ here. 2813 */ 2814 if (params->CRm > 3) 2815 params->regval = 0; 2816 else if (!emulate_sys_reg(vcpu, params)) 2817 return 1; 2818 2819 vcpu_set_reg(vcpu, Rt, params->regval); 2820 return 1; 2821 } 2822 2823 /** 2824 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2825 * @vcpu: The VCPU pointer 2826 * @run: The kvm_run struct 2827 */ 2828 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2829 struct sys_reg_params *params, 2830 const struct sys_reg_desc *global, 2831 size_t nr_global) 2832 { 2833 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2834 2835 params->regval = vcpu_get_reg(vcpu, Rt); 2836 2837 if (emulate_cp(vcpu, params, global, nr_global)) { 2838 if (!params->is_write) 2839 vcpu_set_reg(vcpu, Rt, params->regval); 2840 return 1; 2841 } 2842 2843 unhandled_cp_access(vcpu, params); 2844 return 1; 2845 } 2846 2847 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2848 { 2849 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2850 } 2851 2852 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2853 { 2854 struct sys_reg_params params; 2855 2856 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 2857 2858 /* 2859 * Certain AArch32 ID registers are handled by rerouting to the AArch64 2860 * system register table. Registers in the ID range where CRm=0 are 2861 * excluded from this scheme as they do not trivially map into AArch64 2862 * system register encodings. 2863 */ 2864 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 2865 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 2866 2867 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 2868 } 2869 2870 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2871 { 2872 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2873 } 2874 2875 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2876 { 2877 struct sys_reg_params params; 2878 2879 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 2880 2881 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 2882 } 2883 2884 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2885 { 2886 // See ARM DDI 0487E.a, section D12.3.2 2887 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2888 } 2889 2890 /** 2891 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 2892 * @vcpu: The VCPU pointer 2893 * @params: Decoded system register parameters 2894 * 2895 * Return: true if the system register access was successful, false otherwise. 2896 */ 2897 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 2898 struct sys_reg_params *params) 2899 { 2900 const struct sys_reg_desc *r; 2901 2902 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2903 2904 if (likely(r)) { 2905 perform_access(vcpu, params, r); 2906 return true; 2907 } 2908 2909 if (is_imp_def_sys_reg(params)) { 2910 kvm_inject_undefined(vcpu); 2911 } else { 2912 print_sys_reg_msg(params, 2913 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2914 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2915 kvm_inject_undefined(vcpu); 2916 } 2917 return false; 2918 } 2919 2920 /** 2921 * kvm_reset_sys_regs - sets system registers to reset value 2922 * @vcpu: The VCPU pointer 2923 * 2924 * This function finds the right table above and sets the registers on the 2925 * virtual CPU struct to their architecturally defined reset values. 2926 */ 2927 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2928 { 2929 unsigned long i; 2930 2931 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2932 if (sys_reg_descs[i].reset) 2933 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2934 } 2935 2936 /** 2937 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2938 * @vcpu: The VCPU pointer 2939 */ 2940 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2941 { 2942 struct sys_reg_params params; 2943 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2944 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2945 2946 trace_kvm_handle_sys_reg(esr); 2947 2948 params = esr_sys64_to_params(esr); 2949 params.regval = vcpu_get_reg(vcpu, Rt); 2950 2951 if (!emulate_sys_reg(vcpu, ¶ms)) 2952 return 1; 2953 2954 if (!params.is_write) 2955 vcpu_set_reg(vcpu, Rt, params.regval); 2956 return 1; 2957 } 2958 2959 /****************************************************************************** 2960 * Userspace API 2961 *****************************************************************************/ 2962 2963 static bool index_to_params(u64 id, struct sys_reg_params *params) 2964 { 2965 switch (id & KVM_REG_SIZE_MASK) { 2966 case KVM_REG_SIZE_U64: 2967 /* Any unused index bits means it's not valid. */ 2968 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2969 | KVM_REG_ARM_COPROC_MASK 2970 | KVM_REG_ARM64_SYSREG_OP0_MASK 2971 | KVM_REG_ARM64_SYSREG_OP1_MASK 2972 | KVM_REG_ARM64_SYSREG_CRN_MASK 2973 | KVM_REG_ARM64_SYSREG_CRM_MASK 2974 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2975 return false; 2976 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2977 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2978 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2979 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2980 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2981 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2982 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2983 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2984 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2985 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2986 return true; 2987 default: 2988 return false; 2989 } 2990 } 2991 2992 const struct sys_reg_desc *get_reg_by_id(u64 id, 2993 const struct sys_reg_desc table[], 2994 unsigned int num) 2995 { 2996 struct sys_reg_params params; 2997 2998 if (!index_to_params(id, ¶ms)) 2999 return NULL; 3000 3001 return find_reg(¶ms, table, num); 3002 } 3003 3004 /* Decode an index value, and find the sys_reg_desc entry. */ 3005 static const struct sys_reg_desc * 3006 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 3007 const struct sys_reg_desc table[], unsigned int num) 3008 3009 { 3010 const struct sys_reg_desc *r; 3011 3012 /* We only do sys_reg for now. */ 3013 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 3014 return NULL; 3015 3016 r = get_reg_by_id(id, table, num); 3017 3018 /* Not saved in the sys_reg array and not otherwise accessible? */ 3019 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 3020 r = NULL; 3021 3022 return r; 3023 } 3024 3025 /* 3026 * These are the invariant sys_reg registers: we let the guest see the 3027 * host versions of these, so they're part of the guest state. 3028 * 3029 * A future CPU may provide a mechanism to present different values to 3030 * the guest, or a future kvm may trap them. 3031 */ 3032 3033 #define FUNCTION_INVARIANT(reg) \ 3034 static void get_##reg(struct kvm_vcpu *v, \ 3035 const struct sys_reg_desc *r) \ 3036 { \ 3037 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 3038 } 3039 3040 FUNCTION_INVARIANT(midr_el1) 3041 FUNCTION_INVARIANT(revidr_el1) 3042 FUNCTION_INVARIANT(aidr_el1) 3043 3044 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 3045 { 3046 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 3047 } 3048 3049 /* ->val is filled in by kvm_sys_reg_table_init() */ 3050 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 3051 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 3052 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 3053 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 3054 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 3055 }; 3056 3057 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 3058 { 3059 const struct sys_reg_desc *r; 3060 3061 r = get_reg_by_id(id, invariant_sys_regs, 3062 ARRAY_SIZE(invariant_sys_regs)); 3063 if (!r) 3064 return -ENOENT; 3065 3066 return put_user(r->val, uaddr); 3067 } 3068 3069 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 3070 { 3071 const struct sys_reg_desc *r; 3072 u64 val; 3073 3074 r = get_reg_by_id(id, invariant_sys_regs, 3075 ARRAY_SIZE(invariant_sys_regs)); 3076 if (!r) 3077 return -ENOENT; 3078 3079 if (get_user(val, uaddr)) 3080 return -EFAULT; 3081 3082 /* This is what we mean by invariant: you can't change it. */ 3083 if (r->val != val) 3084 return -EINVAL; 3085 3086 return 0; 3087 } 3088 3089 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 3090 { 3091 u32 val; 3092 u32 __user *uval = uaddr; 3093 3094 /* Fail if we have unknown bits set. */ 3095 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 3096 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 3097 return -ENOENT; 3098 3099 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 3100 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 3101 if (KVM_REG_SIZE(id) != 4) 3102 return -ENOENT; 3103 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 3104 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 3105 if (val >= CSSELR_MAX) 3106 return -ENOENT; 3107 3108 return put_user(get_ccsidr(vcpu, val), uval); 3109 default: 3110 return -ENOENT; 3111 } 3112 } 3113 3114 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 3115 { 3116 u32 val, newval; 3117 u32 __user *uval = uaddr; 3118 3119 /* Fail if we have unknown bits set. */ 3120 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 3121 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 3122 return -ENOENT; 3123 3124 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 3125 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 3126 if (KVM_REG_SIZE(id) != 4) 3127 return -ENOENT; 3128 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 3129 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 3130 if (val >= CSSELR_MAX) 3131 return -ENOENT; 3132 3133 if (get_user(newval, uval)) 3134 return -EFAULT; 3135 3136 return set_ccsidr(vcpu, val, newval); 3137 default: 3138 return -ENOENT; 3139 } 3140 } 3141 3142 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 3143 const struct sys_reg_desc table[], unsigned int num) 3144 { 3145 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 3146 const struct sys_reg_desc *r; 3147 u64 val; 3148 int ret; 3149 3150 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 3151 if (!r || sysreg_hidden_user(vcpu, r)) 3152 return -ENOENT; 3153 3154 if (r->get_user) { 3155 ret = (r->get_user)(vcpu, r, &val); 3156 } else { 3157 val = __vcpu_sys_reg(vcpu, r->reg); 3158 ret = 0; 3159 } 3160 3161 if (!ret) 3162 ret = put_user(val, uaddr); 3163 3164 return ret; 3165 } 3166 3167 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 3168 { 3169 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 3170 int err; 3171 3172 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 3173 return demux_c15_get(vcpu, reg->id, uaddr); 3174 3175 err = get_invariant_sys_reg(reg->id, uaddr); 3176 if (err != -ENOENT) 3177 return err; 3178 3179 return kvm_sys_reg_get_user(vcpu, reg, 3180 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3181 } 3182 3183 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 3184 const struct sys_reg_desc table[], unsigned int num) 3185 { 3186 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 3187 const struct sys_reg_desc *r; 3188 u64 val; 3189 int ret; 3190 3191 if (get_user(val, uaddr)) 3192 return -EFAULT; 3193 3194 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 3195 if (!r || sysreg_hidden_user(vcpu, r)) 3196 return -ENOENT; 3197 3198 if (sysreg_user_write_ignore(vcpu, r)) 3199 return 0; 3200 3201 if (r->set_user) { 3202 ret = (r->set_user)(vcpu, r, val); 3203 } else { 3204 __vcpu_sys_reg(vcpu, r->reg) = val; 3205 ret = 0; 3206 } 3207 3208 return ret; 3209 } 3210 3211 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 3212 { 3213 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 3214 int err; 3215 3216 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 3217 return demux_c15_set(vcpu, reg->id, uaddr); 3218 3219 err = set_invariant_sys_reg(reg->id, uaddr); 3220 if (err != -ENOENT) 3221 return err; 3222 3223 return kvm_sys_reg_set_user(vcpu, reg, 3224 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3225 } 3226 3227 static unsigned int num_demux_regs(void) 3228 { 3229 return CSSELR_MAX; 3230 } 3231 3232 static int write_demux_regids(u64 __user *uindices) 3233 { 3234 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 3235 unsigned int i; 3236 3237 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 3238 for (i = 0; i < CSSELR_MAX; i++) { 3239 if (put_user(val | i, uindices)) 3240 return -EFAULT; 3241 uindices++; 3242 } 3243 return 0; 3244 } 3245 3246 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 3247 { 3248 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 3249 KVM_REG_ARM64_SYSREG | 3250 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 3251 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 3252 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 3253 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 3254 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 3255 } 3256 3257 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 3258 { 3259 if (!*uind) 3260 return true; 3261 3262 if (put_user(sys_reg_to_index(reg), *uind)) 3263 return false; 3264 3265 (*uind)++; 3266 return true; 3267 } 3268 3269 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 3270 const struct sys_reg_desc *rd, 3271 u64 __user **uind, 3272 unsigned int *total) 3273 { 3274 /* 3275 * Ignore registers we trap but don't save, 3276 * and for which no custom user accessor is provided. 3277 */ 3278 if (!(rd->reg || rd->get_user)) 3279 return 0; 3280 3281 if (sysreg_hidden_user(vcpu, rd)) 3282 return 0; 3283 3284 if (!copy_reg_to_user(rd, uind)) 3285 return -EFAULT; 3286 3287 (*total)++; 3288 return 0; 3289 } 3290 3291 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 3292 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 3293 { 3294 const struct sys_reg_desc *i2, *end2; 3295 unsigned int total = 0; 3296 int err; 3297 3298 i2 = sys_reg_descs; 3299 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 3300 3301 while (i2 != end2) { 3302 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 3303 if (err) 3304 return err; 3305 } 3306 return total; 3307 } 3308 3309 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 3310 { 3311 return ARRAY_SIZE(invariant_sys_regs) 3312 + num_demux_regs() 3313 + walk_sys_regs(vcpu, (u64 __user *)NULL); 3314 } 3315 3316 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 3317 { 3318 unsigned int i; 3319 int err; 3320 3321 /* Then give them all the invariant registers' indices. */ 3322 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 3323 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 3324 return -EFAULT; 3325 uindices++; 3326 } 3327 3328 err = walk_sys_regs(vcpu, uindices); 3329 if (err < 0) 3330 return err; 3331 uindices += err; 3332 3333 return write_demux_regids(uindices); 3334 } 3335 3336 int __init kvm_sys_reg_table_init(void) 3337 { 3338 bool valid = true; 3339 unsigned int i; 3340 3341 /* Make sure tables are unique and in order. */ 3342 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 3343 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 3344 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 3345 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 3346 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 3347 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 3348 3349 if (!valid) 3350 return -EINVAL; 3351 3352 /* We abuse the reset function to overwrite the table itself. */ 3353 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 3354 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 3355 3356 return 0; 3357 } 3358