1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/kvm_host.h> 16 #include <linux/mm.h> 17 #include <linux/printk.h> 18 #include <linux/uaccess.h> 19 20 #include <asm/cacheflush.h> 21 #include <asm/cputype.h> 22 #include <asm/debug-monitors.h> 23 #include <asm/esr.h> 24 #include <asm/kvm_arm.h> 25 #include <asm/kvm_emulate.h> 26 #include <asm/kvm_hyp.h> 27 #include <asm/kvm_mmu.h> 28 #include <asm/kvm_nested.h> 29 #include <asm/perf_event.h> 30 #include <asm/sysreg.h> 31 32 #include <trace/events/kvm.h> 33 34 #include "sys_regs.h" 35 36 #include "trace.h" 37 38 /* 39 * For AArch32, we only take care of what is being trapped. Anything 40 * that has to do with init and userspace access has to go via the 41 * 64bit interface. 42 */ 43 44 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 45 46 static bool read_from_write_only(struct kvm_vcpu *vcpu, 47 struct sys_reg_params *params, 48 const struct sys_reg_desc *r) 49 { 50 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 51 print_sys_reg_instr(params); 52 kvm_inject_undefined(vcpu); 53 return false; 54 } 55 56 static bool write_to_read_only(struct kvm_vcpu *vcpu, 57 struct sys_reg_params *params, 58 const struct sys_reg_desc *r) 59 { 60 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 61 print_sys_reg_instr(params); 62 kvm_inject_undefined(vcpu); 63 return false; 64 } 65 66 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 67 { 68 u64 val = 0x8badf00d8badf00d; 69 70 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 71 __vcpu_read_sys_reg_from_cpu(reg, &val)) 72 return val; 73 74 return __vcpu_sys_reg(vcpu, reg); 75 } 76 77 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 78 { 79 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 80 __vcpu_write_sys_reg_to_cpu(val, reg)) 81 return; 82 83 __vcpu_sys_reg(vcpu, reg) = val; 84 } 85 86 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 87 #define CSSELR_MAX 14 88 89 /* 90 * Returns the minimum line size for the selected cache, expressed as 91 * Log2(bytes). 92 */ 93 static u8 get_min_cache_line_size(bool icache) 94 { 95 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 96 u8 field; 97 98 if (icache) 99 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 100 else 101 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 102 103 /* 104 * Cache line size is represented as Log2(words) in CTR_EL0. 105 * Log2(bytes) can be derived with the following: 106 * 107 * Log2(words) + 2 = Log2(bytes / 4) + 2 108 * = Log2(bytes) - 2 + 2 109 * = Log2(bytes) 110 */ 111 return field + 2; 112 } 113 114 /* Which cache CCSIDR represents depends on CSSELR value. */ 115 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 116 { 117 u8 line_size; 118 119 if (vcpu->arch.ccsidr) 120 return vcpu->arch.ccsidr[csselr]; 121 122 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 123 124 /* 125 * Fabricate a CCSIDR value as the overriding value does not exist. 126 * The real CCSIDR value will not be used as it can vary by the 127 * physical CPU which the vcpu currently resides in. 128 * 129 * The line size is determined with get_min_cache_line_size(), which 130 * should be valid for all CPUs even if they have different cache 131 * configuration. 132 * 133 * The associativity bits are cleared, meaning the geometry of all data 134 * and unified caches (which are guaranteed to be PIPT and thus 135 * non-aliasing) are 1 set and 1 way. 136 * Guests should not be doing cache operations by set/way at all, and 137 * for this reason, we trap them and attempt to infer the intent, so 138 * that we can flush the entire guest's address space at the appropriate 139 * time. The exposed geometry minimizes the number of the traps. 140 * [If guests should attempt to infer aliasing properties from the 141 * geometry (which is not permitted by the architecture), they would 142 * only do so for virtually indexed caches.] 143 * 144 * We don't check if the cache level exists as it is allowed to return 145 * an UNKNOWN value if not. 146 */ 147 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 148 } 149 150 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 151 { 152 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 153 u32 *ccsidr = vcpu->arch.ccsidr; 154 u32 i; 155 156 if ((val & CCSIDR_EL1_RES0) || 157 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 158 return -EINVAL; 159 160 if (!ccsidr) { 161 if (val == get_ccsidr(vcpu, csselr)) 162 return 0; 163 164 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 165 if (!ccsidr) 166 return -ENOMEM; 167 168 for (i = 0; i < CSSELR_MAX; i++) 169 ccsidr[i] = get_ccsidr(vcpu, i); 170 171 vcpu->arch.ccsidr = ccsidr; 172 } 173 174 ccsidr[csselr] = val; 175 176 return 0; 177 } 178 179 static bool access_rw(struct kvm_vcpu *vcpu, 180 struct sys_reg_params *p, 181 const struct sys_reg_desc *r) 182 { 183 if (p->is_write) 184 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 185 else 186 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 187 188 return true; 189 } 190 191 /* 192 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 193 */ 194 static bool access_dcsw(struct kvm_vcpu *vcpu, 195 struct sys_reg_params *p, 196 const struct sys_reg_desc *r) 197 { 198 if (!p->is_write) 199 return read_from_write_only(vcpu, p, r); 200 201 /* 202 * Only track S/W ops if we don't have FWB. It still indicates 203 * that the guest is a bit broken (S/W operations should only 204 * be done by firmware, knowing that there is only a single 205 * CPU left in the system, and certainly not from non-secure 206 * software). 207 */ 208 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 209 kvm_set_way_flush(vcpu); 210 211 return true; 212 } 213 214 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 215 { 216 switch (r->aarch32_map) { 217 case AA32_LO: 218 *mask = GENMASK_ULL(31, 0); 219 *shift = 0; 220 break; 221 case AA32_HI: 222 *mask = GENMASK_ULL(63, 32); 223 *shift = 32; 224 break; 225 default: 226 *mask = GENMASK_ULL(63, 0); 227 *shift = 0; 228 break; 229 } 230 } 231 232 /* 233 * Generic accessor for VM registers. Only called as long as HCR_TVM 234 * is set. If the guest enables the MMU, we stop trapping the VM 235 * sys_regs and leave it in complete control of the caches. 236 */ 237 static bool access_vm_reg(struct kvm_vcpu *vcpu, 238 struct sys_reg_params *p, 239 const struct sys_reg_desc *r) 240 { 241 bool was_enabled = vcpu_has_cache_enabled(vcpu); 242 u64 val, mask, shift; 243 244 BUG_ON(!p->is_write); 245 246 get_access_mask(r, &mask, &shift); 247 248 if (~mask) { 249 val = vcpu_read_sys_reg(vcpu, r->reg); 250 val &= ~mask; 251 } else { 252 val = 0; 253 } 254 255 val |= (p->regval & (mask >> shift)) << shift; 256 vcpu_write_sys_reg(vcpu, val, r->reg); 257 258 kvm_toggle_cache(vcpu, was_enabled); 259 return true; 260 } 261 262 static bool access_actlr(struct kvm_vcpu *vcpu, 263 struct sys_reg_params *p, 264 const struct sys_reg_desc *r) 265 { 266 u64 mask, shift; 267 268 if (p->is_write) 269 return ignore_write(vcpu, p); 270 271 get_access_mask(r, &mask, &shift); 272 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 273 274 return true; 275 } 276 277 /* 278 * Trap handler for the GICv3 SGI generation system register. 279 * Forward the request to the VGIC emulation. 280 * The cp15_64 code makes sure this automatically works 281 * for both AArch64 and AArch32 accesses. 282 */ 283 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 284 struct sys_reg_params *p, 285 const struct sys_reg_desc *r) 286 { 287 bool g1; 288 289 if (!p->is_write) 290 return read_from_write_only(vcpu, p, r); 291 292 /* 293 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 294 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 295 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 296 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 297 * group. 298 */ 299 if (p->Op0 == 0) { /* AArch32 */ 300 switch (p->Op1) { 301 default: /* Keep GCC quiet */ 302 case 0: /* ICC_SGI1R */ 303 g1 = true; 304 break; 305 case 1: /* ICC_ASGI1R */ 306 case 2: /* ICC_SGI0R */ 307 g1 = false; 308 break; 309 } 310 } else { /* AArch64 */ 311 switch (p->Op2) { 312 default: /* Keep GCC quiet */ 313 case 5: /* ICC_SGI1R_EL1 */ 314 g1 = true; 315 break; 316 case 6: /* ICC_ASGI1R_EL1 */ 317 case 7: /* ICC_SGI0R_EL1 */ 318 g1 = false; 319 break; 320 } 321 } 322 323 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 324 325 return true; 326 } 327 328 static bool access_gic_sre(struct kvm_vcpu *vcpu, 329 struct sys_reg_params *p, 330 const struct sys_reg_desc *r) 331 { 332 if (p->is_write) 333 return ignore_write(vcpu, p); 334 335 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 336 return true; 337 } 338 339 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 340 struct sys_reg_params *p, 341 const struct sys_reg_desc *r) 342 { 343 if (p->is_write) 344 return ignore_write(vcpu, p); 345 else 346 return read_zero(vcpu, p); 347 } 348 349 static bool trap_undef(struct kvm_vcpu *vcpu, 350 struct sys_reg_params *p, 351 const struct sys_reg_desc *r) 352 { 353 kvm_inject_undefined(vcpu); 354 return false; 355 } 356 357 /* 358 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 359 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 360 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 361 * treat it separately. 362 */ 363 static bool trap_loregion(struct kvm_vcpu *vcpu, 364 struct sys_reg_params *p, 365 const struct sys_reg_desc *r) 366 { 367 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 368 u32 sr = reg_to_encoding(r); 369 370 if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { 371 kvm_inject_undefined(vcpu); 372 return false; 373 } 374 375 if (p->is_write && sr == SYS_LORID_EL1) 376 return write_to_read_only(vcpu, p, r); 377 378 return trap_raz_wi(vcpu, p, r); 379 } 380 381 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 382 struct sys_reg_params *p, 383 const struct sys_reg_desc *r) 384 { 385 u64 oslsr; 386 387 if (!p->is_write) 388 return read_from_write_only(vcpu, p, r); 389 390 /* Forward the OSLK bit to OSLSR */ 391 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK; 392 if (p->regval & SYS_OSLAR_OSLK) 393 oslsr |= SYS_OSLSR_OSLK; 394 395 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 396 return true; 397 } 398 399 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 400 struct sys_reg_params *p, 401 const struct sys_reg_desc *r) 402 { 403 if (p->is_write) 404 return write_to_read_only(vcpu, p, r); 405 406 p->regval = __vcpu_sys_reg(vcpu, r->reg); 407 return true; 408 } 409 410 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 411 u64 val) 412 { 413 /* 414 * The only modifiable bit is the OSLK bit. Refuse the write if 415 * userspace attempts to change any other bit in the register. 416 */ 417 if ((val ^ rd->val) & ~SYS_OSLSR_OSLK) 418 return -EINVAL; 419 420 __vcpu_sys_reg(vcpu, rd->reg) = val; 421 return 0; 422 } 423 424 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 425 struct sys_reg_params *p, 426 const struct sys_reg_desc *r) 427 { 428 if (p->is_write) { 429 return ignore_write(vcpu, p); 430 } else { 431 p->regval = read_sysreg(dbgauthstatus_el1); 432 return true; 433 } 434 } 435 436 /* 437 * We want to avoid world-switching all the DBG registers all the 438 * time: 439 * 440 * - If we've touched any debug register, it is likely that we're 441 * going to touch more of them. It then makes sense to disable the 442 * traps and start doing the save/restore dance 443 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 444 * then mandatory to save/restore the registers, as the guest 445 * depends on them. 446 * 447 * For this, we use a DIRTY bit, indicating the guest has modified the 448 * debug registers, used as follow: 449 * 450 * On guest entry: 451 * - If the dirty bit is set (because we're coming back from trapping), 452 * disable the traps, save host registers, restore guest registers. 453 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 454 * set the dirty bit, disable the traps, save host registers, 455 * restore guest registers. 456 * - Otherwise, enable the traps 457 * 458 * On guest exit: 459 * - If the dirty bit is set, save guest registers, restore host 460 * registers and clear the dirty bit. This ensure that the host can 461 * now use the debug registers. 462 */ 463 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 464 struct sys_reg_params *p, 465 const struct sys_reg_desc *r) 466 { 467 access_rw(vcpu, p, r); 468 if (p->is_write) 469 vcpu_set_flag(vcpu, DEBUG_DIRTY); 470 471 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 472 473 return true; 474 } 475 476 /* 477 * reg_to_dbg/dbg_to_reg 478 * 479 * A 32 bit write to a debug register leave top bits alone 480 * A 32 bit read from a debug register only returns the bottom bits 481 * 482 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code 483 * switches between host and guest values in future. 484 */ 485 static void reg_to_dbg(struct kvm_vcpu *vcpu, 486 struct sys_reg_params *p, 487 const struct sys_reg_desc *rd, 488 u64 *dbg_reg) 489 { 490 u64 mask, shift, val; 491 492 get_access_mask(rd, &mask, &shift); 493 494 val = *dbg_reg; 495 val &= ~mask; 496 val |= (p->regval & (mask >> shift)) << shift; 497 *dbg_reg = val; 498 499 vcpu_set_flag(vcpu, DEBUG_DIRTY); 500 } 501 502 static void dbg_to_reg(struct kvm_vcpu *vcpu, 503 struct sys_reg_params *p, 504 const struct sys_reg_desc *rd, 505 u64 *dbg_reg) 506 { 507 u64 mask, shift; 508 509 get_access_mask(rd, &mask, &shift); 510 p->regval = (*dbg_reg & mask) >> shift; 511 } 512 513 static bool trap_bvr(struct kvm_vcpu *vcpu, 514 struct sys_reg_params *p, 515 const struct sys_reg_desc *rd) 516 { 517 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 518 519 if (p->is_write) 520 reg_to_dbg(vcpu, p, rd, dbg_reg); 521 else 522 dbg_to_reg(vcpu, p, rd, dbg_reg); 523 524 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 525 526 return true; 527 } 528 529 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 530 u64 val) 531 { 532 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; 533 return 0; 534 } 535 536 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 537 u64 *val) 538 { 539 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 540 return 0; 541 } 542 543 static void reset_bvr(struct kvm_vcpu *vcpu, 544 const struct sys_reg_desc *rd) 545 { 546 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 547 } 548 549 static bool trap_bcr(struct kvm_vcpu *vcpu, 550 struct sys_reg_params *p, 551 const struct sys_reg_desc *rd) 552 { 553 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 554 555 if (p->is_write) 556 reg_to_dbg(vcpu, p, rd, dbg_reg); 557 else 558 dbg_to_reg(vcpu, p, rd, dbg_reg); 559 560 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 561 562 return true; 563 } 564 565 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 566 u64 val) 567 { 568 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; 569 return 0; 570 } 571 572 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 573 u64 *val) 574 { 575 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 576 return 0; 577 } 578 579 static void reset_bcr(struct kvm_vcpu *vcpu, 580 const struct sys_reg_desc *rd) 581 { 582 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 583 } 584 585 static bool trap_wvr(struct kvm_vcpu *vcpu, 586 struct sys_reg_params *p, 587 const struct sys_reg_desc *rd) 588 { 589 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 590 591 if (p->is_write) 592 reg_to_dbg(vcpu, p, rd, dbg_reg); 593 else 594 dbg_to_reg(vcpu, p, rd, dbg_reg); 595 596 trace_trap_reg(__func__, rd->CRm, p->is_write, 597 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 598 599 return true; 600 } 601 602 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 603 u64 val) 604 { 605 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; 606 return 0; 607 } 608 609 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 610 u64 *val) 611 { 612 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 613 return 0; 614 } 615 616 static void reset_wvr(struct kvm_vcpu *vcpu, 617 const struct sys_reg_desc *rd) 618 { 619 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 620 } 621 622 static bool trap_wcr(struct kvm_vcpu *vcpu, 623 struct sys_reg_params *p, 624 const struct sys_reg_desc *rd) 625 { 626 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 627 628 if (p->is_write) 629 reg_to_dbg(vcpu, p, rd, dbg_reg); 630 else 631 dbg_to_reg(vcpu, p, rd, dbg_reg); 632 633 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 634 635 return true; 636 } 637 638 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 639 u64 val) 640 { 641 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; 642 return 0; 643 } 644 645 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 646 u64 *val) 647 { 648 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 649 return 0; 650 } 651 652 static void reset_wcr(struct kvm_vcpu *vcpu, 653 const struct sys_reg_desc *rd) 654 { 655 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 656 } 657 658 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 659 { 660 u64 amair = read_sysreg(amair_el1); 661 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 662 } 663 664 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 665 { 666 u64 actlr = read_sysreg(actlr_el1); 667 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 668 } 669 670 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 671 { 672 u64 mpidr; 673 674 /* 675 * Map the vcpu_id into the first three affinity level fields of 676 * the MPIDR. We limit the number of VCPUs in level 0 due to a 677 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 678 * of the GICv3 to be able to address each CPU directly when 679 * sending IPIs. 680 */ 681 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 682 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 683 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 684 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 685 } 686 687 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 688 const struct sys_reg_desc *r) 689 { 690 if (kvm_vcpu_has_pmu(vcpu)) 691 return 0; 692 693 return REG_HIDDEN; 694 } 695 696 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 697 { 698 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); 699 700 /* No PMU available, any PMU reg may UNDEF... */ 701 if (!kvm_arm_support_pmu_v3()) 702 return; 703 704 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; 705 n &= ARMV8_PMU_PMCR_N_MASK; 706 if (n) 707 mask |= GENMASK(n - 1, 0); 708 709 reset_unknown(vcpu, r); 710 __vcpu_sys_reg(vcpu, r->reg) &= mask; 711 } 712 713 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 714 { 715 reset_unknown(vcpu, r); 716 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 717 } 718 719 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 720 { 721 reset_unknown(vcpu, r); 722 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK; 723 } 724 725 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 726 { 727 reset_unknown(vcpu, r); 728 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; 729 } 730 731 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 732 { 733 u64 pmcr; 734 735 /* No PMU available, PMCR_EL0 may UNDEF... */ 736 if (!kvm_arm_support_pmu_v3()) 737 return; 738 739 /* Only preserve PMCR_EL0.N, and reset the rest to 0 */ 740 pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT); 741 if (!kvm_supports_32bit_el0()) 742 pmcr |= ARMV8_PMU_PMCR_LC; 743 744 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 745 } 746 747 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 748 { 749 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 750 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 751 752 if (!enabled) 753 kvm_inject_undefined(vcpu); 754 755 return !enabled; 756 } 757 758 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 759 { 760 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 761 } 762 763 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 764 { 765 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 766 } 767 768 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 769 { 770 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 771 } 772 773 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 774 { 775 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 776 } 777 778 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 779 const struct sys_reg_desc *r) 780 { 781 u64 val; 782 783 if (pmu_access_el0_disabled(vcpu)) 784 return false; 785 786 if (p->is_write) { 787 /* 788 * Only update writeable bits of PMCR (continuing into 789 * kvm_pmu_handle_pmcr() as well) 790 */ 791 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 792 val &= ~ARMV8_PMU_PMCR_MASK; 793 val |= p->regval & ARMV8_PMU_PMCR_MASK; 794 if (!kvm_supports_32bit_el0()) 795 val |= ARMV8_PMU_PMCR_LC; 796 kvm_pmu_handle_pmcr(vcpu, val); 797 kvm_vcpu_pmu_restore_guest(vcpu); 798 } else { 799 /* PMCR.P & PMCR.C are RAZ */ 800 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 801 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 802 p->regval = val; 803 } 804 805 return true; 806 } 807 808 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 809 const struct sys_reg_desc *r) 810 { 811 if (pmu_access_event_counter_el0_disabled(vcpu)) 812 return false; 813 814 if (p->is_write) 815 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 816 else 817 /* return PMSELR.SEL field */ 818 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 819 & ARMV8_PMU_COUNTER_MASK; 820 821 return true; 822 } 823 824 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 825 const struct sys_reg_desc *r) 826 { 827 u64 pmceid, mask, shift; 828 829 BUG_ON(p->is_write); 830 831 if (pmu_access_el0_disabled(vcpu)) 832 return false; 833 834 get_access_mask(r, &mask, &shift); 835 836 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 837 pmceid &= mask; 838 pmceid >>= shift; 839 840 p->regval = pmceid; 841 842 return true; 843 } 844 845 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 846 { 847 u64 pmcr, val; 848 849 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 850 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 851 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 852 kvm_inject_undefined(vcpu); 853 return false; 854 } 855 856 return true; 857 } 858 859 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 860 struct sys_reg_params *p, 861 const struct sys_reg_desc *r) 862 { 863 u64 idx = ~0UL; 864 865 if (r->CRn == 9 && r->CRm == 13) { 866 if (r->Op2 == 2) { 867 /* PMXEVCNTR_EL0 */ 868 if (pmu_access_event_counter_el0_disabled(vcpu)) 869 return false; 870 871 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 872 & ARMV8_PMU_COUNTER_MASK; 873 } else if (r->Op2 == 0) { 874 /* PMCCNTR_EL0 */ 875 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 876 return false; 877 878 idx = ARMV8_PMU_CYCLE_IDX; 879 } 880 } else if (r->CRn == 0 && r->CRm == 9) { 881 /* PMCCNTR */ 882 if (pmu_access_event_counter_el0_disabled(vcpu)) 883 return false; 884 885 idx = ARMV8_PMU_CYCLE_IDX; 886 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 887 /* PMEVCNTRn_EL0 */ 888 if (pmu_access_event_counter_el0_disabled(vcpu)) 889 return false; 890 891 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 892 } 893 894 /* Catch any decoding mistake */ 895 WARN_ON(idx == ~0UL); 896 897 if (!pmu_counter_idx_valid(vcpu, idx)) 898 return false; 899 900 if (p->is_write) { 901 if (pmu_access_el0_disabled(vcpu)) 902 return false; 903 904 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 905 } else { 906 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 907 } 908 909 return true; 910 } 911 912 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 913 const struct sys_reg_desc *r) 914 { 915 u64 idx, reg; 916 917 if (pmu_access_el0_disabled(vcpu)) 918 return false; 919 920 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 921 /* PMXEVTYPER_EL0 */ 922 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 923 reg = PMEVTYPER0_EL0 + idx; 924 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 925 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 926 if (idx == ARMV8_PMU_CYCLE_IDX) 927 reg = PMCCFILTR_EL0; 928 else 929 /* PMEVTYPERn_EL0 */ 930 reg = PMEVTYPER0_EL0 + idx; 931 } else { 932 BUG(); 933 } 934 935 if (!pmu_counter_idx_valid(vcpu, idx)) 936 return false; 937 938 if (p->is_write) { 939 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 940 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 941 kvm_vcpu_pmu_restore_guest(vcpu); 942 } else { 943 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 944 } 945 946 return true; 947 } 948 949 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 950 const struct sys_reg_desc *r) 951 { 952 u64 val, mask; 953 954 if (pmu_access_el0_disabled(vcpu)) 955 return false; 956 957 mask = kvm_pmu_valid_counter_mask(vcpu); 958 if (p->is_write) { 959 val = p->regval & mask; 960 if (r->Op2 & 0x1) { 961 /* accessing PMCNTENSET_EL0 */ 962 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 963 kvm_pmu_enable_counter_mask(vcpu, val); 964 kvm_vcpu_pmu_restore_guest(vcpu); 965 } else { 966 /* accessing PMCNTENCLR_EL0 */ 967 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 968 kvm_pmu_disable_counter_mask(vcpu, val); 969 } 970 } else { 971 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 972 } 973 974 return true; 975 } 976 977 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 978 const struct sys_reg_desc *r) 979 { 980 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 981 982 if (check_pmu_access_disabled(vcpu, 0)) 983 return false; 984 985 if (p->is_write) { 986 u64 val = p->regval & mask; 987 988 if (r->Op2 & 0x1) 989 /* accessing PMINTENSET_EL1 */ 990 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 991 else 992 /* accessing PMINTENCLR_EL1 */ 993 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 994 } else { 995 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 996 } 997 998 return true; 999 } 1000 1001 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1002 const struct sys_reg_desc *r) 1003 { 1004 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 1005 1006 if (pmu_access_el0_disabled(vcpu)) 1007 return false; 1008 1009 if (p->is_write) { 1010 if (r->CRm & 0x2) 1011 /* accessing PMOVSSET_EL0 */ 1012 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1013 else 1014 /* accessing PMOVSCLR_EL0 */ 1015 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1016 } else { 1017 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1018 } 1019 1020 return true; 1021 } 1022 1023 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1024 const struct sys_reg_desc *r) 1025 { 1026 u64 mask; 1027 1028 if (!p->is_write) 1029 return read_from_write_only(vcpu, p, r); 1030 1031 if (pmu_write_swinc_el0_disabled(vcpu)) 1032 return false; 1033 1034 mask = kvm_pmu_valid_counter_mask(vcpu); 1035 kvm_pmu_software_increment(vcpu, p->regval & mask); 1036 return true; 1037 } 1038 1039 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1040 const struct sys_reg_desc *r) 1041 { 1042 if (p->is_write) { 1043 if (!vcpu_mode_priv(vcpu)) { 1044 kvm_inject_undefined(vcpu); 1045 return false; 1046 } 1047 1048 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1049 p->regval & ARMV8_PMU_USERENR_MASK; 1050 } else { 1051 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1052 & ARMV8_PMU_USERENR_MASK; 1053 } 1054 1055 return true; 1056 } 1057 1058 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1059 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1060 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1061 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1062 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1063 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1064 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1065 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1066 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1067 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1068 1069 #define PMU_SYS_REG(r) \ 1070 SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility 1071 1072 /* Macro to expand the PMEVCNTRn_EL0 register */ 1073 #define PMU_PMEVCNTR_EL0(n) \ 1074 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \ 1075 .reset = reset_pmevcntr, \ 1076 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1077 1078 /* Macro to expand the PMEVTYPERn_EL0 register */ 1079 #define PMU_PMEVTYPER_EL0(n) \ 1080 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \ 1081 .reset = reset_pmevtyper, \ 1082 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1083 1084 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1085 const struct sys_reg_desc *r) 1086 { 1087 kvm_inject_undefined(vcpu); 1088 1089 return false; 1090 } 1091 1092 /* Macro to expand the AMU counter and type registers*/ 1093 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1094 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1095 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1096 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1097 1098 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1099 const struct sys_reg_desc *rd) 1100 { 1101 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1102 } 1103 1104 /* 1105 * If we land here on a PtrAuth access, that is because we didn't 1106 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1107 * way this happens is when the guest does not have PtrAuth support 1108 * enabled. 1109 */ 1110 #define __PTRAUTH_KEY(k) \ 1111 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1112 .visibility = ptrauth_visibility} 1113 1114 #define PTRAUTH_KEY(k) \ 1115 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1116 __PTRAUTH_KEY(k ## KEYHI_EL1) 1117 1118 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1119 struct sys_reg_params *p, 1120 const struct sys_reg_desc *r) 1121 { 1122 enum kvm_arch_timers tmr; 1123 enum kvm_arch_timer_regs treg; 1124 u64 reg = reg_to_encoding(r); 1125 1126 switch (reg) { 1127 case SYS_CNTP_TVAL_EL0: 1128 case SYS_AARCH32_CNTP_TVAL: 1129 tmr = TIMER_PTIMER; 1130 treg = TIMER_REG_TVAL; 1131 break; 1132 case SYS_CNTP_CTL_EL0: 1133 case SYS_AARCH32_CNTP_CTL: 1134 tmr = TIMER_PTIMER; 1135 treg = TIMER_REG_CTL; 1136 break; 1137 case SYS_CNTP_CVAL_EL0: 1138 case SYS_AARCH32_CNTP_CVAL: 1139 tmr = TIMER_PTIMER; 1140 treg = TIMER_REG_CVAL; 1141 break; 1142 default: 1143 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1144 kvm_inject_undefined(vcpu); 1145 return false; 1146 } 1147 1148 if (p->is_write) 1149 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1150 else 1151 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1152 1153 return true; 1154 } 1155 1156 static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu) 1157 { 1158 if (kvm_vcpu_has_pmu(vcpu)) 1159 return vcpu->kvm->arch.dfr0_pmuver.imp; 1160 1161 return vcpu->kvm->arch.dfr0_pmuver.unimp; 1162 } 1163 1164 static u8 perfmon_to_pmuver(u8 perfmon) 1165 { 1166 switch (perfmon) { 1167 case ID_DFR0_EL1_PerfMon_PMUv3: 1168 return ID_AA64DFR0_EL1_PMUVer_IMP; 1169 case ID_DFR0_EL1_PerfMon_IMPDEF: 1170 return ID_AA64DFR0_EL1_PMUVer_IMP_DEF; 1171 default: 1172 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1173 return perfmon; 1174 } 1175 } 1176 1177 static u8 pmuver_to_perfmon(u8 pmuver) 1178 { 1179 switch (pmuver) { 1180 case ID_AA64DFR0_EL1_PMUVer_IMP: 1181 return ID_DFR0_EL1_PerfMon_PMUv3; 1182 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1183 return ID_DFR0_EL1_PerfMon_IMPDEF; 1184 default: 1185 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1186 return pmuver; 1187 } 1188 } 1189 1190 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1191 static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r) 1192 { 1193 u32 id = reg_to_encoding(r); 1194 u64 val; 1195 1196 if (sysreg_visible_as_raz(vcpu, r)) 1197 return 0; 1198 1199 val = read_sanitised_ftr_reg(id); 1200 1201 switch (id) { 1202 case SYS_ID_AA64PFR0_EL1: 1203 if (!vcpu_has_sve(vcpu)) 1204 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); 1205 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); 1206 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); 1207 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); 1208 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); 1209 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); 1210 if (kvm_vgic_global_state.type == VGIC_V3) { 1211 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); 1212 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1); 1213 } 1214 break; 1215 case SYS_ID_AA64PFR1_EL1: 1216 if (!kvm_has_mte(vcpu->kvm)) 1217 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1218 1219 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1220 break; 1221 case SYS_ID_AA64ISAR1_EL1: 1222 if (!vcpu_has_ptrauth(vcpu)) 1223 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1224 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1225 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1226 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1227 break; 1228 case SYS_ID_AA64ISAR2_EL1: 1229 if (!vcpu_has_ptrauth(vcpu)) 1230 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1231 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1232 if (!cpus_have_final_cap(ARM64_HAS_WFXT)) 1233 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1234 break; 1235 case SYS_ID_AA64DFR0_EL1: 1236 /* Limit debug to ARMv8.0 */ 1237 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); 1238 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6); 1239 /* Set PMUver to the required version */ 1240 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); 1241 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), 1242 vcpu_pmuver(vcpu)); 1243 /* Hide SPE from guests */ 1244 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); 1245 break; 1246 case SYS_ID_DFR0_EL1: 1247 val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); 1248 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), 1249 pmuver_to_perfmon(vcpu_pmuver(vcpu))); 1250 break; 1251 case SYS_ID_AA64MMFR2_EL1: 1252 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1253 break; 1254 case SYS_ID_MMFR4_EL1: 1255 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1256 break; 1257 } 1258 1259 return val; 1260 } 1261 1262 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1263 const struct sys_reg_desc *r) 1264 { 1265 u32 id = reg_to_encoding(r); 1266 1267 switch (id) { 1268 case SYS_ID_AA64ZFR0_EL1: 1269 if (!vcpu_has_sve(vcpu)) 1270 return REG_RAZ; 1271 break; 1272 } 1273 1274 return 0; 1275 } 1276 1277 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1278 const struct sys_reg_desc *r) 1279 { 1280 /* 1281 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1282 * EL. Promote to RAZ/WI in order to guarantee consistency between 1283 * systems. 1284 */ 1285 if (!kvm_supports_32bit_el0()) 1286 return REG_RAZ | REG_USER_WI; 1287 1288 return id_visibility(vcpu, r); 1289 } 1290 1291 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1292 const struct sys_reg_desc *r) 1293 { 1294 return REG_RAZ; 1295 } 1296 1297 /* cpufeature ID register access trap handlers */ 1298 1299 static bool access_id_reg(struct kvm_vcpu *vcpu, 1300 struct sys_reg_params *p, 1301 const struct sys_reg_desc *r) 1302 { 1303 if (p->is_write) 1304 return write_to_read_only(vcpu, p, r); 1305 1306 p->regval = read_id_reg(vcpu, r); 1307 if (vcpu_has_nv(vcpu)) 1308 access_nested_id_reg(vcpu, p, r); 1309 1310 return true; 1311 } 1312 1313 /* Visibility overrides for SVE-specific control registers */ 1314 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1315 const struct sys_reg_desc *rd) 1316 { 1317 if (vcpu_has_sve(vcpu)) 1318 return 0; 1319 1320 return REG_HIDDEN; 1321 } 1322 1323 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1324 const struct sys_reg_desc *rd, 1325 u64 val) 1326 { 1327 u8 csv2, csv3; 1328 1329 /* 1330 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as 1331 * it doesn't promise more than what is actually provided (the 1332 * guest could otherwise be covered in ectoplasmic residue). 1333 */ 1334 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV2_SHIFT); 1335 if (csv2 > 1 || 1336 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) 1337 return -EINVAL; 1338 1339 /* Same thing for CSV3 */ 1340 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_EL1_CSV3_SHIFT); 1341 if (csv3 > 1 || 1342 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) 1343 return -EINVAL; 1344 1345 /* We can only differ with CSV[23], and anything else is an error */ 1346 val ^= read_id_reg(vcpu, rd); 1347 val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) | 1348 ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3)); 1349 if (val) 1350 return -EINVAL; 1351 1352 vcpu->kvm->arch.pfr0_csv2 = csv2; 1353 vcpu->kvm->arch.pfr0_csv3 = csv3; 1354 1355 return 0; 1356 } 1357 1358 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1359 const struct sys_reg_desc *rd, 1360 u64 val) 1361 { 1362 u8 pmuver, host_pmuver; 1363 bool valid_pmu; 1364 1365 host_pmuver = kvm_arm_pmu_get_pmuver_limit(); 1366 1367 /* 1368 * Allow AA64DFR0_EL1.PMUver to be set from userspace as long 1369 * as it doesn't promise more than what the HW gives us. We 1370 * allow an IMPDEF PMU though, only if no PMU is supported 1371 * (KVM backward compatibility handling). 1372 */ 1373 pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val); 1374 if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver)) 1375 return -EINVAL; 1376 1377 valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF); 1378 1379 /* Make sure view register and PMU support do match */ 1380 if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) 1381 return -EINVAL; 1382 1383 /* We can only differ with PMUver, and anything else is an error */ 1384 val ^= read_id_reg(vcpu, rd); 1385 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); 1386 if (val) 1387 return -EINVAL; 1388 1389 if (valid_pmu) 1390 vcpu->kvm->arch.dfr0_pmuver.imp = pmuver; 1391 else 1392 vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver; 1393 1394 return 0; 1395 } 1396 1397 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1398 const struct sys_reg_desc *rd, 1399 u64 val) 1400 { 1401 u8 perfmon, host_perfmon; 1402 bool valid_pmu; 1403 1404 host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1405 1406 /* 1407 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1408 * it doesn't promise more than what the HW gives us on the 1409 * AArch64 side (as everything is emulated with that), and 1410 * that this is a PMUv3. 1411 */ 1412 perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val); 1413 if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) || 1414 (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)) 1415 return -EINVAL; 1416 1417 valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_EL1_PerfMon_IMPDEF); 1418 1419 /* Make sure view register and PMU support do match */ 1420 if (kvm_vcpu_has_pmu(vcpu) != valid_pmu) 1421 return -EINVAL; 1422 1423 /* We can only differ with PerfMon, and anything else is an error */ 1424 val ^= read_id_reg(vcpu, rd); 1425 val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); 1426 if (val) 1427 return -EINVAL; 1428 1429 if (valid_pmu) 1430 vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon); 1431 else 1432 vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon); 1433 1434 return 0; 1435 } 1436 1437 /* 1438 * cpufeature ID register user accessors 1439 * 1440 * For now, these registers are immutable for userspace, so no values 1441 * are stored, and for set_id_reg() we don't allow the effective value 1442 * to be changed. 1443 */ 1444 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1445 u64 *val) 1446 { 1447 *val = read_id_reg(vcpu, rd); 1448 return 0; 1449 } 1450 1451 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1452 u64 val) 1453 { 1454 /* This is what we mean by invariant: you can't change it. */ 1455 if (val != read_id_reg(vcpu, rd)) 1456 return -EINVAL; 1457 1458 return 0; 1459 } 1460 1461 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1462 u64 *val) 1463 { 1464 *val = 0; 1465 return 0; 1466 } 1467 1468 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1469 u64 val) 1470 { 1471 return 0; 1472 } 1473 1474 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1475 const struct sys_reg_desc *r) 1476 { 1477 if (p->is_write) 1478 return write_to_read_only(vcpu, p, r); 1479 1480 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1481 return true; 1482 } 1483 1484 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1485 const struct sys_reg_desc *r) 1486 { 1487 if (p->is_write) 1488 return write_to_read_only(vcpu, p, r); 1489 1490 p->regval = __vcpu_sys_reg(vcpu, r->reg); 1491 return true; 1492 } 1493 1494 /* 1495 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 1496 * by the physical CPU which the vcpu currently resides in. 1497 */ 1498 static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1499 { 1500 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1501 u64 clidr; 1502 u8 loc; 1503 1504 if ((ctr_el0 & CTR_EL0_IDC)) { 1505 /* 1506 * Data cache clean to the PoU is not required so LoUU and LoUIS 1507 * will not be set and a unified cache, which will be marked as 1508 * LoC, will be added. 1509 * 1510 * If not DIC, let the unified cache L2 so that an instruction 1511 * cache can be added as L1 later. 1512 */ 1513 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 1514 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 1515 } else { 1516 /* 1517 * Data cache clean to the PoU is required so let L1 have a data 1518 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 1519 * it can be marked as LoC too. 1520 */ 1521 loc = 1; 1522 clidr = 1 << CLIDR_LOUU_SHIFT; 1523 clidr |= 1 << CLIDR_LOUIS_SHIFT; 1524 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 1525 } 1526 1527 /* 1528 * Instruction cache invalidation to the PoU is required so let L1 have 1529 * an instruction cache. If L1 already has a data cache, it will be 1530 * CACHE_TYPE_SEPARATE. 1531 */ 1532 if (!(ctr_el0 & CTR_EL0_DIC)) 1533 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 1534 1535 clidr |= loc << CLIDR_LOC_SHIFT; 1536 1537 /* 1538 * Add tag cache unified to data cache. Allocation tags and data are 1539 * unified in a cache line so that it looks valid even if there is only 1540 * one cache line. 1541 */ 1542 if (kvm_has_mte(vcpu->kvm)) 1543 clidr |= 2 << CLIDR_TTYPE_SHIFT(loc); 1544 1545 __vcpu_sys_reg(vcpu, r->reg) = clidr; 1546 } 1547 1548 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1549 u64 val) 1550 { 1551 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 1552 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 1553 1554 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 1555 return -EINVAL; 1556 1557 __vcpu_sys_reg(vcpu, rd->reg) = val; 1558 1559 return 0; 1560 } 1561 1562 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1563 const struct sys_reg_desc *r) 1564 { 1565 int reg = r->reg; 1566 1567 if (p->is_write) 1568 vcpu_write_sys_reg(vcpu, p->regval, reg); 1569 else 1570 p->regval = vcpu_read_sys_reg(vcpu, reg); 1571 return true; 1572 } 1573 1574 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1575 const struct sys_reg_desc *r) 1576 { 1577 u32 csselr; 1578 1579 if (p->is_write) 1580 return write_to_read_only(vcpu, p, r); 1581 1582 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1583 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 1584 if (csselr < CSSELR_MAX) 1585 p->regval = get_ccsidr(vcpu, csselr); 1586 1587 return true; 1588 } 1589 1590 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 1591 const struct sys_reg_desc *rd) 1592 { 1593 if (kvm_has_mte(vcpu->kvm)) 1594 return 0; 1595 1596 return REG_HIDDEN; 1597 } 1598 1599 #define MTE_REG(name) { \ 1600 SYS_DESC(SYS_##name), \ 1601 .access = undef_access, \ 1602 .reset = reset_unknown, \ 1603 .reg = name, \ 1604 .visibility = mte_visibility, \ 1605 } 1606 1607 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 1608 const struct sys_reg_desc *rd) 1609 { 1610 if (vcpu_has_nv(vcpu)) 1611 return 0; 1612 1613 return REG_HIDDEN; 1614 } 1615 1616 #define EL2_REG(name, acc, rst, v) { \ 1617 SYS_DESC(SYS_##name), \ 1618 .access = acc, \ 1619 .reset = rst, \ 1620 .reg = name, \ 1621 .visibility = el2_visibility, \ 1622 .val = v, \ 1623 } 1624 1625 /* 1626 * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when 1627 * HCR_EL2.E2H==1, and only in the sysreg table for convenience of 1628 * handling traps. Given that, they are always hidden from userspace. 1629 */ 1630 static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, 1631 const struct sys_reg_desc *rd) 1632 { 1633 return REG_HIDDEN_USER; 1634 } 1635 1636 #define EL12_REG(name, acc, rst, v) { \ 1637 SYS_DESC(SYS_##name##_EL12), \ 1638 .access = acc, \ 1639 .reset = rst, \ 1640 .reg = name##_EL1, \ 1641 .val = v, \ 1642 .visibility = elx2_visibility, \ 1643 } 1644 1645 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1646 #define ID_SANITISED(name) { \ 1647 SYS_DESC(SYS_##name), \ 1648 .access = access_id_reg, \ 1649 .get_user = get_id_reg, \ 1650 .set_user = set_id_reg, \ 1651 .visibility = id_visibility, \ 1652 } 1653 1654 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1655 #define AA32_ID_SANITISED(name) { \ 1656 SYS_DESC(SYS_##name), \ 1657 .access = access_id_reg, \ 1658 .get_user = get_id_reg, \ 1659 .set_user = set_id_reg, \ 1660 .visibility = aa32_id_visibility, \ 1661 } 1662 1663 /* 1664 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1665 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1666 * (1 <= crm < 8, 0 <= Op2 < 8). 1667 */ 1668 #define ID_UNALLOCATED(crm, op2) { \ 1669 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1670 .access = access_id_reg, \ 1671 .get_user = get_id_reg, \ 1672 .set_user = set_id_reg, \ 1673 .visibility = raz_visibility \ 1674 } 1675 1676 /* 1677 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1678 * For now, these are exposed just like unallocated ID regs: they appear 1679 * RAZ for the guest. 1680 */ 1681 #define ID_HIDDEN(name) { \ 1682 SYS_DESC(SYS_##name), \ 1683 .access = access_id_reg, \ 1684 .get_user = get_id_reg, \ 1685 .set_user = set_id_reg, \ 1686 .visibility = raz_visibility, \ 1687 } 1688 1689 static bool access_sp_el1(struct kvm_vcpu *vcpu, 1690 struct sys_reg_params *p, 1691 const struct sys_reg_desc *r) 1692 { 1693 if (p->is_write) 1694 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 1695 else 1696 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 1697 1698 return true; 1699 } 1700 1701 static bool access_elr(struct kvm_vcpu *vcpu, 1702 struct sys_reg_params *p, 1703 const struct sys_reg_desc *r) 1704 { 1705 if (p->is_write) 1706 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 1707 else 1708 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 1709 1710 return true; 1711 } 1712 1713 static bool access_spsr(struct kvm_vcpu *vcpu, 1714 struct sys_reg_params *p, 1715 const struct sys_reg_desc *r) 1716 { 1717 if (p->is_write) 1718 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 1719 else 1720 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 1721 1722 return true; 1723 } 1724 1725 /* 1726 * Architected system registers. 1727 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1728 * 1729 * Debug handling: We do trap most, if not all debug related system 1730 * registers. The implementation is good enough to ensure that a guest 1731 * can use these with minimal performance degradation. The drawback is 1732 * that we don't implement any of the external debug architecture. 1733 * This should be revisited if we ever encounter a more demanding 1734 * guest... 1735 */ 1736 static const struct sys_reg_desc sys_reg_descs[] = { 1737 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1738 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1739 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1740 1741 DBG_BCR_BVR_WCR_WVR_EL1(0), 1742 DBG_BCR_BVR_WCR_WVR_EL1(1), 1743 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1744 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1745 DBG_BCR_BVR_WCR_WVR_EL1(2), 1746 DBG_BCR_BVR_WCR_WVR_EL1(3), 1747 DBG_BCR_BVR_WCR_WVR_EL1(4), 1748 DBG_BCR_BVR_WCR_WVR_EL1(5), 1749 DBG_BCR_BVR_WCR_WVR_EL1(6), 1750 DBG_BCR_BVR_WCR_WVR_EL1(7), 1751 DBG_BCR_BVR_WCR_WVR_EL1(8), 1752 DBG_BCR_BVR_WCR_WVR_EL1(9), 1753 DBG_BCR_BVR_WCR_WVR_EL1(10), 1754 DBG_BCR_BVR_WCR_WVR_EL1(11), 1755 DBG_BCR_BVR_WCR_WVR_EL1(12), 1756 DBG_BCR_BVR_WCR_WVR_EL1(13), 1757 DBG_BCR_BVR_WCR_WVR_EL1(14), 1758 DBG_BCR_BVR_WCR_WVR_EL1(15), 1759 1760 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1761 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 1762 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 1763 SYS_OSLSR_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 1764 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1765 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1766 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1767 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1768 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1769 1770 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1771 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1772 // DBGDTR[TR]X_EL0 share the same encoding 1773 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1774 1775 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1776 1777 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1778 1779 /* 1780 * ID regs: all ID_SANITISED() entries here must have corresponding 1781 * entries in arm64_ftr_regs[]. 1782 */ 1783 1784 /* AArch64 mappings of the AArch32 ID registers */ 1785 /* CRm=1 */ 1786 AA32_ID_SANITISED(ID_PFR0_EL1), 1787 AA32_ID_SANITISED(ID_PFR1_EL1), 1788 { SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg, 1789 .get_user = get_id_reg, .set_user = set_id_dfr0_el1, 1790 .visibility = aa32_id_visibility, }, 1791 ID_HIDDEN(ID_AFR0_EL1), 1792 AA32_ID_SANITISED(ID_MMFR0_EL1), 1793 AA32_ID_SANITISED(ID_MMFR1_EL1), 1794 AA32_ID_SANITISED(ID_MMFR2_EL1), 1795 AA32_ID_SANITISED(ID_MMFR3_EL1), 1796 1797 /* CRm=2 */ 1798 AA32_ID_SANITISED(ID_ISAR0_EL1), 1799 AA32_ID_SANITISED(ID_ISAR1_EL1), 1800 AA32_ID_SANITISED(ID_ISAR2_EL1), 1801 AA32_ID_SANITISED(ID_ISAR3_EL1), 1802 AA32_ID_SANITISED(ID_ISAR4_EL1), 1803 AA32_ID_SANITISED(ID_ISAR5_EL1), 1804 AA32_ID_SANITISED(ID_MMFR4_EL1), 1805 AA32_ID_SANITISED(ID_ISAR6_EL1), 1806 1807 /* CRm=3 */ 1808 AA32_ID_SANITISED(MVFR0_EL1), 1809 AA32_ID_SANITISED(MVFR1_EL1), 1810 AA32_ID_SANITISED(MVFR2_EL1), 1811 ID_UNALLOCATED(3,3), 1812 AA32_ID_SANITISED(ID_PFR2_EL1), 1813 ID_HIDDEN(ID_DFR1_EL1), 1814 AA32_ID_SANITISED(ID_MMFR5_EL1), 1815 ID_UNALLOCATED(3,7), 1816 1817 /* AArch64 ID registers */ 1818 /* CRm=4 */ 1819 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, 1820 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, 1821 ID_SANITISED(ID_AA64PFR1_EL1), 1822 ID_UNALLOCATED(4,2), 1823 ID_UNALLOCATED(4,3), 1824 ID_SANITISED(ID_AA64ZFR0_EL1), 1825 ID_HIDDEN(ID_AA64SMFR0_EL1), 1826 ID_UNALLOCATED(4,6), 1827 ID_UNALLOCATED(4,7), 1828 1829 /* CRm=5 */ 1830 { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg, 1831 .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, }, 1832 ID_SANITISED(ID_AA64DFR1_EL1), 1833 ID_UNALLOCATED(5,2), 1834 ID_UNALLOCATED(5,3), 1835 ID_HIDDEN(ID_AA64AFR0_EL1), 1836 ID_HIDDEN(ID_AA64AFR1_EL1), 1837 ID_UNALLOCATED(5,6), 1838 ID_UNALLOCATED(5,7), 1839 1840 /* CRm=6 */ 1841 ID_SANITISED(ID_AA64ISAR0_EL1), 1842 ID_SANITISED(ID_AA64ISAR1_EL1), 1843 ID_SANITISED(ID_AA64ISAR2_EL1), 1844 ID_UNALLOCATED(6,3), 1845 ID_UNALLOCATED(6,4), 1846 ID_UNALLOCATED(6,5), 1847 ID_UNALLOCATED(6,6), 1848 ID_UNALLOCATED(6,7), 1849 1850 /* CRm=7 */ 1851 ID_SANITISED(ID_AA64MMFR0_EL1), 1852 ID_SANITISED(ID_AA64MMFR1_EL1), 1853 ID_SANITISED(ID_AA64MMFR2_EL1), 1854 ID_UNALLOCATED(7,3), 1855 ID_UNALLOCATED(7,4), 1856 ID_UNALLOCATED(7,5), 1857 ID_UNALLOCATED(7,6), 1858 ID_UNALLOCATED(7,7), 1859 1860 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1861 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1862 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1863 1864 MTE_REG(RGSR_EL1), 1865 MTE_REG(GCR_EL1), 1866 1867 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1868 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 1869 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 1870 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 1871 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1872 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1873 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1874 1875 PTRAUTH_KEY(APIA), 1876 PTRAUTH_KEY(APIB), 1877 PTRAUTH_KEY(APDA), 1878 PTRAUTH_KEY(APDB), 1879 PTRAUTH_KEY(APGA), 1880 1881 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 1882 { SYS_DESC(SYS_ELR_EL1), access_elr}, 1883 1884 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1885 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1886 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1887 1888 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1889 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1890 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1891 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1892 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1893 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1894 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1895 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1896 1897 MTE_REG(TFSR_EL1), 1898 MTE_REG(TFSRE0_EL1), 1899 1900 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1901 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1902 1903 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 1904 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 1905 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 1906 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 1907 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 1908 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 1909 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 1910 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 1911 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 1912 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 1913 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 1914 /* PMBIDR_EL1 is not trapped */ 1915 1916 { PMU_SYS_REG(SYS_PMINTENSET_EL1), 1917 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1918 { PMU_SYS_REG(SYS_PMINTENCLR_EL1), 1919 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1920 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 1921 1922 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1923 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1924 1925 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1926 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1927 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1928 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1929 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1930 1931 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 1932 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1933 1934 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1935 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1936 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1937 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1938 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1939 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1940 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1941 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1942 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1943 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1944 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1945 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1946 1947 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1948 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1949 1950 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 1951 1952 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1953 1954 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1955 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 1956 .set_user = set_clidr }, 1957 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 1958 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 1959 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1960 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1961 { SYS_DESC(SYS_SVCR), undef_access }, 1962 1963 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, 1964 .reset = reset_pmcr, .reg = PMCR_EL0 }, 1965 { PMU_SYS_REG(SYS_PMCNTENSET_EL0), 1966 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1967 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0), 1968 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1969 { PMU_SYS_REG(SYS_PMOVSCLR_EL0), 1970 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1971 /* 1972 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 1973 * previously (and pointlessly) advertised in the past... 1974 */ 1975 { PMU_SYS_REG(SYS_PMSWINC_EL0), 1976 .get_user = get_raz_reg, .set_user = set_wi_reg, 1977 .access = access_pmswinc, .reset = NULL }, 1978 { PMU_SYS_REG(SYS_PMSELR_EL0), 1979 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 1980 { PMU_SYS_REG(SYS_PMCEID0_EL0), 1981 .access = access_pmceid, .reset = NULL }, 1982 { PMU_SYS_REG(SYS_PMCEID1_EL0), 1983 .access = access_pmceid, .reset = NULL }, 1984 { PMU_SYS_REG(SYS_PMCCNTR_EL0), 1985 .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 }, 1986 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0), 1987 .access = access_pmu_evtyper, .reset = NULL }, 1988 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0), 1989 .access = access_pmu_evcntr, .reset = NULL }, 1990 /* 1991 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1992 * in 32bit mode. Here we choose to reset it as zero for consistency. 1993 */ 1994 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr, 1995 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 1996 { PMU_SYS_REG(SYS_PMOVSSET_EL0), 1997 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1998 1999 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2000 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2001 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2002 2003 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2004 2005 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2006 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2007 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2008 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2009 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2010 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2011 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2012 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2013 AMU_AMEVCNTR0_EL0(0), 2014 AMU_AMEVCNTR0_EL0(1), 2015 AMU_AMEVCNTR0_EL0(2), 2016 AMU_AMEVCNTR0_EL0(3), 2017 AMU_AMEVCNTR0_EL0(4), 2018 AMU_AMEVCNTR0_EL0(5), 2019 AMU_AMEVCNTR0_EL0(6), 2020 AMU_AMEVCNTR0_EL0(7), 2021 AMU_AMEVCNTR0_EL0(8), 2022 AMU_AMEVCNTR0_EL0(9), 2023 AMU_AMEVCNTR0_EL0(10), 2024 AMU_AMEVCNTR0_EL0(11), 2025 AMU_AMEVCNTR0_EL0(12), 2026 AMU_AMEVCNTR0_EL0(13), 2027 AMU_AMEVCNTR0_EL0(14), 2028 AMU_AMEVCNTR0_EL0(15), 2029 AMU_AMEVTYPER0_EL0(0), 2030 AMU_AMEVTYPER0_EL0(1), 2031 AMU_AMEVTYPER0_EL0(2), 2032 AMU_AMEVTYPER0_EL0(3), 2033 AMU_AMEVTYPER0_EL0(4), 2034 AMU_AMEVTYPER0_EL0(5), 2035 AMU_AMEVTYPER0_EL0(6), 2036 AMU_AMEVTYPER0_EL0(7), 2037 AMU_AMEVTYPER0_EL0(8), 2038 AMU_AMEVTYPER0_EL0(9), 2039 AMU_AMEVTYPER0_EL0(10), 2040 AMU_AMEVTYPER0_EL0(11), 2041 AMU_AMEVTYPER0_EL0(12), 2042 AMU_AMEVTYPER0_EL0(13), 2043 AMU_AMEVTYPER0_EL0(14), 2044 AMU_AMEVTYPER0_EL0(15), 2045 AMU_AMEVCNTR1_EL0(0), 2046 AMU_AMEVCNTR1_EL0(1), 2047 AMU_AMEVCNTR1_EL0(2), 2048 AMU_AMEVCNTR1_EL0(3), 2049 AMU_AMEVCNTR1_EL0(4), 2050 AMU_AMEVCNTR1_EL0(5), 2051 AMU_AMEVCNTR1_EL0(6), 2052 AMU_AMEVCNTR1_EL0(7), 2053 AMU_AMEVCNTR1_EL0(8), 2054 AMU_AMEVCNTR1_EL0(9), 2055 AMU_AMEVCNTR1_EL0(10), 2056 AMU_AMEVCNTR1_EL0(11), 2057 AMU_AMEVCNTR1_EL0(12), 2058 AMU_AMEVCNTR1_EL0(13), 2059 AMU_AMEVCNTR1_EL0(14), 2060 AMU_AMEVCNTR1_EL0(15), 2061 AMU_AMEVTYPER1_EL0(0), 2062 AMU_AMEVTYPER1_EL0(1), 2063 AMU_AMEVTYPER1_EL0(2), 2064 AMU_AMEVTYPER1_EL0(3), 2065 AMU_AMEVTYPER1_EL0(4), 2066 AMU_AMEVTYPER1_EL0(5), 2067 AMU_AMEVTYPER1_EL0(6), 2068 AMU_AMEVTYPER1_EL0(7), 2069 AMU_AMEVTYPER1_EL0(8), 2070 AMU_AMEVTYPER1_EL0(9), 2071 AMU_AMEVTYPER1_EL0(10), 2072 AMU_AMEVTYPER1_EL0(11), 2073 AMU_AMEVTYPER1_EL0(12), 2074 AMU_AMEVTYPER1_EL0(13), 2075 AMU_AMEVTYPER1_EL0(14), 2076 AMU_AMEVTYPER1_EL0(15), 2077 2078 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2079 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2080 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2081 2082 /* PMEVCNTRn_EL0 */ 2083 PMU_PMEVCNTR_EL0(0), 2084 PMU_PMEVCNTR_EL0(1), 2085 PMU_PMEVCNTR_EL0(2), 2086 PMU_PMEVCNTR_EL0(3), 2087 PMU_PMEVCNTR_EL0(4), 2088 PMU_PMEVCNTR_EL0(5), 2089 PMU_PMEVCNTR_EL0(6), 2090 PMU_PMEVCNTR_EL0(7), 2091 PMU_PMEVCNTR_EL0(8), 2092 PMU_PMEVCNTR_EL0(9), 2093 PMU_PMEVCNTR_EL0(10), 2094 PMU_PMEVCNTR_EL0(11), 2095 PMU_PMEVCNTR_EL0(12), 2096 PMU_PMEVCNTR_EL0(13), 2097 PMU_PMEVCNTR_EL0(14), 2098 PMU_PMEVCNTR_EL0(15), 2099 PMU_PMEVCNTR_EL0(16), 2100 PMU_PMEVCNTR_EL0(17), 2101 PMU_PMEVCNTR_EL0(18), 2102 PMU_PMEVCNTR_EL0(19), 2103 PMU_PMEVCNTR_EL0(20), 2104 PMU_PMEVCNTR_EL0(21), 2105 PMU_PMEVCNTR_EL0(22), 2106 PMU_PMEVCNTR_EL0(23), 2107 PMU_PMEVCNTR_EL0(24), 2108 PMU_PMEVCNTR_EL0(25), 2109 PMU_PMEVCNTR_EL0(26), 2110 PMU_PMEVCNTR_EL0(27), 2111 PMU_PMEVCNTR_EL0(28), 2112 PMU_PMEVCNTR_EL0(29), 2113 PMU_PMEVCNTR_EL0(30), 2114 /* PMEVTYPERn_EL0 */ 2115 PMU_PMEVTYPER_EL0(0), 2116 PMU_PMEVTYPER_EL0(1), 2117 PMU_PMEVTYPER_EL0(2), 2118 PMU_PMEVTYPER_EL0(3), 2119 PMU_PMEVTYPER_EL0(4), 2120 PMU_PMEVTYPER_EL0(5), 2121 PMU_PMEVTYPER_EL0(6), 2122 PMU_PMEVTYPER_EL0(7), 2123 PMU_PMEVTYPER_EL0(8), 2124 PMU_PMEVTYPER_EL0(9), 2125 PMU_PMEVTYPER_EL0(10), 2126 PMU_PMEVTYPER_EL0(11), 2127 PMU_PMEVTYPER_EL0(12), 2128 PMU_PMEVTYPER_EL0(13), 2129 PMU_PMEVTYPER_EL0(14), 2130 PMU_PMEVTYPER_EL0(15), 2131 PMU_PMEVTYPER_EL0(16), 2132 PMU_PMEVTYPER_EL0(17), 2133 PMU_PMEVTYPER_EL0(18), 2134 PMU_PMEVTYPER_EL0(19), 2135 PMU_PMEVTYPER_EL0(20), 2136 PMU_PMEVTYPER_EL0(21), 2137 PMU_PMEVTYPER_EL0(22), 2138 PMU_PMEVTYPER_EL0(23), 2139 PMU_PMEVTYPER_EL0(24), 2140 PMU_PMEVTYPER_EL0(25), 2141 PMU_PMEVTYPER_EL0(26), 2142 PMU_PMEVTYPER_EL0(27), 2143 PMU_PMEVTYPER_EL0(28), 2144 PMU_PMEVTYPER_EL0(29), 2145 PMU_PMEVTYPER_EL0(30), 2146 /* 2147 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 2148 * in 32bit mode. Here we choose to reset it as zero for consistency. 2149 */ 2150 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper, 2151 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 2152 2153 EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0), 2154 EL2_REG(VMPIDR_EL2, access_rw, reset_unknown, 0), 2155 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 2156 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 2157 EL2_REG(HCR_EL2, access_rw, reset_val, 0), 2158 EL2_REG(MDCR_EL2, access_rw, reset_val, 0), 2159 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_EL2_DEFAULT ), 2160 EL2_REG(HSTR_EL2, access_rw, reset_val, 0), 2161 EL2_REG(HACR_EL2, access_rw, reset_val, 0), 2162 2163 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 2164 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 2165 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 2166 EL2_REG(VTTBR_EL2, access_rw, reset_val, 0), 2167 EL2_REG(VTCR_EL2, access_rw, reset_val, 0), 2168 2169 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 2170 EL2_REG(SPSR_EL2, access_rw, reset_val, 0), 2171 EL2_REG(ELR_EL2, access_rw, reset_val, 0), 2172 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 2173 2174 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 2175 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 2176 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 2177 EL2_REG(ESR_EL2, access_rw, reset_val, 0), 2178 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 2179 2180 EL2_REG(FAR_EL2, access_rw, reset_val, 0), 2181 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 2182 2183 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 2184 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 2185 2186 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 2187 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 2188 { SYS_DESC(SYS_RMR_EL2), trap_undef }, 2189 2190 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 2191 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 2192 2193 EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0), 2194 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 2195 2196 EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078), 2197 EL12_REG(CPACR, access_rw, reset_val, 0), 2198 EL12_REG(TTBR0, access_vm_reg, reset_unknown, 0), 2199 EL12_REG(TTBR1, access_vm_reg, reset_unknown, 0), 2200 EL12_REG(TCR, access_vm_reg, reset_val, 0), 2201 { SYS_DESC(SYS_SPSR_EL12), access_spsr}, 2202 { SYS_DESC(SYS_ELR_EL12), access_elr}, 2203 EL12_REG(AFSR0, access_vm_reg, reset_unknown, 0), 2204 EL12_REG(AFSR1, access_vm_reg, reset_unknown, 0), 2205 EL12_REG(ESR, access_vm_reg, reset_unknown, 0), 2206 EL12_REG(FAR, access_vm_reg, reset_unknown, 0), 2207 EL12_REG(MAIR, access_vm_reg, reset_unknown, 0), 2208 EL12_REG(AMAIR, access_vm_reg, reset_amair_el1, 0), 2209 EL12_REG(VBAR, access_rw, reset_val, 0), 2210 EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0), 2211 EL12_REG(CNTKCTL, access_rw, reset_val, 0), 2212 2213 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 2214 }; 2215 2216 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 2217 struct sys_reg_params *p, 2218 const struct sys_reg_desc *r) 2219 { 2220 if (p->is_write) { 2221 return ignore_write(vcpu, p); 2222 } else { 2223 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 2224 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2225 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); 2226 2227 p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | 2228 (((dfr >> ID_AA64DFR0_EL1_BRPs_SHIFT) & 0xf) << 24) | 2229 (((dfr >> ID_AA64DFR0_EL1_CTX_CMPs_SHIFT) & 0xf) << 20) 2230 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); 2231 return true; 2232 } 2233 } 2234 2235 /* 2236 * AArch32 debug register mappings 2237 * 2238 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 2239 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 2240 * 2241 * None of the other registers share their location, so treat them as 2242 * if they were 64bit. 2243 */ 2244 #define DBG_BCR_BVR_WCR_WVR(n) \ 2245 /* DBGBVRn */ \ 2246 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 2247 /* DBGBCRn */ \ 2248 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 2249 /* DBGWVRn */ \ 2250 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 2251 /* DBGWCRn */ \ 2252 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 2253 2254 #define DBGBXVR(n) \ 2255 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 2256 2257 /* 2258 * Trapped cp14 registers. We generally ignore most of the external 2259 * debug, on the principle that they don't really make sense to a 2260 * guest. Revisit this one day, would this principle change. 2261 */ 2262 static const struct sys_reg_desc cp14_regs[] = { 2263 /* DBGDIDR */ 2264 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 2265 /* DBGDTRRXext */ 2266 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 2267 2268 DBG_BCR_BVR_WCR_WVR(0), 2269 /* DBGDSCRint */ 2270 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 2271 DBG_BCR_BVR_WCR_WVR(1), 2272 /* DBGDCCINT */ 2273 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 2274 /* DBGDSCRext */ 2275 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 2276 DBG_BCR_BVR_WCR_WVR(2), 2277 /* DBGDTR[RT]Xint */ 2278 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 2279 /* DBGDTR[RT]Xext */ 2280 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 2281 DBG_BCR_BVR_WCR_WVR(3), 2282 DBG_BCR_BVR_WCR_WVR(4), 2283 DBG_BCR_BVR_WCR_WVR(5), 2284 /* DBGWFAR */ 2285 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 2286 /* DBGOSECCR */ 2287 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 2288 DBG_BCR_BVR_WCR_WVR(6), 2289 /* DBGVCR */ 2290 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 2291 DBG_BCR_BVR_WCR_WVR(7), 2292 DBG_BCR_BVR_WCR_WVR(8), 2293 DBG_BCR_BVR_WCR_WVR(9), 2294 DBG_BCR_BVR_WCR_WVR(10), 2295 DBG_BCR_BVR_WCR_WVR(11), 2296 DBG_BCR_BVR_WCR_WVR(12), 2297 DBG_BCR_BVR_WCR_WVR(13), 2298 DBG_BCR_BVR_WCR_WVR(14), 2299 DBG_BCR_BVR_WCR_WVR(15), 2300 2301 /* DBGDRAR (32bit) */ 2302 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 2303 2304 DBGBXVR(0), 2305 /* DBGOSLAR */ 2306 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 2307 DBGBXVR(1), 2308 /* DBGOSLSR */ 2309 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 2310 DBGBXVR(2), 2311 DBGBXVR(3), 2312 /* DBGOSDLR */ 2313 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 2314 DBGBXVR(4), 2315 /* DBGPRCR */ 2316 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 2317 DBGBXVR(5), 2318 DBGBXVR(6), 2319 DBGBXVR(7), 2320 DBGBXVR(8), 2321 DBGBXVR(9), 2322 DBGBXVR(10), 2323 DBGBXVR(11), 2324 DBGBXVR(12), 2325 DBGBXVR(13), 2326 DBGBXVR(14), 2327 DBGBXVR(15), 2328 2329 /* DBGDSAR (32bit) */ 2330 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 2331 2332 /* DBGDEVID2 */ 2333 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 2334 /* DBGDEVID1 */ 2335 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 2336 /* DBGDEVID */ 2337 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 2338 /* DBGCLAIMSET */ 2339 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 2340 /* DBGCLAIMCLR */ 2341 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 2342 /* DBGAUTHSTATUS */ 2343 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 2344 }; 2345 2346 /* Trapped cp14 64bit registers */ 2347 static const struct sys_reg_desc cp14_64_regs[] = { 2348 /* DBGDRAR (64bit) */ 2349 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 2350 2351 /* DBGDSAR (64bit) */ 2352 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 2353 }; 2354 2355 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 2356 AA32(_map), \ 2357 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 2358 .visibility = pmu_visibility 2359 2360 /* Macro to expand the PMEVCNTRn register */ 2361 #define PMU_PMEVCNTR(n) \ 2362 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 2363 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 2364 .access = access_pmu_evcntr } 2365 2366 /* Macro to expand the PMEVTYPERn register */ 2367 #define PMU_PMEVTYPER(n) \ 2368 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 2369 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 2370 .access = access_pmu_evtyper } 2371 /* 2372 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 2373 * depending on the way they are accessed (as a 32bit or a 64bit 2374 * register). 2375 */ 2376 static const struct sys_reg_desc cp15_regs[] = { 2377 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 2378 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 2379 /* ACTLR */ 2380 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 2381 /* ACTLR2 */ 2382 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 2383 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2384 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 2385 /* TTBCR */ 2386 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 2387 /* TTBCR2 */ 2388 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 2389 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 2390 /* DFSR */ 2391 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 2392 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 2393 /* ADFSR */ 2394 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 2395 /* AIFSR */ 2396 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 2397 /* DFAR */ 2398 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 2399 /* IFAR */ 2400 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 2401 2402 /* 2403 * DC{C,I,CI}SW operations: 2404 */ 2405 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 2406 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 2407 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 2408 2409 /* PMU */ 2410 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 2411 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 2412 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 2413 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 2414 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 2415 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 2416 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 2417 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 2418 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 2419 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 2420 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 2421 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 2422 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 2423 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 2424 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 2425 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 2426 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 2427 /* PMMIR */ 2428 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 2429 2430 /* PRRR/MAIR0 */ 2431 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 2432 /* NMRR/MAIR1 */ 2433 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 2434 /* AMAIR0 */ 2435 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 2436 /* AMAIR1 */ 2437 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 2438 2439 /* ICC_SRE */ 2440 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 2441 2442 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 2443 2444 /* Arch Tmers */ 2445 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 2446 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 2447 2448 /* PMEVCNTRn */ 2449 PMU_PMEVCNTR(0), 2450 PMU_PMEVCNTR(1), 2451 PMU_PMEVCNTR(2), 2452 PMU_PMEVCNTR(3), 2453 PMU_PMEVCNTR(4), 2454 PMU_PMEVCNTR(5), 2455 PMU_PMEVCNTR(6), 2456 PMU_PMEVCNTR(7), 2457 PMU_PMEVCNTR(8), 2458 PMU_PMEVCNTR(9), 2459 PMU_PMEVCNTR(10), 2460 PMU_PMEVCNTR(11), 2461 PMU_PMEVCNTR(12), 2462 PMU_PMEVCNTR(13), 2463 PMU_PMEVCNTR(14), 2464 PMU_PMEVCNTR(15), 2465 PMU_PMEVCNTR(16), 2466 PMU_PMEVCNTR(17), 2467 PMU_PMEVCNTR(18), 2468 PMU_PMEVCNTR(19), 2469 PMU_PMEVCNTR(20), 2470 PMU_PMEVCNTR(21), 2471 PMU_PMEVCNTR(22), 2472 PMU_PMEVCNTR(23), 2473 PMU_PMEVCNTR(24), 2474 PMU_PMEVCNTR(25), 2475 PMU_PMEVCNTR(26), 2476 PMU_PMEVCNTR(27), 2477 PMU_PMEVCNTR(28), 2478 PMU_PMEVCNTR(29), 2479 PMU_PMEVCNTR(30), 2480 /* PMEVTYPERn */ 2481 PMU_PMEVTYPER(0), 2482 PMU_PMEVTYPER(1), 2483 PMU_PMEVTYPER(2), 2484 PMU_PMEVTYPER(3), 2485 PMU_PMEVTYPER(4), 2486 PMU_PMEVTYPER(5), 2487 PMU_PMEVTYPER(6), 2488 PMU_PMEVTYPER(7), 2489 PMU_PMEVTYPER(8), 2490 PMU_PMEVTYPER(9), 2491 PMU_PMEVTYPER(10), 2492 PMU_PMEVTYPER(11), 2493 PMU_PMEVTYPER(12), 2494 PMU_PMEVTYPER(13), 2495 PMU_PMEVTYPER(14), 2496 PMU_PMEVTYPER(15), 2497 PMU_PMEVTYPER(16), 2498 PMU_PMEVTYPER(17), 2499 PMU_PMEVTYPER(18), 2500 PMU_PMEVTYPER(19), 2501 PMU_PMEVTYPER(20), 2502 PMU_PMEVTYPER(21), 2503 PMU_PMEVTYPER(22), 2504 PMU_PMEVTYPER(23), 2505 PMU_PMEVTYPER(24), 2506 PMU_PMEVTYPER(25), 2507 PMU_PMEVTYPER(26), 2508 PMU_PMEVTYPER(27), 2509 PMU_PMEVTYPER(28), 2510 PMU_PMEVTYPER(29), 2511 PMU_PMEVTYPER(30), 2512 /* PMCCFILTR */ 2513 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 2514 2515 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2516 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2517 2518 /* CCSIDR2 */ 2519 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 2520 2521 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 2522 }; 2523 2524 static const struct sys_reg_desc cp15_64_regs[] = { 2525 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2526 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 2527 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2528 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 2529 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2530 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2531 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2532 }; 2533 2534 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2535 bool is_32) 2536 { 2537 unsigned int i; 2538 2539 for (i = 0; i < n; i++) { 2540 if (!is_32 && table[i].reg && !table[i].reset) { 2541 kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i); 2542 return false; 2543 } 2544 2545 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2546 kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1); 2547 return false; 2548 } 2549 } 2550 2551 return true; 2552 } 2553 2554 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2555 { 2556 kvm_inject_undefined(vcpu); 2557 return 1; 2558 } 2559 2560 static void perform_access(struct kvm_vcpu *vcpu, 2561 struct sys_reg_params *params, 2562 const struct sys_reg_desc *r) 2563 { 2564 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2565 2566 /* Check for regs disabled by runtime config */ 2567 if (sysreg_hidden(vcpu, r)) { 2568 kvm_inject_undefined(vcpu); 2569 return; 2570 } 2571 2572 /* 2573 * Not having an accessor means that we have configured a trap 2574 * that we don't know how to handle. This certainly qualifies 2575 * as a gross bug that should be fixed right away. 2576 */ 2577 BUG_ON(!r->access); 2578 2579 /* Skip instruction if instructed so */ 2580 if (likely(r->access(vcpu, params, r))) 2581 kvm_incr_pc(vcpu); 2582 } 2583 2584 /* 2585 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2586 * call the corresponding trap handler. 2587 * 2588 * @params: pointer to the descriptor of the access 2589 * @table: array of trap descriptors 2590 * @num: size of the trap descriptor array 2591 * 2592 * Return true if the access has been handled, false if not. 2593 */ 2594 static bool emulate_cp(struct kvm_vcpu *vcpu, 2595 struct sys_reg_params *params, 2596 const struct sys_reg_desc *table, 2597 size_t num) 2598 { 2599 const struct sys_reg_desc *r; 2600 2601 if (!table) 2602 return false; /* Not handled */ 2603 2604 r = find_reg(params, table, num); 2605 2606 if (r) { 2607 perform_access(vcpu, params, r); 2608 return true; 2609 } 2610 2611 /* Not handled */ 2612 return false; 2613 } 2614 2615 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2616 struct sys_reg_params *params) 2617 { 2618 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2619 int cp = -1; 2620 2621 switch (esr_ec) { 2622 case ESR_ELx_EC_CP15_32: 2623 case ESR_ELx_EC_CP15_64: 2624 cp = 15; 2625 break; 2626 case ESR_ELx_EC_CP14_MR: 2627 case ESR_ELx_EC_CP14_64: 2628 cp = 14; 2629 break; 2630 default: 2631 WARN_ON(1); 2632 } 2633 2634 print_sys_reg_msg(params, 2635 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2636 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2637 kvm_inject_undefined(vcpu); 2638 } 2639 2640 /** 2641 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2642 * @vcpu: The VCPU pointer 2643 * @run: The kvm_run struct 2644 */ 2645 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2646 const struct sys_reg_desc *global, 2647 size_t nr_global) 2648 { 2649 struct sys_reg_params params; 2650 u64 esr = kvm_vcpu_get_esr(vcpu); 2651 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2652 int Rt2 = (esr >> 10) & 0x1f; 2653 2654 params.CRm = (esr >> 1) & 0xf; 2655 params.is_write = ((esr & 1) == 0); 2656 2657 params.Op0 = 0; 2658 params.Op1 = (esr >> 16) & 0xf; 2659 params.Op2 = 0; 2660 params.CRn = 0; 2661 2662 /* 2663 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2664 * backends between AArch32 and AArch64, we get away with it. 2665 */ 2666 if (params.is_write) { 2667 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2668 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2669 } 2670 2671 /* 2672 * If the table contains a handler, handle the 2673 * potential register operation in the case of a read and return 2674 * with success. 2675 */ 2676 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 2677 /* Split up the value between registers for the read side */ 2678 if (!params.is_write) { 2679 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2680 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2681 } 2682 2683 return 1; 2684 } 2685 2686 unhandled_cp_access(vcpu, ¶ms); 2687 return 1; 2688 } 2689 2690 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 2691 2692 /* 2693 * The CP10 ID registers are architecturally mapped to AArch64 feature 2694 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 2695 * from AArch32. 2696 */ 2697 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 2698 { 2699 u8 reg_id = (esr >> 10) & 0xf; 2700 bool valid; 2701 2702 params->is_write = ((esr & 1) == 0); 2703 params->Op0 = 3; 2704 params->Op1 = 0; 2705 params->CRn = 0; 2706 params->CRm = 3; 2707 2708 /* CP10 ID registers are read-only */ 2709 valid = !params->is_write; 2710 2711 switch (reg_id) { 2712 /* MVFR0 */ 2713 case 0b0111: 2714 params->Op2 = 0; 2715 break; 2716 /* MVFR1 */ 2717 case 0b0110: 2718 params->Op2 = 1; 2719 break; 2720 /* MVFR2 */ 2721 case 0b0101: 2722 params->Op2 = 2; 2723 break; 2724 default: 2725 valid = false; 2726 } 2727 2728 if (valid) 2729 return true; 2730 2731 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 2732 params->is_write ? "write" : "read", reg_id); 2733 return false; 2734 } 2735 2736 /** 2737 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 2738 * VFP Register' from AArch32. 2739 * @vcpu: The vCPU pointer 2740 * 2741 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 2742 * Work out the correct AArch64 system register encoding and reroute to the 2743 * AArch64 system register emulation. 2744 */ 2745 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 2746 { 2747 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2748 u64 esr = kvm_vcpu_get_esr(vcpu); 2749 struct sys_reg_params params; 2750 2751 /* UNDEF on any unhandled register access */ 2752 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 2753 kvm_inject_undefined(vcpu); 2754 return 1; 2755 } 2756 2757 if (emulate_sys_reg(vcpu, ¶ms)) 2758 vcpu_set_reg(vcpu, Rt, params.regval); 2759 2760 return 1; 2761 } 2762 2763 /** 2764 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 2765 * CRn=0, which corresponds to the AArch32 feature 2766 * registers. 2767 * @vcpu: the vCPU pointer 2768 * @params: the system register access parameters. 2769 * 2770 * Our cp15 system register tables do not enumerate the AArch32 feature 2771 * registers. Conveniently, our AArch64 table does, and the AArch32 system 2772 * register encoding can be trivially remapped into the AArch64 for the feature 2773 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 2774 * 2775 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 2776 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 2777 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 2778 * treat undefined registers in this range as RAZ. 2779 */ 2780 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 2781 struct sys_reg_params *params) 2782 { 2783 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2784 2785 /* Treat impossible writes to RO registers as UNDEFINED */ 2786 if (params->is_write) { 2787 unhandled_cp_access(vcpu, params); 2788 return 1; 2789 } 2790 2791 params->Op0 = 3; 2792 2793 /* 2794 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 2795 * Avoid conflicting with future expansion of AArch64 feature registers 2796 * and simply treat them as RAZ here. 2797 */ 2798 if (params->CRm > 3) 2799 params->regval = 0; 2800 else if (!emulate_sys_reg(vcpu, params)) 2801 return 1; 2802 2803 vcpu_set_reg(vcpu, Rt, params->regval); 2804 return 1; 2805 } 2806 2807 /** 2808 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2809 * @vcpu: The VCPU pointer 2810 * @run: The kvm_run struct 2811 */ 2812 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2813 struct sys_reg_params *params, 2814 const struct sys_reg_desc *global, 2815 size_t nr_global) 2816 { 2817 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2818 2819 params->regval = vcpu_get_reg(vcpu, Rt); 2820 2821 if (emulate_cp(vcpu, params, global, nr_global)) { 2822 if (!params->is_write) 2823 vcpu_set_reg(vcpu, Rt, params->regval); 2824 return 1; 2825 } 2826 2827 unhandled_cp_access(vcpu, params); 2828 return 1; 2829 } 2830 2831 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2832 { 2833 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2834 } 2835 2836 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2837 { 2838 struct sys_reg_params params; 2839 2840 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 2841 2842 /* 2843 * Certain AArch32 ID registers are handled by rerouting to the AArch64 2844 * system register table. Registers in the ID range where CRm=0 are 2845 * excluded from this scheme as they do not trivially map into AArch64 2846 * system register encodings. 2847 */ 2848 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 2849 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 2850 2851 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 2852 } 2853 2854 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2855 { 2856 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2857 } 2858 2859 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2860 { 2861 struct sys_reg_params params; 2862 2863 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 2864 2865 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 2866 } 2867 2868 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2869 { 2870 // See ARM DDI 0487E.a, section D12.3.2 2871 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2872 } 2873 2874 /** 2875 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 2876 * @vcpu: The VCPU pointer 2877 * @params: Decoded system register parameters 2878 * 2879 * Return: true if the system register access was successful, false otherwise. 2880 */ 2881 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 2882 struct sys_reg_params *params) 2883 { 2884 const struct sys_reg_desc *r; 2885 2886 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2887 2888 if (likely(r)) { 2889 perform_access(vcpu, params, r); 2890 return true; 2891 } 2892 2893 if (is_imp_def_sys_reg(params)) { 2894 kvm_inject_undefined(vcpu); 2895 } else { 2896 print_sys_reg_msg(params, 2897 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2898 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2899 kvm_inject_undefined(vcpu); 2900 } 2901 return false; 2902 } 2903 2904 /** 2905 * kvm_reset_sys_regs - sets system registers to reset value 2906 * @vcpu: The VCPU pointer 2907 * 2908 * This function finds the right table above and sets the registers on the 2909 * virtual CPU struct to their architecturally defined reset values. 2910 */ 2911 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2912 { 2913 unsigned long i; 2914 2915 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2916 if (sys_reg_descs[i].reset) 2917 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2918 } 2919 2920 /** 2921 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2922 * @vcpu: The VCPU pointer 2923 */ 2924 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2925 { 2926 struct sys_reg_params params; 2927 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2928 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2929 2930 trace_kvm_handle_sys_reg(esr); 2931 2932 params = esr_sys64_to_params(esr); 2933 params.regval = vcpu_get_reg(vcpu, Rt); 2934 2935 if (!emulate_sys_reg(vcpu, ¶ms)) 2936 return 1; 2937 2938 if (!params.is_write) 2939 vcpu_set_reg(vcpu, Rt, params.regval); 2940 return 1; 2941 } 2942 2943 /****************************************************************************** 2944 * Userspace API 2945 *****************************************************************************/ 2946 2947 static bool index_to_params(u64 id, struct sys_reg_params *params) 2948 { 2949 switch (id & KVM_REG_SIZE_MASK) { 2950 case KVM_REG_SIZE_U64: 2951 /* Any unused index bits means it's not valid. */ 2952 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2953 | KVM_REG_ARM_COPROC_MASK 2954 | KVM_REG_ARM64_SYSREG_OP0_MASK 2955 | KVM_REG_ARM64_SYSREG_OP1_MASK 2956 | KVM_REG_ARM64_SYSREG_CRN_MASK 2957 | KVM_REG_ARM64_SYSREG_CRM_MASK 2958 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2959 return false; 2960 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2961 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2962 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2963 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2964 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2965 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2966 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2967 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2968 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2969 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2970 return true; 2971 default: 2972 return false; 2973 } 2974 } 2975 2976 const struct sys_reg_desc *get_reg_by_id(u64 id, 2977 const struct sys_reg_desc table[], 2978 unsigned int num) 2979 { 2980 struct sys_reg_params params; 2981 2982 if (!index_to_params(id, ¶ms)) 2983 return NULL; 2984 2985 return find_reg(¶ms, table, num); 2986 } 2987 2988 /* Decode an index value, and find the sys_reg_desc entry. */ 2989 static const struct sys_reg_desc * 2990 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 2991 const struct sys_reg_desc table[], unsigned int num) 2992 2993 { 2994 const struct sys_reg_desc *r; 2995 2996 /* We only do sys_reg for now. */ 2997 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2998 return NULL; 2999 3000 r = get_reg_by_id(id, table, num); 3001 3002 /* Not saved in the sys_reg array and not otherwise accessible? */ 3003 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 3004 r = NULL; 3005 3006 return r; 3007 } 3008 3009 /* 3010 * These are the invariant sys_reg registers: we let the guest see the 3011 * host versions of these, so they're part of the guest state. 3012 * 3013 * A future CPU may provide a mechanism to present different values to 3014 * the guest, or a future kvm may trap them. 3015 */ 3016 3017 #define FUNCTION_INVARIANT(reg) \ 3018 static void get_##reg(struct kvm_vcpu *v, \ 3019 const struct sys_reg_desc *r) \ 3020 { \ 3021 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 3022 } 3023 3024 FUNCTION_INVARIANT(midr_el1) 3025 FUNCTION_INVARIANT(revidr_el1) 3026 FUNCTION_INVARIANT(aidr_el1) 3027 3028 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 3029 { 3030 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 3031 } 3032 3033 /* ->val is filled in by kvm_sys_reg_table_init() */ 3034 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 3035 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 3036 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 3037 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 3038 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 3039 }; 3040 3041 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 3042 { 3043 const struct sys_reg_desc *r; 3044 3045 r = get_reg_by_id(id, invariant_sys_regs, 3046 ARRAY_SIZE(invariant_sys_regs)); 3047 if (!r) 3048 return -ENOENT; 3049 3050 return put_user(r->val, uaddr); 3051 } 3052 3053 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 3054 { 3055 const struct sys_reg_desc *r; 3056 u64 val; 3057 3058 r = get_reg_by_id(id, invariant_sys_regs, 3059 ARRAY_SIZE(invariant_sys_regs)); 3060 if (!r) 3061 return -ENOENT; 3062 3063 if (get_user(val, uaddr)) 3064 return -EFAULT; 3065 3066 /* This is what we mean by invariant: you can't change it. */ 3067 if (r->val != val) 3068 return -EINVAL; 3069 3070 return 0; 3071 } 3072 3073 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 3074 { 3075 u32 val; 3076 u32 __user *uval = uaddr; 3077 3078 /* Fail if we have unknown bits set. */ 3079 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 3080 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 3081 return -ENOENT; 3082 3083 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 3084 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 3085 if (KVM_REG_SIZE(id) != 4) 3086 return -ENOENT; 3087 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 3088 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 3089 if (val >= CSSELR_MAX) 3090 return -ENOENT; 3091 3092 return put_user(get_ccsidr(vcpu, val), uval); 3093 default: 3094 return -ENOENT; 3095 } 3096 } 3097 3098 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 3099 { 3100 u32 val, newval; 3101 u32 __user *uval = uaddr; 3102 3103 /* Fail if we have unknown bits set. */ 3104 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 3105 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 3106 return -ENOENT; 3107 3108 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 3109 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 3110 if (KVM_REG_SIZE(id) != 4) 3111 return -ENOENT; 3112 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 3113 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 3114 if (val >= CSSELR_MAX) 3115 return -ENOENT; 3116 3117 if (get_user(newval, uval)) 3118 return -EFAULT; 3119 3120 return set_ccsidr(vcpu, val, newval); 3121 default: 3122 return -ENOENT; 3123 } 3124 } 3125 3126 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 3127 const struct sys_reg_desc table[], unsigned int num) 3128 { 3129 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 3130 const struct sys_reg_desc *r; 3131 u64 val; 3132 int ret; 3133 3134 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 3135 if (!r || sysreg_hidden_user(vcpu, r)) 3136 return -ENOENT; 3137 3138 if (r->get_user) { 3139 ret = (r->get_user)(vcpu, r, &val); 3140 } else { 3141 val = __vcpu_sys_reg(vcpu, r->reg); 3142 ret = 0; 3143 } 3144 3145 if (!ret) 3146 ret = put_user(val, uaddr); 3147 3148 return ret; 3149 } 3150 3151 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 3152 { 3153 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 3154 int err; 3155 3156 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 3157 return demux_c15_get(vcpu, reg->id, uaddr); 3158 3159 err = get_invariant_sys_reg(reg->id, uaddr); 3160 if (err != -ENOENT) 3161 return err; 3162 3163 return kvm_sys_reg_get_user(vcpu, reg, 3164 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3165 } 3166 3167 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 3168 const struct sys_reg_desc table[], unsigned int num) 3169 { 3170 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 3171 const struct sys_reg_desc *r; 3172 u64 val; 3173 int ret; 3174 3175 if (get_user(val, uaddr)) 3176 return -EFAULT; 3177 3178 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 3179 if (!r || sysreg_hidden_user(vcpu, r)) 3180 return -ENOENT; 3181 3182 if (sysreg_user_write_ignore(vcpu, r)) 3183 return 0; 3184 3185 if (r->set_user) { 3186 ret = (r->set_user)(vcpu, r, val); 3187 } else { 3188 __vcpu_sys_reg(vcpu, r->reg) = val; 3189 ret = 0; 3190 } 3191 3192 return ret; 3193 } 3194 3195 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 3196 { 3197 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 3198 int err; 3199 3200 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 3201 return demux_c15_set(vcpu, reg->id, uaddr); 3202 3203 err = set_invariant_sys_reg(reg->id, uaddr); 3204 if (err != -ENOENT) 3205 return err; 3206 3207 return kvm_sys_reg_set_user(vcpu, reg, 3208 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 3209 } 3210 3211 static unsigned int num_demux_regs(void) 3212 { 3213 return CSSELR_MAX; 3214 } 3215 3216 static int write_demux_regids(u64 __user *uindices) 3217 { 3218 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 3219 unsigned int i; 3220 3221 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 3222 for (i = 0; i < CSSELR_MAX; i++) { 3223 if (put_user(val | i, uindices)) 3224 return -EFAULT; 3225 uindices++; 3226 } 3227 return 0; 3228 } 3229 3230 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 3231 { 3232 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 3233 KVM_REG_ARM64_SYSREG | 3234 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 3235 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 3236 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 3237 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 3238 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 3239 } 3240 3241 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 3242 { 3243 if (!*uind) 3244 return true; 3245 3246 if (put_user(sys_reg_to_index(reg), *uind)) 3247 return false; 3248 3249 (*uind)++; 3250 return true; 3251 } 3252 3253 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 3254 const struct sys_reg_desc *rd, 3255 u64 __user **uind, 3256 unsigned int *total) 3257 { 3258 /* 3259 * Ignore registers we trap but don't save, 3260 * and for which no custom user accessor is provided. 3261 */ 3262 if (!(rd->reg || rd->get_user)) 3263 return 0; 3264 3265 if (sysreg_hidden_user(vcpu, rd)) 3266 return 0; 3267 3268 if (!copy_reg_to_user(rd, uind)) 3269 return -EFAULT; 3270 3271 (*total)++; 3272 return 0; 3273 } 3274 3275 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 3276 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 3277 { 3278 const struct sys_reg_desc *i2, *end2; 3279 unsigned int total = 0; 3280 int err; 3281 3282 i2 = sys_reg_descs; 3283 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 3284 3285 while (i2 != end2) { 3286 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 3287 if (err) 3288 return err; 3289 } 3290 return total; 3291 } 3292 3293 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 3294 { 3295 return ARRAY_SIZE(invariant_sys_regs) 3296 + num_demux_regs() 3297 + walk_sys_regs(vcpu, (u64 __user *)NULL); 3298 } 3299 3300 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 3301 { 3302 unsigned int i; 3303 int err; 3304 3305 /* Then give them all the invariant registers' indices. */ 3306 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 3307 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 3308 return -EFAULT; 3309 uindices++; 3310 } 3311 3312 err = walk_sys_regs(vcpu, uindices); 3313 if (err < 0) 3314 return err; 3315 uindices += err; 3316 3317 return write_demux_regids(uindices); 3318 } 3319 3320 int __init kvm_sys_reg_table_init(void) 3321 { 3322 bool valid = true; 3323 unsigned int i; 3324 3325 /* Make sure tables are unique and in order. */ 3326 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 3327 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 3328 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 3329 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 3330 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 3331 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 3332 3333 if (!valid) 3334 return -EINVAL; 3335 3336 /* We abuse the reset function to overwrite the table itself. */ 3337 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 3338 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 3339 3340 return 0; 3341 } 3342