1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bsearch.h> 13 #include <linux/kvm_host.h> 14 #include <linux/mm.h> 15 #include <linux/printk.h> 16 #include <linux/uaccess.h> 17 18 #include <asm/cacheflush.h> 19 #include <asm/cputype.h> 20 #include <asm/debug-monitors.h> 21 #include <asm/esr.h> 22 #include <asm/kvm_arm.h> 23 #include <asm/kvm_coproc.h> 24 #include <asm/kvm_emulate.h> 25 #include <asm/kvm_hyp.h> 26 #include <asm/kvm_mmu.h> 27 #include <asm/perf_event.h> 28 #include <asm/sysreg.h> 29 30 #include <trace/events/kvm.h> 31 32 #include "sys_regs.h" 33 34 #include "trace.h" 35 36 /* 37 * All of this file is extremely similar to the ARM coproc.c, but the 38 * types are different. My gut feeling is that it should be pretty 39 * easy to merge, but that would be an ABI breakage -- again. VFP 40 * would also need to be abstracted. 41 * 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static bool read_from_write_only(struct kvm_vcpu *vcpu, 48 struct sys_reg_params *params, 49 const struct sys_reg_desc *r) 50 { 51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 52 print_sys_reg_instr(params); 53 kvm_inject_undefined(vcpu); 54 return false; 55 } 56 57 static bool write_to_read_only(struct kvm_vcpu *vcpu, 58 struct sys_reg_params *params, 59 const struct sys_reg_desc *r) 60 { 61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 62 print_sys_reg_instr(params); 63 kvm_inject_undefined(vcpu); 64 return false; 65 } 66 67 static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 68 { 69 /* 70 * System registers listed in the switch are not saved on every 71 * exit from the guest but are only saved on vcpu_put. 72 * 73 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 74 * should never be listed below, because the guest cannot modify its 75 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 76 * thread when emulating cross-VCPU communication. 77 */ 78 switch (reg) { 79 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break; 80 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 81 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 82 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 83 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 84 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 85 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 86 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 87 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 88 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 89 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 90 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 91 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 92 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 93 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 94 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 95 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 96 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 97 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 98 case PAR_EL1: *val = read_sysreg_s(SYS_PAR_EL1); break; 99 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 100 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 101 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 102 default: return false; 103 } 104 105 return true; 106 } 107 108 static bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 109 { 110 /* 111 * System registers listed in the switch are not restored on every 112 * entry to the guest but are only restored on vcpu_load. 113 * 114 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 115 * should never be listed below, because the MPIDR should only be set 116 * once, before running the VCPU, and never changed later. 117 */ 118 switch (reg) { 119 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; 120 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 121 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 122 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 123 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 124 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 125 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 126 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 127 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 128 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 129 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 130 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 131 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 132 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 133 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 134 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 135 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 136 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 137 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 138 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 139 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 140 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 141 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 142 default: return false; 143 } 144 145 return true; 146 } 147 148 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 149 { 150 u64 val = 0x8badf00d8badf00d; 151 152 if (vcpu->arch.sysregs_loaded_on_cpu && 153 __vcpu_read_sys_reg_from_cpu(reg, &val)) 154 return val; 155 156 return __vcpu_sys_reg(vcpu, reg); 157 } 158 159 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 160 { 161 if (vcpu->arch.sysregs_loaded_on_cpu && 162 __vcpu_write_sys_reg_to_cpu(val, reg)) 163 return; 164 165 __vcpu_sys_reg(vcpu, reg) = val; 166 } 167 168 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ 169 static u32 cache_levels; 170 171 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 172 #define CSSELR_MAX 12 173 174 /* Which cache CCSIDR represents depends on CSSELR value. */ 175 static u32 get_ccsidr(u32 csselr) 176 { 177 u32 ccsidr; 178 179 /* Make sure noone else changes CSSELR during this! */ 180 local_irq_disable(); 181 write_sysreg(csselr, csselr_el1); 182 isb(); 183 ccsidr = read_sysreg(ccsidr_el1); 184 local_irq_enable(); 185 186 return ccsidr; 187 } 188 189 /* 190 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 191 */ 192 static bool access_dcsw(struct kvm_vcpu *vcpu, 193 struct sys_reg_params *p, 194 const struct sys_reg_desc *r) 195 { 196 if (!p->is_write) 197 return read_from_write_only(vcpu, p, r); 198 199 /* 200 * Only track S/W ops if we don't have FWB. It still indicates 201 * that the guest is a bit broken (S/W operations should only 202 * be done by firmware, knowing that there is only a single 203 * CPU left in the system, and certainly not from non-secure 204 * software). 205 */ 206 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 207 kvm_set_way_flush(vcpu); 208 209 return true; 210 } 211 212 /* 213 * Generic accessor for VM registers. Only called as long as HCR_TVM 214 * is set. If the guest enables the MMU, we stop trapping the VM 215 * sys_regs and leave it in complete control of the caches. 216 */ 217 static bool access_vm_reg(struct kvm_vcpu *vcpu, 218 struct sys_reg_params *p, 219 const struct sys_reg_desc *r) 220 { 221 bool was_enabled = vcpu_has_cache_enabled(vcpu); 222 u64 val; 223 int reg = r->reg; 224 225 BUG_ON(!p->is_write); 226 227 /* See the 32bit mapping in kvm_host.h */ 228 if (p->is_aarch32) 229 reg = r->reg / 2; 230 231 if (!p->is_aarch32 || !p->is_32bit) { 232 val = p->regval; 233 } else { 234 val = vcpu_read_sys_reg(vcpu, reg); 235 if (r->reg % 2) 236 val = (p->regval << 32) | (u64)lower_32_bits(val); 237 else 238 val = ((u64)upper_32_bits(val) << 32) | 239 lower_32_bits(p->regval); 240 } 241 vcpu_write_sys_reg(vcpu, val, reg); 242 243 kvm_toggle_cache(vcpu, was_enabled); 244 return true; 245 } 246 247 static bool access_actlr(struct kvm_vcpu *vcpu, 248 struct sys_reg_params *p, 249 const struct sys_reg_desc *r) 250 { 251 if (p->is_write) 252 return ignore_write(vcpu, p); 253 254 p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1); 255 256 if (p->is_aarch32) { 257 if (r->Op2 & 2) 258 p->regval = upper_32_bits(p->regval); 259 else 260 p->regval = lower_32_bits(p->regval); 261 } 262 263 return true; 264 } 265 266 /* 267 * Trap handler for the GICv3 SGI generation system register. 268 * Forward the request to the VGIC emulation. 269 * The cp15_64 code makes sure this automatically works 270 * for both AArch64 and AArch32 accesses. 271 */ 272 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 273 struct sys_reg_params *p, 274 const struct sys_reg_desc *r) 275 { 276 bool g1; 277 278 if (!p->is_write) 279 return read_from_write_only(vcpu, p, r); 280 281 /* 282 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 283 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 284 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 285 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 286 * group. 287 */ 288 if (p->is_aarch32) { 289 switch (p->Op1) { 290 default: /* Keep GCC quiet */ 291 case 0: /* ICC_SGI1R */ 292 g1 = true; 293 break; 294 case 1: /* ICC_ASGI1R */ 295 case 2: /* ICC_SGI0R */ 296 g1 = false; 297 break; 298 } 299 } else { 300 switch (p->Op2) { 301 default: /* Keep GCC quiet */ 302 case 5: /* ICC_SGI1R_EL1 */ 303 g1 = true; 304 break; 305 case 6: /* ICC_ASGI1R_EL1 */ 306 case 7: /* ICC_SGI0R_EL1 */ 307 g1 = false; 308 break; 309 } 310 } 311 312 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 313 314 return true; 315 } 316 317 static bool access_gic_sre(struct kvm_vcpu *vcpu, 318 struct sys_reg_params *p, 319 const struct sys_reg_desc *r) 320 { 321 if (p->is_write) 322 return ignore_write(vcpu, p); 323 324 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 325 return true; 326 } 327 328 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 329 struct sys_reg_params *p, 330 const struct sys_reg_desc *r) 331 { 332 if (p->is_write) 333 return ignore_write(vcpu, p); 334 else 335 return read_zero(vcpu, p); 336 } 337 338 /* 339 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 340 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 341 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 342 * treat it separately. 343 */ 344 static bool trap_loregion(struct kvm_vcpu *vcpu, 345 struct sys_reg_params *p, 346 const struct sys_reg_desc *r) 347 { 348 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 349 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1, 350 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 351 352 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { 353 kvm_inject_undefined(vcpu); 354 return false; 355 } 356 357 if (p->is_write && sr == SYS_LORID_EL1) 358 return write_to_read_only(vcpu, p, r); 359 360 return trap_raz_wi(vcpu, p, r); 361 } 362 363 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 364 struct sys_reg_params *p, 365 const struct sys_reg_desc *r) 366 { 367 if (p->is_write) { 368 return ignore_write(vcpu, p); 369 } else { 370 p->regval = (1 << 3); 371 return true; 372 } 373 } 374 375 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 376 struct sys_reg_params *p, 377 const struct sys_reg_desc *r) 378 { 379 if (p->is_write) { 380 return ignore_write(vcpu, p); 381 } else { 382 p->regval = read_sysreg(dbgauthstatus_el1); 383 return true; 384 } 385 } 386 387 /* 388 * We want to avoid world-switching all the DBG registers all the 389 * time: 390 * 391 * - If we've touched any debug register, it is likely that we're 392 * going to touch more of them. It then makes sense to disable the 393 * traps and start doing the save/restore dance 394 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 395 * then mandatory to save/restore the registers, as the guest 396 * depends on them. 397 * 398 * For this, we use a DIRTY bit, indicating the guest has modified the 399 * debug registers, used as follow: 400 * 401 * On guest entry: 402 * - If the dirty bit is set (because we're coming back from trapping), 403 * disable the traps, save host registers, restore guest registers. 404 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 405 * set the dirty bit, disable the traps, save host registers, 406 * restore guest registers. 407 * - Otherwise, enable the traps 408 * 409 * On guest exit: 410 * - If the dirty bit is set, save guest registers, restore host 411 * registers and clear the dirty bit. This ensure that the host can 412 * now use the debug registers. 413 */ 414 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 415 struct sys_reg_params *p, 416 const struct sys_reg_desc *r) 417 { 418 if (p->is_write) { 419 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 420 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 421 } else { 422 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 423 } 424 425 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 426 427 return true; 428 } 429 430 /* 431 * reg_to_dbg/dbg_to_reg 432 * 433 * A 32 bit write to a debug register leave top bits alone 434 * A 32 bit read from a debug register only returns the bottom bits 435 * 436 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the 437 * hyp.S code switches between host and guest values in future. 438 */ 439 static void reg_to_dbg(struct kvm_vcpu *vcpu, 440 struct sys_reg_params *p, 441 u64 *dbg_reg) 442 { 443 u64 val = p->regval; 444 445 if (p->is_32bit) { 446 val &= 0xffffffffUL; 447 val |= ((*dbg_reg >> 32) << 32); 448 } 449 450 *dbg_reg = val; 451 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 452 } 453 454 static void dbg_to_reg(struct kvm_vcpu *vcpu, 455 struct sys_reg_params *p, 456 u64 *dbg_reg) 457 { 458 p->regval = *dbg_reg; 459 if (p->is_32bit) 460 p->regval &= 0xffffffffUL; 461 } 462 463 static bool trap_bvr(struct kvm_vcpu *vcpu, 464 struct sys_reg_params *p, 465 const struct sys_reg_desc *rd) 466 { 467 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 468 469 if (p->is_write) 470 reg_to_dbg(vcpu, p, dbg_reg); 471 else 472 dbg_to_reg(vcpu, p, dbg_reg); 473 474 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 475 476 return true; 477 } 478 479 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 480 const struct kvm_one_reg *reg, void __user *uaddr) 481 { 482 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 483 484 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 485 return -EFAULT; 486 return 0; 487 } 488 489 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 490 const struct kvm_one_reg *reg, void __user *uaddr) 491 { 492 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 493 494 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 495 return -EFAULT; 496 return 0; 497 } 498 499 static void reset_bvr(struct kvm_vcpu *vcpu, 500 const struct sys_reg_desc *rd) 501 { 502 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; 503 } 504 505 static bool trap_bcr(struct kvm_vcpu *vcpu, 506 struct sys_reg_params *p, 507 const struct sys_reg_desc *rd) 508 { 509 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 510 511 if (p->is_write) 512 reg_to_dbg(vcpu, p, dbg_reg); 513 else 514 dbg_to_reg(vcpu, p, dbg_reg); 515 516 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 517 518 return true; 519 } 520 521 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 522 const struct kvm_one_reg *reg, void __user *uaddr) 523 { 524 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 525 526 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 527 return -EFAULT; 528 529 return 0; 530 } 531 532 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 533 const struct kvm_one_reg *reg, void __user *uaddr) 534 { 535 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 536 537 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 538 return -EFAULT; 539 return 0; 540 } 541 542 static void reset_bcr(struct kvm_vcpu *vcpu, 543 const struct sys_reg_desc *rd) 544 { 545 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; 546 } 547 548 static bool trap_wvr(struct kvm_vcpu *vcpu, 549 struct sys_reg_params *p, 550 const struct sys_reg_desc *rd) 551 { 552 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 553 554 if (p->is_write) 555 reg_to_dbg(vcpu, p, dbg_reg); 556 else 557 dbg_to_reg(vcpu, p, dbg_reg); 558 559 trace_trap_reg(__func__, rd->reg, p->is_write, 560 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]); 561 562 return true; 563 } 564 565 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 566 const struct kvm_one_reg *reg, void __user *uaddr) 567 { 568 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 569 570 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 571 return -EFAULT; 572 return 0; 573 } 574 575 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 576 const struct kvm_one_reg *reg, void __user *uaddr) 577 { 578 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 579 580 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 581 return -EFAULT; 582 return 0; 583 } 584 585 static void reset_wvr(struct kvm_vcpu *vcpu, 586 const struct sys_reg_desc *rd) 587 { 588 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; 589 } 590 591 static bool trap_wcr(struct kvm_vcpu *vcpu, 592 struct sys_reg_params *p, 593 const struct sys_reg_desc *rd) 594 { 595 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 596 597 if (p->is_write) 598 reg_to_dbg(vcpu, p, dbg_reg); 599 else 600 dbg_to_reg(vcpu, p, dbg_reg); 601 602 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 603 604 return true; 605 } 606 607 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 608 const struct kvm_one_reg *reg, void __user *uaddr) 609 { 610 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 611 612 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 613 return -EFAULT; 614 return 0; 615 } 616 617 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 618 const struct kvm_one_reg *reg, void __user *uaddr) 619 { 620 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 621 622 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 623 return -EFAULT; 624 return 0; 625 } 626 627 static void reset_wcr(struct kvm_vcpu *vcpu, 628 const struct sys_reg_desc *rd) 629 { 630 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; 631 } 632 633 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 634 { 635 u64 amair = read_sysreg(amair_el1); 636 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 637 } 638 639 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 640 { 641 u64 actlr = read_sysreg(actlr_el1); 642 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 643 } 644 645 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 646 { 647 u64 mpidr; 648 649 /* 650 * Map the vcpu_id into the first three affinity level fields of 651 * the MPIDR. We limit the number of VCPUs in level 0 due to a 652 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 653 * of the GICv3 to be able to address each CPU directly when 654 * sending IPIs. 655 */ 656 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 657 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 658 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 659 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 660 } 661 662 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 663 { 664 u64 pmcr, val; 665 666 pmcr = read_sysreg(pmcr_el0); 667 /* 668 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN 669 * except PMCR.E resetting to zero. 670 */ 671 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) 672 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); 673 if (!system_supports_32bit_el0()) 674 val |= ARMV8_PMU_PMCR_LC; 675 __vcpu_sys_reg(vcpu, r->reg) = val; 676 } 677 678 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 679 { 680 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 681 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 682 683 if (!enabled) 684 kvm_inject_undefined(vcpu); 685 686 return !enabled; 687 } 688 689 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 690 { 691 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 692 } 693 694 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 695 { 696 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 697 } 698 699 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 700 { 701 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 702 } 703 704 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 705 { 706 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 707 } 708 709 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 710 const struct sys_reg_desc *r) 711 { 712 u64 val; 713 714 if (!kvm_arm_pmu_v3_ready(vcpu)) 715 return trap_raz_wi(vcpu, p, r); 716 717 if (pmu_access_el0_disabled(vcpu)) 718 return false; 719 720 if (p->is_write) { 721 /* Only update writeable bits of PMCR */ 722 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 723 val &= ~ARMV8_PMU_PMCR_MASK; 724 val |= p->regval & ARMV8_PMU_PMCR_MASK; 725 if (!system_supports_32bit_el0()) 726 val |= ARMV8_PMU_PMCR_LC; 727 __vcpu_sys_reg(vcpu, PMCR_EL0) = val; 728 kvm_pmu_handle_pmcr(vcpu, val); 729 kvm_vcpu_pmu_restore_guest(vcpu); 730 } else { 731 /* PMCR.P & PMCR.C are RAZ */ 732 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 733 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 734 p->regval = val; 735 } 736 737 return true; 738 } 739 740 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 741 const struct sys_reg_desc *r) 742 { 743 if (!kvm_arm_pmu_v3_ready(vcpu)) 744 return trap_raz_wi(vcpu, p, r); 745 746 if (pmu_access_event_counter_el0_disabled(vcpu)) 747 return false; 748 749 if (p->is_write) 750 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 751 else 752 /* return PMSELR.SEL field */ 753 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 754 & ARMV8_PMU_COUNTER_MASK; 755 756 return true; 757 } 758 759 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 760 const struct sys_reg_desc *r) 761 { 762 u64 pmceid; 763 764 if (!kvm_arm_pmu_v3_ready(vcpu)) 765 return trap_raz_wi(vcpu, p, r); 766 767 BUG_ON(p->is_write); 768 769 if (pmu_access_el0_disabled(vcpu)) 770 return false; 771 772 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 773 774 p->regval = pmceid; 775 776 return true; 777 } 778 779 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 780 { 781 u64 pmcr, val; 782 783 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 784 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 785 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 786 kvm_inject_undefined(vcpu); 787 return false; 788 } 789 790 return true; 791 } 792 793 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 794 struct sys_reg_params *p, 795 const struct sys_reg_desc *r) 796 { 797 u64 idx; 798 799 if (!kvm_arm_pmu_v3_ready(vcpu)) 800 return trap_raz_wi(vcpu, p, r); 801 802 if (r->CRn == 9 && r->CRm == 13) { 803 if (r->Op2 == 2) { 804 /* PMXEVCNTR_EL0 */ 805 if (pmu_access_event_counter_el0_disabled(vcpu)) 806 return false; 807 808 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 809 & ARMV8_PMU_COUNTER_MASK; 810 } else if (r->Op2 == 0) { 811 /* PMCCNTR_EL0 */ 812 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 813 return false; 814 815 idx = ARMV8_PMU_CYCLE_IDX; 816 } else { 817 return false; 818 } 819 } else if (r->CRn == 0 && r->CRm == 9) { 820 /* PMCCNTR */ 821 if (pmu_access_event_counter_el0_disabled(vcpu)) 822 return false; 823 824 idx = ARMV8_PMU_CYCLE_IDX; 825 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 826 /* PMEVCNTRn_EL0 */ 827 if (pmu_access_event_counter_el0_disabled(vcpu)) 828 return false; 829 830 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 831 } else { 832 return false; 833 } 834 835 if (!pmu_counter_idx_valid(vcpu, idx)) 836 return false; 837 838 if (p->is_write) { 839 if (pmu_access_el0_disabled(vcpu)) 840 return false; 841 842 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 843 } else { 844 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 845 } 846 847 return true; 848 } 849 850 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 851 const struct sys_reg_desc *r) 852 { 853 u64 idx, reg; 854 855 if (!kvm_arm_pmu_v3_ready(vcpu)) 856 return trap_raz_wi(vcpu, p, r); 857 858 if (pmu_access_el0_disabled(vcpu)) 859 return false; 860 861 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 862 /* PMXEVTYPER_EL0 */ 863 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 864 reg = PMEVTYPER0_EL0 + idx; 865 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 866 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 867 if (idx == ARMV8_PMU_CYCLE_IDX) 868 reg = PMCCFILTR_EL0; 869 else 870 /* PMEVTYPERn_EL0 */ 871 reg = PMEVTYPER0_EL0 + idx; 872 } else { 873 BUG(); 874 } 875 876 if (!pmu_counter_idx_valid(vcpu, idx)) 877 return false; 878 879 if (p->is_write) { 880 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 881 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 882 kvm_vcpu_pmu_restore_guest(vcpu); 883 } else { 884 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 885 } 886 887 return true; 888 } 889 890 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 891 const struct sys_reg_desc *r) 892 { 893 u64 val, mask; 894 895 if (!kvm_arm_pmu_v3_ready(vcpu)) 896 return trap_raz_wi(vcpu, p, r); 897 898 if (pmu_access_el0_disabled(vcpu)) 899 return false; 900 901 mask = kvm_pmu_valid_counter_mask(vcpu); 902 if (p->is_write) { 903 val = p->regval & mask; 904 if (r->Op2 & 0x1) { 905 /* accessing PMCNTENSET_EL0 */ 906 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 907 kvm_pmu_enable_counter_mask(vcpu, val); 908 kvm_vcpu_pmu_restore_guest(vcpu); 909 } else { 910 /* accessing PMCNTENCLR_EL0 */ 911 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 912 kvm_pmu_disable_counter_mask(vcpu, val); 913 } 914 } else { 915 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; 916 } 917 918 return true; 919 } 920 921 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 922 const struct sys_reg_desc *r) 923 { 924 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 925 926 if (!kvm_arm_pmu_v3_ready(vcpu)) 927 return trap_raz_wi(vcpu, p, r); 928 929 if (!vcpu_mode_priv(vcpu)) { 930 kvm_inject_undefined(vcpu); 931 return false; 932 } 933 934 if (p->is_write) { 935 u64 val = p->regval & mask; 936 937 if (r->Op2 & 0x1) 938 /* accessing PMINTENSET_EL1 */ 939 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 940 else 941 /* accessing PMINTENCLR_EL1 */ 942 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 943 } else { 944 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; 945 } 946 947 return true; 948 } 949 950 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 951 const struct sys_reg_desc *r) 952 { 953 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 954 955 if (!kvm_arm_pmu_v3_ready(vcpu)) 956 return trap_raz_wi(vcpu, p, r); 957 958 if (pmu_access_el0_disabled(vcpu)) 959 return false; 960 961 if (p->is_write) { 962 if (r->CRm & 0x2) 963 /* accessing PMOVSSET_EL0 */ 964 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 965 else 966 /* accessing PMOVSCLR_EL0 */ 967 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 968 } else { 969 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; 970 } 971 972 return true; 973 } 974 975 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 976 const struct sys_reg_desc *r) 977 { 978 u64 mask; 979 980 if (!kvm_arm_pmu_v3_ready(vcpu)) 981 return trap_raz_wi(vcpu, p, r); 982 983 if (!p->is_write) 984 return read_from_write_only(vcpu, p, r); 985 986 if (pmu_write_swinc_el0_disabled(vcpu)) 987 return false; 988 989 mask = kvm_pmu_valid_counter_mask(vcpu); 990 kvm_pmu_software_increment(vcpu, p->regval & mask); 991 return true; 992 } 993 994 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 995 const struct sys_reg_desc *r) 996 { 997 if (!kvm_arm_pmu_v3_ready(vcpu)) 998 return trap_raz_wi(vcpu, p, r); 999 1000 if (p->is_write) { 1001 if (!vcpu_mode_priv(vcpu)) { 1002 kvm_inject_undefined(vcpu); 1003 return false; 1004 } 1005 1006 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1007 p->regval & ARMV8_PMU_USERENR_MASK; 1008 } else { 1009 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1010 & ARMV8_PMU_USERENR_MASK; 1011 } 1012 1013 return true; 1014 } 1015 1016 #define reg_to_encoding(x) \ 1017 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \ 1018 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2); 1019 1020 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1021 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1022 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1023 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1024 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1025 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1026 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1027 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1028 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1029 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1030 1031 /* Macro to expand the PMEVCNTRn_EL0 register */ 1032 #define PMU_PMEVCNTR_EL0(n) \ 1033 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \ 1034 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), } 1035 1036 /* Macro to expand the PMEVTYPERn_EL0 register */ 1037 #define PMU_PMEVTYPER_EL0(n) \ 1038 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \ 1039 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), } 1040 1041 static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1042 const struct sys_reg_desc *r) 1043 { 1044 kvm_inject_undefined(vcpu); 1045 1046 return false; 1047 } 1048 1049 /* Macro to expand the AMU counter and type registers*/ 1050 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu } 1051 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), access_amu } 1052 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu } 1053 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), access_amu } 1054 1055 static bool trap_ptrauth(struct kvm_vcpu *vcpu, 1056 struct sys_reg_params *p, 1057 const struct sys_reg_desc *rd) 1058 { 1059 /* 1060 * If we land here, that is because we didn't fixup the access on exit 1061 * by allowing the PtrAuth sysregs. The only way this happens is when 1062 * the guest does not have PtrAuth support enabled. 1063 */ 1064 kvm_inject_undefined(vcpu); 1065 1066 return false; 1067 } 1068 1069 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1070 const struct sys_reg_desc *rd) 1071 { 1072 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN_USER | REG_HIDDEN_GUEST; 1073 } 1074 1075 #define __PTRAUTH_KEY(k) \ 1076 { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \ 1077 .visibility = ptrauth_visibility} 1078 1079 #define PTRAUTH_KEY(k) \ 1080 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1081 __PTRAUTH_KEY(k ## KEYHI_EL1) 1082 1083 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1084 struct sys_reg_params *p, 1085 const struct sys_reg_desc *r) 1086 { 1087 enum kvm_arch_timers tmr; 1088 enum kvm_arch_timer_regs treg; 1089 u64 reg = reg_to_encoding(r); 1090 1091 switch (reg) { 1092 case SYS_CNTP_TVAL_EL0: 1093 case SYS_AARCH32_CNTP_TVAL: 1094 tmr = TIMER_PTIMER; 1095 treg = TIMER_REG_TVAL; 1096 break; 1097 case SYS_CNTP_CTL_EL0: 1098 case SYS_AARCH32_CNTP_CTL: 1099 tmr = TIMER_PTIMER; 1100 treg = TIMER_REG_CTL; 1101 break; 1102 case SYS_CNTP_CVAL_EL0: 1103 case SYS_AARCH32_CNTP_CVAL: 1104 tmr = TIMER_PTIMER; 1105 treg = TIMER_REG_CVAL; 1106 break; 1107 default: 1108 BUG(); 1109 } 1110 1111 if (p->is_write) 1112 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1113 else 1114 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1115 1116 return true; 1117 } 1118 1119 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1120 static u64 read_id_reg(const struct kvm_vcpu *vcpu, 1121 struct sys_reg_desc const *r, bool raz) 1122 { 1123 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, 1124 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 1125 u64 val = raz ? 0 : read_sanitised_ftr_reg(id); 1126 1127 if (id == SYS_ID_AA64PFR0_EL1) { 1128 if (!vcpu_has_sve(vcpu)) 1129 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); 1130 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); 1131 if (!(val & (0xfUL << ID_AA64PFR0_CSV2_SHIFT)) && 1132 arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) 1133 val |= (1UL << ID_AA64PFR0_CSV2_SHIFT); 1134 } else if (id == SYS_ID_AA64PFR1_EL1) { 1135 val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT); 1136 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { 1137 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | 1138 (0xfUL << ID_AA64ISAR1_API_SHIFT) | 1139 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | 1140 (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); 1141 } else if (id == SYS_ID_AA64DFR0_EL1) { 1142 /* Limit guests to PMUv3 for ARMv8.1 */ 1143 val = cpuid_feature_cap_perfmon_field(val, 1144 ID_AA64DFR0_PMUVER_SHIFT, 1145 ID_AA64DFR0_PMUVER_8_1); 1146 } else if (id == SYS_ID_DFR0_EL1) { 1147 /* Limit guests to PMUv3 for ARMv8.1 */ 1148 val = cpuid_feature_cap_perfmon_field(val, 1149 ID_DFR0_PERFMON_SHIFT, 1150 ID_DFR0_PERFMON_8_1); 1151 } 1152 1153 return val; 1154 } 1155 1156 /* cpufeature ID register access trap handlers */ 1157 1158 static bool __access_id_reg(struct kvm_vcpu *vcpu, 1159 struct sys_reg_params *p, 1160 const struct sys_reg_desc *r, 1161 bool raz) 1162 { 1163 if (p->is_write) 1164 return write_to_read_only(vcpu, p, r); 1165 1166 p->regval = read_id_reg(vcpu, r, raz); 1167 return true; 1168 } 1169 1170 static bool access_id_reg(struct kvm_vcpu *vcpu, 1171 struct sys_reg_params *p, 1172 const struct sys_reg_desc *r) 1173 { 1174 return __access_id_reg(vcpu, p, r, false); 1175 } 1176 1177 static bool access_raz_id_reg(struct kvm_vcpu *vcpu, 1178 struct sys_reg_params *p, 1179 const struct sys_reg_desc *r) 1180 { 1181 return __access_id_reg(vcpu, p, r, true); 1182 } 1183 1184 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); 1185 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); 1186 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 1187 1188 /* Visibility overrides for SVE-specific control registers */ 1189 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1190 const struct sys_reg_desc *rd) 1191 { 1192 if (vcpu_has_sve(vcpu)) 1193 return 0; 1194 1195 return REG_HIDDEN_USER | REG_HIDDEN_GUEST; 1196 } 1197 1198 /* Visibility overrides for SVE-specific ID registers */ 1199 static unsigned int sve_id_visibility(const struct kvm_vcpu *vcpu, 1200 const struct sys_reg_desc *rd) 1201 { 1202 if (vcpu_has_sve(vcpu)) 1203 return 0; 1204 1205 return REG_HIDDEN_USER; 1206 } 1207 1208 /* Generate the emulated ID_AA64ZFR0_EL1 value exposed to the guest */ 1209 static u64 guest_id_aa64zfr0_el1(const struct kvm_vcpu *vcpu) 1210 { 1211 if (!vcpu_has_sve(vcpu)) 1212 return 0; 1213 1214 return read_sanitised_ftr_reg(SYS_ID_AA64ZFR0_EL1); 1215 } 1216 1217 static bool access_id_aa64zfr0_el1(struct kvm_vcpu *vcpu, 1218 struct sys_reg_params *p, 1219 const struct sys_reg_desc *rd) 1220 { 1221 if (p->is_write) 1222 return write_to_read_only(vcpu, p, rd); 1223 1224 p->regval = guest_id_aa64zfr0_el1(vcpu); 1225 return true; 1226 } 1227 1228 static int get_id_aa64zfr0_el1(struct kvm_vcpu *vcpu, 1229 const struct sys_reg_desc *rd, 1230 const struct kvm_one_reg *reg, void __user *uaddr) 1231 { 1232 u64 val; 1233 1234 if (WARN_ON(!vcpu_has_sve(vcpu))) 1235 return -ENOENT; 1236 1237 val = guest_id_aa64zfr0_el1(vcpu); 1238 return reg_to_user(uaddr, &val, reg->id); 1239 } 1240 1241 static int set_id_aa64zfr0_el1(struct kvm_vcpu *vcpu, 1242 const struct sys_reg_desc *rd, 1243 const struct kvm_one_reg *reg, void __user *uaddr) 1244 { 1245 const u64 id = sys_reg_to_index(rd); 1246 int err; 1247 u64 val; 1248 1249 if (WARN_ON(!vcpu_has_sve(vcpu))) 1250 return -ENOENT; 1251 1252 err = reg_from_user(&val, uaddr, id); 1253 if (err) 1254 return err; 1255 1256 /* This is what we mean by invariant: you can't change it. */ 1257 if (val != guest_id_aa64zfr0_el1(vcpu)) 1258 return -EINVAL; 1259 1260 return 0; 1261 } 1262 1263 /* 1264 * cpufeature ID register user accessors 1265 * 1266 * For now, these registers are immutable for userspace, so no values 1267 * are stored, and for set_id_reg() we don't allow the effective value 1268 * to be changed. 1269 */ 1270 static int __get_id_reg(const struct kvm_vcpu *vcpu, 1271 const struct sys_reg_desc *rd, void __user *uaddr, 1272 bool raz) 1273 { 1274 const u64 id = sys_reg_to_index(rd); 1275 const u64 val = read_id_reg(vcpu, rd, raz); 1276 1277 return reg_to_user(uaddr, &val, id); 1278 } 1279 1280 static int __set_id_reg(const struct kvm_vcpu *vcpu, 1281 const struct sys_reg_desc *rd, void __user *uaddr, 1282 bool raz) 1283 { 1284 const u64 id = sys_reg_to_index(rd); 1285 int err; 1286 u64 val; 1287 1288 err = reg_from_user(&val, uaddr, id); 1289 if (err) 1290 return err; 1291 1292 /* This is what we mean by invariant: you can't change it. */ 1293 if (val != read_id_reg(vcpu, rd, raz)) 1294 return -EINVAL; 1295 1296 return 0; 1297 } 1298 1299 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1300 const struct kvm_one_reg *reg, void __user *uaddr) 1301 { 1302 return __get_id_reg(vcpu, rd, uaddr, false); 1303 } 1304 1305 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1306 const struct kvm_one_reg *reg, void __user *uaddr) 1307 { 1308 return __set_id_reg(vcpu, rd, uaddr, false); 1309 } 1310 1311 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1312 const struct kvm_one_reg *reg, void __user *uaddr) 1313 { 1314 return __get_id_reg(vcpu, rd, uaddr, true); 1315 } 1316 1317 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1318 const struct kvm_one_reg *reg, void __user *uaddr) 1319 { 1320 return __set_id_reg(vcpu, rd, uaddr, true); 1321 } 1322 1323 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1324 const struct sys_reg_desc *r) 1325 { 1326 if (p->is_write) 1327 return write_to_read_only(vcpu, p, r); 1328 1329 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1330 return true; 1331 } 1332 1333 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1334 const struct sys_reg_desc *r) 1335 { 1336 if (p->is_write) 1337 return write_to_read_only(vcpu, p, r); 1338 1339 p->regval = read_sysreg(clidr_el1); 1340 return true; 1341 } 1342 1343 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1344 const struct sys_reg_desc *r) 1345 { 1346 int reg = r->reg; 1347 1348 /* See the 32bit mapping in kvm_host.h */ 1349 if (p->is_aarch32) 1350 reg = r->reg / 2; 1351 1352 if (p->is_write) 1353 vcpu_write_sys_reg(vcpu, p->regval, reg); 1354 else 1355 p->regval = vcpu_read_sys_reg(vcpu, reg); 1356 return true; 1357 } 1358 1359 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1360 const struct sys_reg_desc *r) 1361 { 1362 u32 csselr; 1363 1364 if (p->is_write) 1365 return write_to_read_only(vcpu, p, r); 1366 1367 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1368 p->regval = get_ccsidr(csselr); 1369 1370 /* 1371 * Guests should not be doing cache operations by set/way at all, and 1372 * for this reason, we trap them and attempt to infer the intent, so 1373 * that we can flush the entire guest's address space at the appropriate 1374 * time. 1375 * To prevent this trapping from causing performance problems, let's 1376 * expose the geometry of all data and unified caches (which are 1377 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. 1378 * [If guests should attempt to infer aliasing properties from the 1379 * geometry (which is not permitted by the architecture), they would 1380 * only do so for virtually indexed caches.] 1381 */ 1382 if (!(csselr & 1)) // data or unified cache 1383 p->regval &= ~GENMASK(27, 3); 1384 return true; 1385 } 1386 1387 static bool access_mte_regs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1388 const struct sys_reg_desc *r) 1389 { 1390 kvm_inject_undefined(vcpu); 1391 return false; 1392 } 1393 1394 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1395 #define ID_SANITISED(name) { \ 1396 SYS_DESC(SYS_##name), \ 1397 .access = access_id_reg, \ 1398 .get_user = get_id_reg, \ 1399 .set_user = set_id_reg, \ 1400 } 1401 1402 /* 1403 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1404 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1405 * (1 <= crm < 8, 0 <= Op2 < 8). 1406 */ 1407 #define ID_UNALLOCATED(crm, op2) { \ 1408 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1409 .access = access_raz_id_reg, \ 1410 .get_user = get_raz_id_reg, \ 1411 .set_user = set_raz_id_reg, \ 1412 } 1413 1414 /* 1415 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1416 * For now, these are exposed just like unallocated ID regs: they appear 1417 * RAZ for the guest. 1418 */ 1419 #define ID_HIDDEN(name) { \ 1420 SYS_DESC(SYS_##name), \ 1421 .access = access_raz_id_reg, \ 1422 .get_user = get_raz_id_reg, \ 1423 .set_user = set_raz_id_reg, \ 1424 } 1425 1426 /* 1427 * Architected system registers. 1428 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1429 * 1430 * Debug handling: We do trap most, if not all debug related system 1431 * registers. The implementation is good enough to ensure that a guest 1432 * can use these with minimal performance degradation. The drawback is 1433 * that we don't implement any of the external debug, none of the 1434 * OSlock protocol. This should be revisited if we ever encounter a 1435 * more demanding guest... 1436 */ 1437 static const struct sys_reg_desc sys_reg_descs[] = { 1438 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1439 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1440 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1441 1442 DBG_BCR_BVR_WCR_WVR_EL1(0), 1443 DBG_BCR_BVR_WCR_WVR_EL1(1), 1444 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1445 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1446 DBG_BCR_BVR_WCR_WVR_EL1(2), 1447 DBG_BCR_BVR_WCR_WVR_EL1(3), 1448 DBG_BCR_BVR_WCR_WVR_EL1(4), 1449 DBG_BCR_BVR_WCR_WVR_EL1(5), 1450 DBG_BCR_BVR_WCR_WVR_EL1(6), 1451 DBG_BCR_BVR_WCR_WVR_EL1(7), 1452 DBG_BCR_BVR_WCR_WVR_EL1(8), 1453 DBG_BCR_BVR_WCR_WVR_EL1(9), 1454 DBG_BCR_BVR_WCR_WVR_EL1(10), 1455 DBG_BCR_BVR_WCR_WVR_EL1(11), 1456 DBG_BCR_BVR_WCR_WVR_EL1(12), 1457 DBG_BCR_BVR_WCR_WVR_EL1(13), 1458 DBG_BCR_BVR_WCR_WVR_EL1(14), 1459 DBG_BCR_BVR_WCR_WVR_EL1(15), 1460 1461 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1462 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, 1463 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, 1464 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1465 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1466 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1467 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1468 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1469 1470 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1471 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1472 // DBGDTR[TR]X_EL0 share the same encoding 1473 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1474 1475 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1476 1477 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1478 1479 /* 1480 * ID regs: all ID_SANITISED() entries here must have corresponding 1481 * entries in arm64_ftr_regs[]. 1482 */ 1483 1484 /* AArch64 mappings of the AArch32 ID registers */ 1485 /* CRm=1 */ 1486 ID_SANITISED(ID_PFR0_EL1), 1487 ID_SANITISED(ID_PFR1_EL1), 1488 ID_SANITISED(ID_DFR0_EL1), 1489 ID_HIDDEN(ID_AFR0_EL1), 1490 ID_SANITISED(ID_MMFR0_EL1), 1491 ID_SANITISED(ID_MMFR1_EL1), 1492 ID_SANITISED(ID_MMFR2_EL1), 1493 ID_SANITISED(ID_MMFR3_EL1), 1494 1495 /* CRm=2 */ 1496 ID_SANITISED(ID_ISAR0_EL1), 1497 ID_SANITISED(ID_ISAR1_EL1), 1498 ID_SANITISED(ID_ISAR2_EL1), 1499 ID_SANITISED(ID_ISAR3_EL1), 1500 ID_SANITISED(ID_ISAR4_EL1), 1501 ID_SANITISED(ID_ISAR5_EL1), 1502 ID_SANITISED(ID_MMFR4_EL1), 1503 ID_SANITISED(ID_ISAR6_EL1), 1504 1505 /* CRm=3 */ 1506 ID_SANITISED(MVFR0_EL1), 1507 ID_SANITISED(MVFR1_EL1), 1508 ID_SANITISED(MVFR2_EL1), 1509 ID_UNALLOCATED(3,3), 1510 ID_SANITISED(ID_PFR2_EL1), 1511 ID_HIDDEN(ID_DFR1_EL1), 1512 ID_SANITISED(ID_MMFR5_EL1), 1513 ID_UNALLOCATED(3,7), 1514 1515 /* AArch64 ID registers */ 1516 /* CRm=4 */ 1517 ID_SANITISED(ID_AA64PFR0_EL1), 1518 ID_SANITISED(ID_AA64PFR1_EL1), 1519 ID_UNALLOCATED(4,2), 1520 ID_UNALLOCATED(4,3), 1521 { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user = get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, .visibility = sve_id_visibility }, 1522 ID_UNALLOCATED(4,5), 1523 ID_UNALLOCATED(4,6), 1524 ID_UNALLOCATED(4,7), 1525 1526 /* CRm=5 */ 1527 ID_SANITISED(ID_AA64DFR0_EL1), 1528 ID_SANITISED(ID_AA64DFR1_EL1), 1529 ID_UNALLOCATED(5,2), 1530 ID_UNALLOCATED(5,3), 1531 ID_HIDDEN(ID_AA64AFR0_EL1), 1532 ID_HIDDEN(ID_AA64AFR1_EL1), 1533 ID_UNALLOCATED(5,6), 1534 ID_UNALLOCATED(5,7), 1535 1536 /* CRm=6 */ 1537 ID_SANITISED(ID_AA64ISAR0_EL1), 1538 ID_SANITISED(ID_AA64ISAR1_EL1), 1539 ID_UNALLOCATED(6,2), 1540 ID_UNALLOCATED(6,3), 1541 ID_UNALLOCATED(6,4), 1542 ID_UNALLOCATED(6,5), 1543 ID_UNALLOCATED(6,6), 1544 ID_UNALLOCATED(6,7), 1545 1546 /* CRm=7 */ 1547 ID_SANITISED(ID_AA64MMFR0_EL1), 1548 ID_SANITISED(ID_AA64MMFR1_EL1), 1549 ID_SANITISED(ID_AA64MMFR2_EL1), 1550 ID_UNALLOCATED(7,3), 1551 ID_UNALLOCATED(7,4), 1552 ID_UNALLOCATED(7,5), 1553 ID_UNALLOCATED(7,6), 1554 ID_UNALLOCATED(7,7), 1555 1556 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1557 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1558 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1559 1560 { SYS_DESC(SYS_RGSR_EL1), access_mte_regs }, 1561 { SYS_DESC(SYS_GCR_EL1), access_mte_regs }, 1562 1563 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1564 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1565 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1566 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1567 1568 PTRAUTH_KEY(APIA), 1569 PTRAUTH_KEY(APIB), 1570 PTRAUTH_KEY(APDA), 1571 PTRAUTH_KEY(APDB), 1572 PTRAUTH_KEY(APGA), 1573 1574 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1575 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1576 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1577 1578 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1579 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1580 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1581 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1582 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1583 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1584 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1585 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1586 1587 { SYS_DESC(SYS_TFSR_EL1), access_mte_regs }, 1588 { SYS_DESC(SYS_TFSRE0_EL1), access_mte_regs }, 1589 1590 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1591 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1592 1593 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, 1594 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, 1595 1596 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1597 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1598 1599 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1600 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1601 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1602 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1603 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1604 1605 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, 1606 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1607 1608 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1609 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1610 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1611 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1612 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1613 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1614 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1615 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1616 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1617 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1618 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1619 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1620 1621 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1622 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1623 1624 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1625 1626 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1627 { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, 1628 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1629 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1630 1631 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 }, 1632 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, 1633 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, 1634 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, 1635 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 }, 1636 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 }, 1637 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid }, 1638 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid }, 1639 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 }, 1640 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper }, 1641 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr }, 1642 /* 1643 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1644 * in 32bit mode. Here we choose to reset it as zero for consistency. 1645 */ 1646 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 }, 1647 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, 1648 1649 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 1650 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 1651 1652 { SYS_DESC(SYS_AMCR_EL0), access_amu }, 1653 { SYS_DESC(SYS_AMCFGR_EL0), access_amu }, 1654 { SYS_DESC(SYS_AMCGCR_EL0), access_amu }, 1655 { SYS_DESC(SYS_AMUSERENR_EL0), access_amu }, 1656 { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu }, 1657 { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu }, 1658 { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu }, 1659 { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu }, 1660 AMU_AMEVCNTR0_EL0(0), 1661 AMU_AMEVCNTR0_EL0(1), 1662 AMU_AMEVCNTR0_EL0(2), 1663 AMU_AMEVCNTR0_EL0(3), 1664 AMU_AMEVCNTR0_EL0(4), 1665 AMU_AMEVCNTR0_EL0(5), 1666 AMU_AMEVCNTR0_EL0(6), 1667 AMU_AMEVCNTR0_EL0(7), 1668 AMU_AMEVCNTR0_EL0(8), 1669 AMU_AMEVCNTR0_EL0(9), 1670 AMU_AMEVCNTR0_EL0(10), 1671 AMU_AMEVCNTR0_EL0(11), 1672 AMU_AMEVCNTR0_EL0(12), 1673 AMU_AMEVCNTR0_EL0(13), 1674 AMU_AMEVCNTR0_EL0(14), 1675 AMU_AMEVCNTR0_EL0(15), 1676 AMU_AMEVTYPER0_EL0(0), 1677 AMU_AMEVTYPER0_EL0(1), 1678 AMU_AMEVTYPER0_EL0(2), 1679 AMU_AMEVTYPER0_EL0(3), 1680 AMU_AMEVTYPER0_EL0(4), 1681 AMU_AMEVTYPER0_EL0(5), 1682 AMU_AMEVTYPER0_EL0(6), 1683 AMU_AMEVTYPER0_EL0(7), 1684 AMU_AMEVTYPER0_EL0(8), 1685 AMU_AMEVTYPER0_EL0(9), 1686 AMU_AMEVTYPER0_EL0(10), 1687 AMU_AMEVTYPER0_EL0(11), 1688 AMU_AMEVTYPER0_EL0(12), 1689 AMU_AMEVTYPER0_EL0(13), 1690 AMU_AMEVTYPER0_EL0(14), 1691 AMU_AMEVTYPER0_EL0(15), 1692 AMU_AMEVCNTR1_EL0(0), 1693 AMU_AMEVCNTR1_EL0(1), 1694 AMU_AMEVCNTR1_EL0(2), 1695 AMU_AMEVCNTR1_EL0(3), 1696 AMU_AMEVCNTR1_EL0(4), 1697 AMU_AMEVCNTR1_EL0(5), 1698 AMU_AMEVCNTR1_EL0(6), 1699 AMU_AMEVCNTR1_EL0(7), 1700 AMU_AMEVCNTR1_EL0(8), 1701 AMU_AMEVCNTR1_EL0(9), 1702 AMU_AMEVCNTR1_EL0(10), 1703 AMU_AMEVCNTR1_EL0(11), 1704 AMU_AMEVCNTR1_EL0(12), 1705 AMU_AMEVCNTR1_EL0(13), 1706 AMU_AMEVCNTR1_EL0(14), 1707 AMU_AMEVCNTR1_EL0(15), 1708 AMU_AMEVTYPER1_EL0(0), 1709 AMU_AMEVTYPER1_EL0(1), 1710 AMU_AMEVTYPER1_EL0(2), 1711 AMU_AMEVTYPER1_EL0(3), 1712 AMU_AMEVTYPER1_EL0(4), 1713 AMU_AMEVTYPER1_EL0(5), 1714 AMU_AMEVTYPER1_EL0(6), 1715 AMU_AMEVTYPER1_EL0(7), 1716 AMU_AMEVTYPER1_EL0(8), 1717 AMU_AMEVTYPER1_EL0(9), 1718 AMU_AMEVTYPER1_EL0(10), 1719 AMU_AMEVTYPER1_EL0(11), 1720 AMU_AMEVTYPER1_EL0(12), 1721 AMU_AMEVTYPER1_EL0(13), 1722 AMU_AMEVTYPER1_EL0(14), 1723 AMU_AMEVTYPER1_EL0(15), 1724 1725 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 1726 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 1727 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 1728 1729 /* PMEVCNTRn_EL0 */ 1730 PMU_PMEVCNTR_EL0(0), 1731 PMU_PMEVCNTR_EL0(1), 1732 PMU_PMEVCNTR_EL0(2), 1733 PMU_PMEVCNTR_EL0(3), 1734 PMU_PMEVCNTR_EL0(4), 1735 PMU_PMEVCNTR_EL0(5), 1736 PMU_PMEVCNTR_EL0(6), 1737 PMU_PMEVCNTR_EL0(7), 1738 PMU_PMEVCNTR_EL0(8), 1739 PMU_PMEVCNTR_EL0(9), 1740 PMU_PMEVCNTR_EL0(10), 1741 PMU_PMEVCNTR_EL0(11), 1742 PMU_PMEVCNTR_EL0(12), 1743 PMU_PMEVCNTR_EL0(13), 1744 PMU_PMEVCNTR_EL0(14), 1745 PMU_PMEVCNTR_EL0(15), 1746 PMU_PMEVCNTR_EL0(16), 1747 PMU_PMEVCNTR_EL0(17), 1748 PMU_PMEVCNTR_EL0(18), 1749 PMU_PMEVCNTR_EL0(19), 1750 PMU_PMEVCNTR_EL0(20), 1751 PMU_PMEVCNTR_EL0(21), 1752 PMU_PMEVCNTR_EL0(22), 1753 PMU_PMEVCNTR_EL0(23), 1754 PMU_PMEVCNTR_EL0(24), 1755 PMU_PMEVCNTR_EL0(25), 1756 PMU_PMEVCNTR_EL0(26), 1757 PMU_PMEVCNTR_EL0(27), 1758 PMU_PMEVCNTR_EL0(28), 1759 PMU_PMEVCNTR_EL0(29), 1760 PMU_PMEVCNTR_EL0(30), 1761 /* PMEVTYPERn_EL0 */ 1762 PMU_PMEVTYPER_EL0(0), 1763 PMU_PMEVTYPER_EL0(1), 1764 PMU_PMEVTYPER_EL0(2), 1765 PMU_PMEVTYPER_EL0(3), 1766 PMU_PMEVTYPER_EL0(4), 1767 PMU_PMEVTYPER_EL0(5), 1768 PMU_PMEVTYPER_EL0(6), 1769 PMU_PMEVTYPER_EL0(7), 1770 PMU_PMEVTYPER_EL0(8), 1771 PMU_PMEVTYPER_EL0(9), 1772 PMU_PMEVTYPER_EL0(10), 1773 PMU_PMEVTYPER_EL0(11), 1774 PMU_PMEVTYPER_EL0(12), 1775 PMU_PMEVTYPER_EL0(13), 1776 PMU_PMEVTYPER_EL0(14), 1777 PMU_PMEVTYPER_EL0(15), 1778 PMU_PMEVTYPER_EL0(16), 1779 PMU_PMEVTYPER_EL0(17), 1780 PMU_PMEVTYPER_EL0(18), 1781 PMU_PMEVTYPER_EL0(19), 1782 PMU_PMEVTYPER_EL0(20), 1783 PMU_PMEVTYPER_EL0(21), 1784 PMU_PMEVTYPER_EL0(22), 1785 PMU_PMEVTYPER_EL0(23), 1786 PMU_PMEVTYPER_EL0(24), 1787 PMU_PMEVTYPER_EL0(25), 1788 PMU_PMEVTYPER_EL0(26), 1789 PMU_PMEVTYPER_EL0(27), 1790 PMU_PMEVTYPER_EL0(28), 1791 PMU_PMEVTYPER_EL0(29), 1792 PMU_PMEVTYPER_EL0(30), 1793 /* 1794 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 1795 * in 32bit mode. Here we choose to reset it as zero for consistency. 1796 */ 1797 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 }, 1798 1799 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 1800 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 1801 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 1802 }; 1803 1804 static bool trap_dbgidr(struct kvm_vcpu *vcpu, 1805 struct sys_reg_params *p, 1806 const struct sys_reg_desc *r) 1807 { 1808 if (p->is_write) { 1809 return ignore_write(vcpu, p); 1810 } else { 1811 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1812 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1813 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); 1814 1815 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | 1816 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | 1817 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) 1818 | (6 << 16) | (el3 << 14) | (el3 << 12)); 1819 return true; 1820 } 1821 } 1822 1823 static bool trap_debug32(struct kvm_vcpu *vcpu, 1824 struct sys_reg_params *p, 1825 const struct sys_reg_desc *r) 1826 { 1827 if (p->is_write) { 1828 vcpu_cp14(vcpu, r->reg) = p->regval; 1829 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 1830 } else { 1831 p->regval = vcpu_cp14(vcpu, r->reg); 1832 } 1833 1834 return true; 1835 } 1836 1837 /* AArch32 debug register mappings 1838 * 1839 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 1840 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 1841 * 1842 * All control registers and watchpoint value registers are mapped to 1843 * the lower 32 bits of their AArch64 equivalents. We share the trap 1844 * handlers with the above AArch64 code which checks what mode the 1845 * system is in. 1846 */ 1847 1848 static bool trap_xvr(struct kvm_vcpu *vcpu, 1849 struct sys_reg_params *p, 1850 const struct sys_reg_desc *rd) 1851 { 1852 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 1853 1854 if (p->is_write) { 1855 u64 val = *dbg_reg; 1856 1857 val &= 0xffffffffUL; 1858 val |= p->regval << 32; 1859 *dbg_reg = val; 1860 1861 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 1862 } else { 1863 p->regval = *dbg_reg >> 32; 1864 } 1865 1866 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 1867 1868 return true; 1869 } 1870 1871 #define DBG_BCR_BVR_WCR_WVR(n) \ 1872 /* DBGBVRn */ \ 1873 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 1874 /* DBGBCRn */ \ 1875 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 1876 /* DBGWVRn */ \ 1877 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 1878 /* DBGWCRn */ \ 1879 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 1880 1881 #define DBGBXVR(n) \ 1882 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n } 1883 1884 /* 1885 * Trapped cp14 registers. We generally ignore most of the external 1886 * debug, on the principle that they don't really make sense to a 1887 * guest. Revisit this one day, would this principle change. 1888 */ 1889 static const struct sys_reg_desc cp14_regs[] = { 1890 /* DBGIDR */ 1891 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr }, 1892 /* DBGDTRRXext */ 1893 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 1894 1895 DBG_BCR_BVR_WCR_WVR(0), 1896 /* DBGDSCRint */ 1897 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 1898 DBG_BCR_BVR_WCR_WVR(1), 1899 /* DBGDCCINT */ 1900 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 }, 1901 /* DBGDSCRext */ 1902 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 }, 1903 DBG_BCR_BVR_WCR_WVR(2), 1904 /* DBGDTR[RT]Xint */ 1905 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 1906 /* DBGDTR[RT]Xext */ 1907 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 1908 DBG_BCR_BVR_WCR_WVR(3), 1909 DBG_BCR_BVR_WCR_WVR(4), 1910 DBG_BCR_BVR_WCR_WVR(5), 1911 /* DBGWFAR */ 1912 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 1913 /* DBGOSECCR */ 1914 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 1915 DBG_BCR_BVR_WCR_WVR(6), 1916 /* DBGVCR */ 1917 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 }, 1918 DBG_BCR_BVR_WCR_WVR(7), 1919 DBG_BCR_BVR_WCR_WVR(8), 1920 DBG_BCR_BVR_WCR_WVR(9), 1921 DBG_BCR_BVR_WCR_WVR(10), 1922 DBG_BCR_BVR_WCR_WVR(11), 1923 DBG_BCR_BVR_WCR_WVR(12), 1924 DBG_BCR_BVR_WCR_WVR(13), 1925 DBG_BCR_BVR_WCR_WVR(14), 1926 DBG_BCR_BVR_WCR_WVR(15), 1927 1928 /* DBGDRAR (32bit) */ 1929 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 1930 1931 DBGBXVR(0), 1932 /* DBGOSLAR */ 1933 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, 1934 DBGBXVR(1), 1935 /* DBGOSLSR */ 1936 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, 1937 DBGBXVR(2), 1938 DBGBXVR(3), 1939 /* DBGOSDLR */ 1940 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 1941 DBGBXVR(4), 1942 /* DBGPRCR */ 1943 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 1944 DBGBXVR(5), 1945 DBGBXVR(6), 1946 DBGBXVR(7), 1947 DBGBXVR(8), 1948 DBGBXVR(9), 1949 DBGBXVR(10), 1950 DBGBXVR(11), 1951 DBGBXVR(12), 1952 DBGBXVR(13), 1953 DBGBXVR(14), 1954 DBGBXVR(15), 1955 1956 /* DBGDSAR (32bit) */ 1957 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 1958 1959 /* DBGDEVID2 */ 1960 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 1961 /* DBGDEVID1 */ 1962 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 1963 /* DBGDEVID */ 1964 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 1965 /* DBGCLAIMSET */ 1966 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 1967 /* DBGCLAIMCLR */ 1968 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 1969 /* DBGAUTHSTATUS */ 1970 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 1971 }; 1972 1973 /* Trapped cp14 64bit registers */ 1974 static const struct sys_reg_desc cp14_64_regs[] = { 1975 /* DBGDRAR (64bit) */ 1976 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 1977 1978 /* DBGDSAR (64bit) */ 1979 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 1980 }; 1981 1982 /* Macro to expand the PMEVCNTRn register */ 1983 #define PMU_PMEVCNTR(n) \ 1984 /* PMEVCNTRn */ \ 1985 { Op1(0), CRn(0b1110), \ 1986 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1987 access_pmu_evcntr } 1988 1989 /* Macro to expand the PMEVTYPERn register */ 1990 #define PMU_PMEVTYPER(n) \ 1991 /* PMEVTYPERn */ \ 1992 { Op1(0), CRn(0b1110), \ 1993 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1994 access_pmu_evtyper } 1995 1996 /* 1997 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 1998 * depending on the way they are accessed (as a 32bit or a 64bit 1999 * register). 2000 */ 2001 static const struct sys_reg_desc cp15_regs[] = { 2002 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 2003 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR }, 2004 { Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr }, 2005 { Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr }, 2006 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 2007 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 }, 2008 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR }, 2009 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR }, 2010 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR }, 2011 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR }, 2012 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR }, 2013 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR }, 2014 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR }, 2015 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR }, 2016 2017 /* 2018 * DC{C,I,CI}SW operations: 2019 */ 2020 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 2021 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 2022 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 2023 2024 /* PMU */ 2025 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, 2026 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, 2027 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, 2028 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, 2029 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, 2030 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, 2031 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, 2032 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, 2033 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, 2034 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, 2035 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, 2036 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, 2037 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, 2038 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, 2039 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, 2040 2041 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, 2042 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, 2043 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 }, 2044 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, 2045 2046 /* ICC_SRE */ 2047 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 2048 2049 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, 2050 2051 /* Arch Tmers */ 2052 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 2053 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 2054 2055 /* PMEVCNTRn */ 2056 PMU_PMEVCNTR(0), 2057 PMU_PMEVCNTR(1), 2058 PMU_PMEVCNTR(2), 2059 PMU_PMEVCNTR(3), 2060 PMU_PMEVCNTR(4), 2061 PMU_PMEVCNTR(5), 2062 PMU_PMEVCNTR(6), 2063 PMU_PMEVCNTR(7), 2064 PMU_PMEVCNTR(8), 2065 PMU_PMEVCNTR(9), 2066 PMU_PMEVCNTR(10), 2067 PMU_PMEVCNTR(11), 2068 PMU_PMEVCNTR(12), 2069 PMU_PMEVCNTR(13), 2070 PMU_PMEVCNTR(14), 2071 PMU_PMEVCNTR(15), 2072 PMU_PMEVCNTR(16), 2073 PMU_PMEVCNTR(17), 2074 PMU_PMEVCNTR(18), 2075 PMU_PMEVCNTR(19), 2076 PMU_PMEVCNTR(20), 2077 PMU_PMEVCNTR(21), 2078 PMU_PMEVCNTR(22), 2079 PMU_PMEVCNTR(23), 2080 PMU_PMEVCNTR(24), 2081 PMU_PMEVCNTR(25), 2082 PMU_PMEVCNTR(26), 2083 PMU_PMEVCNTR(27), 2084 PMU_PMEVCNTR(28), 2085 PMU_PMEVCNTR(29), 2086 PMU_PMEVCNTR(30), 2087 /* PMEVTYPERn */ 2088 PMU_PMEVTYPER(0), 2089 PMU_PMEVTYPER(1), 2090 PMU_PMEVTYPER(2), 2091 PMU_PMEVTYPER(3), 2092 PMU_PMEVTYPER(4), 2093 PMU_PMEVTYPER(5), 2094 PMU_PMEVTYPER(6), 2095 PMU_PMEVTYPER(7), 2096 PMU_PMEVTYPER(8), 2097 PMU_PMEVTYPER(9), 2098 PMU_PMEVTYPER(10), 2099 PMU_PMEVTYPER(11), 2100 PMU_PMEVTYPER(12), 2101 PMU_PMEVTYPER(13), 2102 PMU_PMEVTYPER(14), 2103 PMU_PMEVTYPER(15), 2104 PMU_PMEVTYPER(16), 2105 PMU_PMEVTYPER(17), 2106 PMU_PMEVTYPER(18), 2107 PMU_PMEVTYPER(19), 2108 PMU_PMEVTYPER(20), 2109 PMU_PMEVTYPER(21), 2110 PMU_PMEVTYPER(22), 2111 PMU_PMEVTYPER(23), 2112 PMU_PMEVTYPER(24), 2113 PMU_PMEVTYPER(25), 2114 PMU_PMEVTYPER(26), 2115 PMU_PMEVTYPER(27), 2116 PMU_PMEVTYPER(28), 2117 PMU_PMEVTYPER(29), 2118 PMU_PMEVTYPER(30), 2119 /* PMCCFILTR */ 2120 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, 2121 2122 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2123 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2124 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR }, 2125 }; 2126 2127 static const struct sys_reg_desc cp15_64_regs[] = { 2128 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 2129 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, 2130 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2131 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, 2132 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2133 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2134 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2135 }; 2136 2137 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2138 bool is_32) 2139 { 2140 unsigned int i; 2141 2142 for (i = 0; i < n; i++) { 2143 if (!is_32 && table[i].reg && !table[i].reset) { 2144 kvm_err("sys_reg table %p entry %d has lacks reset\n", 2145 table, i); 2146 return 1; 2147 } 2148 2149 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2150 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); 2151 return 1; 2152 } 2153 } 2154 2155 return 0; 2156 } 2157 2158 static int match_sys_reg(const void *key, const void *elt) 2159 { 2160 const unsigned long pval = (unsigned long)key; 2161 const struct sys_reg_desc *r = elt; 2162 2163 return pval - reg_to_encoding(r); 2164 } 2165 2166 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params, 2167 const struct sys_reg_desc table[], 2168 unsigned int num) 2169 { 2170 unsigned long pval = reg_to_encoding(params); 2171 2172 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg); 2173 } 2174 2175 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2176 { 2177 kvm_inject_undefined(vcpu); 2178 return 1; 2179 } 2180 2181 static void perform_access(struct kvm_vcpu *vcpu, 2182 struct sys_reg_params *params, 2183 const struct sys_reg_desc *r) 2184 { 2185 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2186 2187 /* Check for regs disabled by runtime config */ 2188 if (sysreg_hidden_from_guest(vcpu, r)) { 2189 kvm_inject_undefined(vcpu); 2190 return; 2191 } 2192 2193 /* 2194 * Not having an accessor means that we have configured a trap 2195 * that we don't know how to handle. This certainly qualifies 2196 * as a gross bug that should be fixed right away. 2197 */ 2198 BUG_ON(!r->access); 2199 2200 /* Skip instruction if instructed so */ 2201 if (likely(r->access(vcpu, params, r))) 2202 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); 2203 } 2204 2205 /* 2206 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2207 * call the corresponding trap handler. 2208 * 2209 * @params: pointer to the descriptor of the access 2210 * @table: array of trap descriptors 2211 * @num: size of the trap descriptor array 2212 * 2213 * Return 0 if the access has been handled, and -1 if not. 2214 */ 2215 static int emulate_cp(struct kvm_vcpu *vcpu, 2216 struct sys_reg_params *params, 2217 const struct sys_reg_desc *table, 2218 size_t num) 2219 { 2220 const struct sys_reg_desc *r; 2221 2222 if (!table) 2223 return -1; /* Not handled */ 2224 2225 r = find_reg(params, table, num); 2226 2227 if (r) { 2228 perform_access(vcpu, params, r); 2229 return 0; 2230 } 2231 2232 /* Not handled */ 2233 return -1; 2234 } 2235 2236 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2237 struct sys_reg_params *params) 2238 { 2239 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2240 int cp = -1; 2241 2242 switch (esr_ec) { 2243 case ESR_ELx_EC_CP15_32: 2244 case ESR_ELx_EC_CP15_64: 2245 cp = 15; 2246 break; 2247 case ESR_ELx_EC_CP14_MR: 2248 case ESR_ELx_EC_CP14_64: 2249 cp = 14; 2250 break; 2251 default: 2252 WARN_ON(1); 2253 } 2254 2255 print_sys_reg_msg(params, 2256 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2257 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2258 kvm_inject_undefined(vcpu); 2259 } 2260 2261 /** 2262 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2263 * @vcpu: The VCPU pointer 2264 * @run: The kvm_run struct 2265 */ 2266 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2267 const struct sys_reg_desc *global, 2268 size_t nr_global) 2269 { 2270 struct sys_reg_params params; 2271 u32 esr = kvm_vcpu_get_esr(vcpu); 2272 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2273 int Rt2 = (esr >> 10) & 0x1f; 2274 2275 params.is_aarch32 = true; 2276 params.is_32bit = false; 2277 params.CRm = (esr >> 1) & 0xf; 2278 params.is_write = ((esr & 1) == 0); 2279 2280 params.Op0 = 0; 2281 params.Op1 = (esr >> 16) & 0xf; 2282 params.Op2 = 0; 2283 params.CRn = 0; 2284 2285 /* 2286 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2287 * backends between AArch32 and AArch64, we get away with it. 2288 */ 2289 if (params.is_write) { 2290 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2291 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2292 } 2293 2294 /* 2295 * If the table contains a handler, handle the 2296 * potential register operation in the case of a read and return 2297 * with success. 2298 */ 2299 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2300 /* Split up the value between registers for the read side */ 2301 if (!params.is_write) { 2302 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2303 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2304 } 2305 2306 return 1; 2307 } 2308 2309 unhandled_cp_access(vcpu, ¶ms); 2310 return 1; 2311 } 2312 2313 /** 2314 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2315 * @vcpu: The VCPU pointer 2316 * @run: The kvm_run struct 2317 */ 2318 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2319 const struct sys_reg_desc *global, 2320 size_t nr_global) 2321 { 2322 struct sys_reg_params params; 2323 u32 esr = kvm_vcpu_get_esr(vcpu); 2324 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2325 2326 params.is_aarch32 = true; 2327 params.is_32bit = true; 2328 params.CRm = (esr >> 1) & 0xf; 2329 params.regval = vcpu_get_reg(vcpu, Rt); 2330 params.is_write = ((esr & 1) == 0); 2331 params.CRn = (esr >> 10) & 0xf; 2332 params.Op0 = 0; 2333 params.Op1 = (esr >> 14) & 0x7; 2334 params.Op2 = (esr >> 17) & 0x7; 2335 2336 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2337 if (!params.is_write) 2338 vcpu_set_reg(vcpu, Rt, params.regval); 2339 return 1; 2340 } 2341 2342 unhandled_cp_access(vcpu, ¶ms); 2343 return 1; 2344 } 2345 2346 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2347 { 2348 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2349 } 2350 2351 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2352 { 2353 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); 2354 } 2355 2356 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2357 { 2358 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2359 } 2360 2361 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2362 { 2363 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs)); 2364 } 2365 2366 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2367 { 2368 // See ARM DDI 0487E.a, section D12.3.2 2369 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2370 } 2371 2372 static int emulate_sys_reg(struct kvm_vcpu *vcpu, 2373 struct sys_reg_params *params) 2374 { 2375 const struct sys_reg_desc *r; 2376 2377 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2378 2379 if (likely(r)) { 2380 perform_access(vcpu, params, r); 2381 } else if (is_imp_def_sys_reg(params)) { 2382 kvm_inject_undefined(vcpu); 2383 } else { 2384 print_sys_reg_msg(params, 2385 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2386 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2387 kvm_inject_undefined(vcpu); 2388 } 2389 return 1; 2390 } 2391 2392 /** 2393 * kvm_reset_sys_regs - sets system registers to reset value 2394 * @vcpu: The VCPU pointer 2395 * 2396 * This function finds the right table above and sets the registers on the 2397 * virtual CPU struct to their architecturally defined reset values. 2398 */ 2399 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2400 { 2401 unsigned long i; 2402 2403 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2404 if (sys_reg_descs[i].reset) 2405 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2406 } 2407 2408 /** 2409 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2410 * @vcpu: The VCPU pointer 2411 */ 2412 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2413 { 2414 struct sys_reg_params params; 2415 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2416 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2417 int ret; 2418 2419 trace_kvm_handle_sys_reg(esr); 2420 2421 params.is_aarch32 = false; 2422 params.is_32bit = false; 2423 params.Op0 = (esr >> 20) & 3; 2424 params.Op1 = (esr >> 14) & 0x7; 2425 params.CRn = (esr >> 10) & 0xf; 2426 params.CRm = (esr >> 1) & 0xf; 2427 params.Op2 = (esr >> 17) & 0x7; 2428 params.regval = vcpu_get_reg(vcpu, Rt); 2429 params.is_write = !(esr & 1); 2430 2431 ret = emulate_sys_reg(vcpu, ¶ms); 2432 2433 if (!params.is_write) 2434 vcpu_set_reg(vcpu, Rt, params.regval); 2435 return ret; 2436 } 2437 2438 /****************************************************************************** 2439 * Userspace API 2440 *****************************************************************************/ 2441 2442 static bool index_to_params(u64 id, struct sys_reg_params *params) 2443 { 2444 switch (id & KVM_REG_SIZE_MASK) { 2445 case KVM_REG_SIZE_U64: 2446 /* Any unused index bits means it's not valid. */ 2447 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2448 | KVM_REG_ARM_COPROC_MASK 2449 | KVM_REG_ARM64_SYSREG_OP0_MASK 2450 | KVM_REG_ARM64_SYSREG_OP1_MASK 2451 | KVM_REG_ARM64_SYSREG_CRN_MASK 2452 | KVM_REG_ARM64_SYSREG_CRM_MASK 2453 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2454 return false; 2455 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2456 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2457 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2458 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2459 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2460 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2461 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2462 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2463 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2464 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2465 return true; 2466 default: 2467 return false; 2468 } 2469 } 2470 2471 const struct sys_reg_desc *find_reg_by_id(u64 id, 2472 struct sys_reg_params *params, 2473 const struct sys_reg_desc table[], 2474 unsigned int num) 2475 { 2476 if (!index_to_params(id, params)) 2477 return NULL; 2478 2479 return find_reg(params, table, num); 2480 } 2481 2482 /* Decode an index value, and find the sys_reg_desc entry. */ 2483 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, 2484 u64 id) 2485 { 2486 const struct sys_reg_desc *r; 2487 struct sys_reg_params params; 2488 2489 /* We only do sys_reg for now. */ 2490 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2491 return NULL; 2492 2493 if (!index_to_params(id, ¶ms)) 2494 return NULL; 2495 2496 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2497 2498 /* Not saved in the sys_reg array and not otherwise accessible? */ 2499 if (r && !(r->reg || r->get_user)) 2500 r = NULL; 2501 2502 return r; 2503 } 2504 2505 /* 2506 * These are the invariant sys_reg registers: we let the guest see the 2507 * host versions of these, so they're part of the guest state. 2508 * 2509 * A future CPU may provide a mechanism to present different values to 2510 * the guest, or a future kvm may trap them. 2511 */ 2512 2513 #define FUNCTION_INVARIANT(reg) \ 2514 static void get_##reg(struct kvm_vcpu *v, \ 2515 const struct sys_reg_desc *r) \ 2516 { \ 2517 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 2518 } 2519 2520 FUNCTION_INVARIANT(midr_el1) 2521 FUNCTION_INVARIANT(revidr_el1) 2522 FUNCTION_INVARIANT(clidr_el1) 2523 FUNCTION_INVARIANT(aidr_el1) 2524 2525 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 2526 { 2527 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 2528 } 2529 2530 /* ->val is filled in by kvm_sys_reg_table_init() */ 2531 static struct sys_reg_desc invariant_sys_regs[] = { 2532 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 2533 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 2534 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, 2535 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 2536 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 2537 }; 2538 2539 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) 2540 { 2541 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) 2542 return -EFAULT; 2543 return 0; 2544 } 2545 2546 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) 2547 { 2548 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) 2549 return -EFAULT; 2550 return 0; 2551 } 2552 2553 static int get_invariant_sys_reg(u64 id, void __user *uaddr) 2554 { 2555 struct sys_reg_params params; 2556 const struct sys_reg_desc *r; 2557 2558 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2559 ARRAY_SIZE(invariant_sys_regs)); 2560 if (!r) 2561 return -ENOENT; 2562 2563 return reg_to_user(uaddr, &r->val, id); 2564 } 2565 2566 static int set_invariant_sys_reg(u64 id, void __user *uaddr) 2567 { 2568 struct sys_reg_params params; 2569 const struct sys_reg_desc *r; 2570 int err; 2571 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ 2572 2573 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2574 ARRAY_SIZE(invariant_sys_regs)); 2575 if (!r) 2576 return -ENOENT; 2577 2578 err = reg_from_user(&val, uaddr, id); 2579 if (err) 2580 return err; 2581 2582 /* This is what we mean by invariant: you can't change it. */ 2583 if (r->val != val) 2584 return -EINVAL; 2585 2586 return 0; 2587 } 2588 2589 static bool is_valid_cache(u32 val) 2590 { 2591 u32 level, ctype; 2592 2593 if (val >= CSSELR_MAX) 2594 return false; 2595 2596 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 2597 level = (val >> 1); 2598 ctype = (cache_levels >> (level * 3)) & 7; 2599 2600 switch (ctype) { 2601 case 0: /* No cache */ 2602 return false; 2603 case 1: /* Instruction cache only */ 2604 return (val & 1); 2605 case 2: /* Data cache only */ 2606 case 4: /* Unified cache */ 2607 return !(val & 1); 2608 case 3: /* Separate instruction and data caches */ 2609 return true; 2610 default: /* Reserved: we can't know instruction or data. */ 2611 return false; 2612 } 2613 } 2614 2615 static int demux_c15_get(u64 id, void __user *uaddr) 2616 { 2617 u32 val; 2618 u32 __user *uval = uaddr; 2619 2620 /* Fail if we have unknown bits set. */ 2621 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2622 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2623 return -ENOENT; 2624 2625 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2626 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2627 if (KVM_REG_SIZE(id) != 4) 2628 return -ENOENT; 2629 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2630 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2631 if (!is_valid_cache(val)) 2632 return -ENOENT; 2633 2634 return put_user(get_ccsidr(val), uval); 2635 default: 2636 return -ENOENT; 2637 } 2638 } 2639 2640 static int demux_c15_set(u64 id, void __user *uaddr) 2641 { 2642 u32 val, newval; 2643 u32 __user *uval = uaddr; 2644 2645 /* Fail if we have unknown bits set. */ 2646 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2647 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2648 return -ENOENT; 2649 2650 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2651 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2652 if (KVM_REG_SIZE(id) != 4) 2653 return -ENOENT; 2654 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2655 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2656 if (!is_valid_cache(val)) 2657 return -ENOENT; 2658 2659 if (get_user(newval, uval)) 2660 return -EFAULT; 2661 2662 /* This is also invariant: you can't change it. */ 2663 if (newval != get_ccsidr(val)) 2664 return -EINVAL; 2665 return 0; 2666 default: 2667 return -ENOENT; 2668 } 2669 } 2670 2671 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2672 { 2673 const struct sys_reg_desc *r; 2674 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2675 2676 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2677 return demux_c15_get(reg->id, uaddr); 2678 2679 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2680 return -ENOENT; 2681 2682 r = index_to_sys_reg_desc(vcpu, reg->id); 2683 if (!r) 2684 return get_invariant_sys_reg(reg->id, uaddr); 2685 2686 /* Check for regs disabled by runtime config */ 2687 if (sysreg_hidden_from_user(vcpu, r)) 2688 return -ENOENT; 2689 2690 if (r->get_user) 2691 return (r->get_user)(vcpu, r, reg, uaddr); 2692 2693 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); 2694 } 2695 2696 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2697 { 2698 const struct sys_reg_desc *r; 2699 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2700 2701 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2702 return demux_c15_set(reg->id, uaddr); 2703 2704 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2705 return -ENOENT; 2706 2707 r = index_to_sys_reg_desc(vcpu, reg->id); 2708 if (!r) 2709 return set_invariant_sys_reg(reg->id, uaddr); 2710 2711 /* Check for regs disabled by runtime config */ 2712 if (sysreg_hidden_from_user(vcpu, r)) 2713 return -ENOENT; 2714 2715 if (r->set_user) 2716 return (r->set_user)(vcpu, r, reg, uaddr); 2717 2718 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); 2719 } 2720 2721 static unsigned int num_demux_regs(void) 2722 { 2723 unsigned int i, count = 0; 2724 2725 for (i = 0; i < CSSELR_MAX; i++) 2726 if (is_valid_cache(i)) 2727 count++; 2728 2729 return count; 2730 } 2731 2732 static int write_demux_regids(u64 __user *uindices) 2733 { 2734 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 2735 unsigned int i; 2736 2737 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 2738 for (i = 0; i < CSSELR_MAX; i++) { 2739 if (!is_valid_cache(i)) 2740 continue; 2741 if (put_user(val | i, uindices)) 2742 return -EFAULT; 2743 uindices++; 2744 } 2745 return 0; 2746 } 2747 2748 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 2749 { 2750 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 2751 KVM_REG_ARM64_SYSREG | 2752 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 2753 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 2754 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 2755 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 2756 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 2757 } 2758 2759 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 2760 { 2761 if (!*uind) 2762 return true; 2763 2764 if (put_user(sys_reg_to_index(reg), *uind)) 2765 return false; 2766 2767 (*uind)++; 2768 return true; 2769 } 2770 2771 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 2772 const struct sys_reg_desc *rd, 2773 u64 __user **uind, 2774 unsigned int *total) 2775 { 2776 /* 2777 * Ignore registers we trap but don't save, 2778 * and for which no custom user accessor is provided. 2779 */ 2780 if (!(rd->reg || rd->get_user)) 2781 return 0; 2782 2783 if (sysreg_hidden_from_user(vcpu, rd)) 2784 return 0; 2785 2786 if (!copy_reg_to_user(rd, uind)) 2787 return -EFAULT; 2788 2789 (*total)++; 2790 return 0; 2791 } 2792 2793 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 2794 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 2795 { 2796 const struct sys_reg_desc *i2, *end2; 2797 unsigned int total = 0; 2798 int err; 2799 2800 i2 = sys_reg_descs; 2801 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 2802 2803 while (i2 != end2) { 2804 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 2805 if (err) 2806 return err; 2807 } 2808 return total; 2809 } 2810 2811 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 2812 { 2813 return ARRAY_SIZE(invariant_sys_regs) 2814 + num_demux_regs() 2815 + walk_sys_regs(vcpu, (u64 __user *)NULL); 2816 } 2817 2818 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 2819 { 2820 unsigned int i; 2821 int err; 2822 2823 /* Then give them all the invariant registers' indices. */ 2824 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 2825 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 2826 return -EFAULT; 2827 uindices++; 2828 } 2829 2830 err = walk_sys_regs(vcpu, uindices); 2831 if (err < 0) 2832 return err; 2833 uindices += err; 2834 2835 return write_demux_regids(uindices); 2836 } 2837 2838 void kvm_sys_reg_table_init(void) 2839 { 2840 unsigned int i; 2841 struct sys_reg_desc clidr; 2842 2843 /* Make sure tables are unique and in order. */ 2844 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false)); 2845 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true)); 2846 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true)); 2847 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true)); 2848 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true)); 2849 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false)); 2850 2851 /* We abuse the reset function to overwrite the table itself. */ 2852 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 2853 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 2854 2855 /* 2856 * CLIDR format is awkward, so clean it up. See ARM B4.1.20: 2857 * 2858 * If software reads the Cache Type fields from Ctype1 2859 * upwards, once it has seen a value of 0b000, no caches 2860 * exist at further-out levels of the hierarchy. So, for 2861 * example, if Ctype3 is the first Cache Type field with a 2862 * value of 0b000, the values of Ctype4 to Ctype7 must be 2863 * ignored. 2864 */ 2865 get_clidr_el1(NULL, &clidr); /* Ugly... */ 2866 cache_levels = clidr.val; 2867 for (i = 0; i < 7; i++) 2868 if (((cache_levels >> (i*3)) & 7) == 0) 2869 break; 2870 /* Clear all higher bits. */ 2871 cache_levels &= (1 << (i*3))-1; 2872 } 2873