1 /* 2 * Copyright (C) 2012,2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * Derived from arch/arm/kvm/coproc.c: 6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 7 * Authors: Rusty Russell <rusty@rustcorp.com.au> 8 * Christoffer Dall <c.dall@virtualopensystems.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License, version 2, as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/kvm_host.h> 25 #include <linux/mm.h> 26 #include <linux/printk.h> 27 #include <linux/uaccess.h> 28 29 #include <asm/cacheflush.h> 30 #include <asm/cputype.h> 31 #include <asm/debug-monitors.h> 32 #include <asm/esr.h> 33 #include <asm/kvm_arm.h> 34 #include <asm/kvm_asm.h> 35 #include <asm/kvm_coproc.h> 36 #include <asm/kvm_emulate.h> 37 #include <asm/kvm_host.h> 38 #include <asm/kvm_hyp.h> 39 #include <asm/kvm_mmu.h> 40 #include <asm/perf_event.h> 41 #include <asm/sysreg.h> 42 43 #include <trace/events/kvm.h> 44 45 #include "sys_regs.h" 46 47 #include "trace.h" 48 49 /* 50 * All of this file is extremly similar to the ARM coproc.c, but the 51 * types are different. My gut feeling is that it should be pretty 52 * easy to merge, but that would be an ABI breakage -- again. VFP 53 * would also need to be abstracted. 54 * 55 * For AArch32, we only take care of what is being trapped. Anything 56 * that has to do with init and userspace access has to go via the 57 * 64bit interface. 58 */ 59 60 static bool read_from_write_only(struct kvm_vcpu *vcpu, 61 struct sys_reg_params *params, 62 const struct sys_reg_desc *r) 63 { 64 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 65 print_sys_reg_instr(params); 66 kvm_inject_undefined(vcpu); 67 return false; 68 } 69 70 static bool write_to_read_only(struct kvm_vcpu *vcpu, 71 struct sys_reg_params *params, 72 const struct sys_reg_desc *r) 73 { 74 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 75 print_sys_reg_instr(params); 76 kvm_inject_undefined(vcpu); 77 return false; 78 } 79 80 u64 vcpu_read_sys_reg(struct kvm_vcpu *vcpu, int reg) 81 { 82 if (!vcpu->arch.sysregs_loaded_on_cpu) 83 goto immediate_read; 84 85 /* 86 * System registers listed in the switch are not saved on every 87 * exit from the guest but are only saved on vcpu_put. 88 * 89 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 90 * should never be listed below, because the guest cannot modify its 91 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 92 * thread when emulating cross-VCPU communication. 93 */ 94 switch (reg) { 95 case CSSELR_EL1: return read_sysreg_s(SYS_CSSELR_EL1); 96 case SCTLR_EL1: return read_sysreg_s(sctlr_EL12); 97 case ACTLR_EL1: return read_sysreg_s(SYS_ACTLR_EL1); 98 case CPACR_EL1: return read_sysreg_s(cpacr_EL12); 99 case TTBR0_EL1: return read_sysreg_s(ttbr0_EL12); 100 case TTBR1_EL1: return read_sysreg_s(ttbr1_EL12); 101 case TCR_EL1: return read_sysreg_s(tcr_EL12); 102 case ESR_EL1: return read_sysreg_s(esr_EL12); 103 case AFSR0_EL1: return read_sysreg_s(afsr0_EL12); 104 case AFSR1_EL1: return read_sysreg_s(afsr1_EL12); 105 case FAR_EL1: return read_sysreg_s(far_EL12); 106 case MAIR_EL1: return read_sysreg_s(mair_EL12); 107 case VBAR_EL1: return read_sysreg_s(vbar_EL12); 108 case CONTEXTIDR_EL1: return read_sysreg_s(contextidr_EL12); 109 case TPIDR_EL0: return read_sysreg_s(SYS_TPIDR_EL0); 110 case TPIDRRO_EL0: return read_sysreg_s(SYS_TPIDRRO_EL0); 111 case TPIDR_EL1: return read_sysreg_s(SYS_TPIDR_EL1); 112 case AMAIR_EL1: return read_sysreg_s(amair_EL12); 113 case CNTKCTL_EL1: return read_sysreg_s(cntkctl_EL12); 114 case PAR_EL1: return read_sysreg_s(SYS_PAR_EL1); 115 case DACR32_EL2: return read_sysreg_s(SYS_DACR32_EL2); 116 case IFSR32_EL2: return read_sysreg_s(SYS_IFSR32_EL2); 117 case DBGVCR32_EL2: return read_sysreg_s(SYS_DBGVCR32_EL2); 118 } 119 120 immediate_read: 121 return __vcpu_sys_reg(vcpu, reg); 122 } 123 124 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 125 { 126 if (!vcpu->arch.sysregs_loaded_on_cpu) 127 goto immediate_write; 128 129 /* 130 * System registers listed in the switch are not restored on every 131 * entry to the guest but are only restored on vcpu_load. 132 * 133 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 134 * should never be listed below, because the the MPIDR should only be 135 * set once, before running the VCPU, and never changed later. 136 */ 137 switch (reg) { 138 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); return; 139 case SCTLR_EL1: write_sysreg_s(val, sctlr_EL12); return; 140 case ACTLR_EL1: write_sysreg_s(val, SYS_ACTLR_EL1); return; 141 case CPACR_EL1: write_sysreg_s(val, cpacr_EL12); return; 142 case TTBR0_EL1: write_sysreg_s(val, ttbr0_EL12); return; 143 case TTBR1_EL1: write_sysreg_s(val, ttbr1_EL12); return; 144 case TCR_EL1: write_sysreg_s(val, tcr_EL12); return; 145 case ESR_EL1: write_sysreg_s(val, esr_EL12); return; 146 case AFSR0_EL1: write_sysreg_s(val, afsr0_EL12); return; 147 case AFSR1_EL1: write_sysreg_s(val, afsr1_EL12); return; 148 case FAR_EL1: write_sysreg_s(val, far_EL12); return; 149 case MAIR_EL1: write_sysreg_s(val, mair_EL12); return; 150 case VBAR_EL1: write_sysreg_s(val, vbar_EL12); return; 151 case CONTEXTIDR_EL1: write_sysreg_s(val, contextidr_EL12); return; 152 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); return; 153 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); return; 154 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); return; 155 case AMAIR_EL1: write_sysreg_s(val, amair_EL12); return; 156 case CNTKCTL_EL1: write_sysreg_s(val, cntkctl_EL12); return; 157 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); return; 158 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); return; 159 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); return; 160 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); return; 161 } 162 163 immediate_write: 164 __vcpu_sys_reg(vcpu, reg) = val; 165 } 166 167 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ 168 static u32 cache_levels; 169 170 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 171 #define CSSELR_MAX 12 172 173 /* Which cache CCSIDR represents depends on CSSELR value. */ 174 static u32 get_ccsidr(u32 csselr) 175 { 176 u32 ccsidr; 177 178 /* Make sure noone else changes CSSELR during this! */ 179 local_irq_disable(); 180 write_sysreg(csselr, csselr_el1); 181 isb(); 182 ccsidr = read_sysreg(ccsidr_el1); 183 local_irq_enable(); 184 185 return ccsidr; 186 } 187 188 /* 189 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 190 */ 191 static bool access_dcsw(struct kvm_vcpu *vcpu, 192 struct sys_reg_params *p, 193 const struct sys_reg_desc *r) 194 { 195 if (!p->is_write) 196 return read_from_write_only(vcpu, p, r); 197 198 kvm_set_way_flush(vcpu); 199 return true; 200 } 201 202 /* 203 * Generic accessor for VM registers. Only called as long as HCR_TVM 204 * is set. If the guest enables the MMU, we stop trapping the VM 205 * sys_regs and leave it in complete control of the caches. 206 */ 207 static bool access_vm_reg(struct kvm_vcpu *vcpu, 208 struct sys_reg_params *p, 209 const struct sys_reg_desc *r) 210 { 211 bool was_enabled = vcpu_has_cache_enabled(vcpu); 212 u64 val; 213 int reg = r->reg; 214 215 BUG_ON(!p->is_write); 216 217 /* See the 32bit mapping in kvm_host.h */ 218 if (p->is_aarch32) 219 reg = r->reg / 2; 220 221 if (!p->is_aarch32 || !p->is_32bit) { 222 val = p->regval; 223 } else { 224 val = vcpu_read_sys_reg(vcpu, reg); 225 if (r->reg % 2) 226 val = (p->regval << 32) | (u64)lower_32_bits(val); 227 else 228 val = ((u64)upper_32_bits(val) << 32) | 229 lower_32_bits(p->regval); 230 } 231 vcpu_write_sys_reg(vcpu, val, reg); 232 233 kvm_toggle_cache(vcpu, was_enabled); 234 return true; 235 } 236 237 /* 238 * Trap handler for the GICv3 SGI generation system register. 239 * Forward the request to the VGIC emulation. 240 * The cp15_64 code makes sure this automatically works 241 * for both AArch64 and AArch32 accesses. 242 */ 243 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 244 struct sys_reg_params *p, 245 const struct sys_reg_desc *r) 246 { 247 if (!p->is_write) 248 return read_from_write_only(vcpu, p, r); 249 250 vgic_v3_dispatch_sgi(vcpu, p->regval); 251 252 return true; 253 } 254 255 static bool access_gic_sre(struct kvm_vcpu *vcpu, 256 struct sys_reg_params *p, 257 const struct sys_reg_desc *r) 258 { 259 if (p->is_write) 260 return ignore_write(vcpu, p); 261 262 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 263 return true; 264 } 265 266 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 267 struct sys_reg_params *p, 268 const struct sys_reg_desc *r) 269 { 270 if (p->is_write) 271 return ignore_write(vcpu, p); 272 else 273 return read_zero(vcpu, p); 274 } 275 276 static bool trap_undef(struct kvm_vcpu *vcpu, 277 struct sys_reg_params *p, 278 const struct sys_reg_desc *r) 279 { 280 kvm_inject_undefined(vcpu); 281 return false; 282 } 283 284 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 285 struct sys_reg_params *p, 286 const struct sys_reg_desc *r) 287 { 288 if (p->is_write) { 289 return ignore_write(vcpu, p); 290 } else { 291 p->regval = (1 << 3); 292 return true; 293 } 294 } 295 296 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 297 struct sys_reg_params *p, 298 const struct sys_reg_desc *r) 299 { 300 if (p->is_write) { 301 return ignore_write(vcpu, p); 302 } else { 303 p->regval = read_sysreg(dbgauthstatus_el1); 304 return true; 305 } 306 } 307 308 /* 309 * We want to avoid world-switching all the DBG registers all the 310 * time: 311 * 312 * - If we've touched any debug register, it is likely that we're 313 * going to touch more of them. It then makes sense to disable the 314 * traps and start doing the save/restore dance 315 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 316 * then mandatory to save/restore the registers, as the guest 317 * depends on them. 318 * 319 * For this, we use a DIRTY bit, indicating the guest has modified the 320 * debug registers, used as follow: 321 * 322 * On guest entry: 323 * - If the dirty bit is set (because we're coming back from trapping), 324 * disable the traps, save host registers, restore guest registers. 325 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 326 * set the dirty bit, disable the traps, save host registers, 327 * restore guest registers. 328 * - Otherwise, enable the traps 329 * 330 * On guest exit: 331 * - If the dirty bit is set, save guest registers, restore host 332 * registers and clear the dirty bit. This ensure that the host can 333 * now use the debug registers. 334 */ 335 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 336 struct sys_reg_params *p, 337 const struct sys_reg_desc *r) 338 { 339 if (p->is_write) { 340 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 341 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY; 342 } else { 343 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 344 } 345 346 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 347 348 return true; 349 } 350 351 /* 352 * reg_to_dbg/dbg_to_reg 353 * 354 * A 32 bit write to a debug register leave top bits alone 355 * A 32 bit read from a debug register only returns the bottom bits 356 * 357 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the 358 * hyp.S code switches between host and guest values in future. 359 */ 360 static void reg_to_dbg(struct kvm_vcpu *vcpu, 361 struct sys_reg_params *p, 362 u64 *dbg_reg) 363 { 364 u64 val = p->regval; 365 366 if (p->is_32bit) { 367 val &= 0xffffffffUL; 368 val |= ((*dbg_reg >> 32) << 32); 369 } 370 371 *dbg_reg = val; 372 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY; 373 } 374 375 static void dbg_to_reg(struct kvm_vcpu *vcpu, 376 struct sys_reg_params *p, 377 u64 *dbg_reg) 378 { 379 p->regval = *dbg_reg; 380 if (p->is_32bit) 381 p->regval &= 0xffffffffUL; 382 } 383 384 static bool trap_bvr(struct kvm_vcpu *vcpu, 385 struct sys_reg_params *p, 386 const struct sys_reg_desc *rd) 387 { 388 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 389 390 if (p->is_write) 391 reg_to_dbg(vcpu, p, dbg_reg); 392 else 393 dbg_to_reg(vcpu, p, dbg_reg); 394 395 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 396 397 return true; 398 } 399 400 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 401 const struct kvm_one_reg *reg, void __user *uaddr) 402 { 403 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 404 405 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 406 return -EFAULT; 407 return 0; 408 } 409 410 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 411 const struct kvm_one_reg *reg, void __user *uaddr) 412 { 413 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 414 415 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 416 return -EFAULT; 417 return 0; 418 } 419 420 static void reset_bvr(struct kvm_vcpu *vcpu, 421 const struct sys_reg_desc *rd) 422 { 423 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; 424 } 425 426 static bool trap_bcr(struct kvm_vcpu *vcpu, 427 struct sys_reg_params *p, 428 const struct sys_reg_desc *rd) 429 { 430 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 431 432 if (p->is_write) 433 reg_to_dbg(vcpu, p, dbg_reg); 434 else 435 dbg_to_reg(vcpu, p, dbg_reg); 436 437 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 438 439 return true; 440 } 441 442 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 443 const struct kvm_one_reg *reg, void __user *uaddr) 444 { 445 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 446 447 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 448 return -EFAULT; 449 450 return 0; 451 } 452 453 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 454 const struct kvm_one_reg *reg, void __user *uaddr) 455 { 456 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 457 458 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 459 return -EFAULT; 460 return 0; 461 } 462 463 static void reset_bcr(struct kvm_vcpu *vcpu, 464 const struct sys_reg_desc *rd) 465 { 466 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; 467 } 468 469 static bool trap_wvr(struct kvm_vcpu *vcpu, 470 struct sys_reg_params *p, 471 const struct sys_reg_desc *rd) 472 { 473 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 474 475 if (p->is_write) 476 reg_to_dbg(vcpu, p, dbg_reg); 477 else 478 dbg_to_reg(vcpu, p, dbg_reg); 479 480 trace_trap_reg(__func__, rd->reg, p->is_write, 481 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]); 482 483 return true; 484 } 485 486 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 487 const struct kvm_one_reg *reg, void __user *uaddr) 488 { 489 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 490 491 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 492 return -EFAULT; 493 return 0; 494 } 495 496 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 497 const struct kvm_one_reg *reg, void __user *uaddr) 498 { 499 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 500 501 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 502 return -EFAULT; 503 return 0; 504 } 505 506 static void reset_wvr(struct kvm_vcpu *vcpu, 507 const struct sys_reg_desc *rd) 508 { 509 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; 510 } 511 512 static bool trap_wcr(struct kvm_vcpu *vcpu, 513 struct sys_reg_params *p, 514 const struct sys_reg_desc *rd) 515 { 516 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 517 518 if (p->is_write) 519 reg_to_dbg(vcpu, p, dbg_reg); 520 else 521 dbg_to_reg(vcpu, p, dbg_reg); 522 523 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 524 525 return true; 526 } 527 528 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 529 const struct kvm_one_reg *reg, void __user *uaddr) 530 { 531 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 532 533 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 534 return -EFAULT; 535 return 0; 536 } 537 538 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 539 const struct kvm_one_reg *reg, void __user *uaddr) 540 { 541 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 542 543 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 544 return -EFAULT; 545 return 0; 546 } 547 548 static void reset_wcr(struct kvm_vcpu *vcpu, 549 const struct sys_reg_desc *rd) 550 { 551 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; 552 } 553 554 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 555 { 556 u64 amair = read_sysreg(amair_el1); 557 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 558 } 559 560 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 561 { 562 u64 mpidr; 563 564 /* 565 * Map the vcpu_id into the first three affinity level fields of 566 * the MPIDR. We limit the number of VCPUs in level 0 due to a 567 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 568 * of the GICv3 to be able to address each CPU directly when 569 * sending IPIs. 570 */ 571 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 572 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 573 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 574 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 575 } 576 577 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 578 { 579 u64 pmcr, val; 580 581 pmcr = read_sysreg(pmcr_el0); 582 /* 583 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN 584 * except PMCR.E resetting to zero. 585 */ 586 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) 587 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); 588 __vcpu_sys_reg(vcpu, PMCR_EL0) = val; 589 } 590 591 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 592 { 593 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 594 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 595 596 if (!enabled) 597 kvm_inject_undefined(vcpu); 598 599 return !enabled; 600 } 601 602 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 603 { 604 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 605 } 606 607 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 608 { 609 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 610 } 611 612 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 613 { 614 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 615 } 616 617 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 618 { 619 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 620 } 621 622 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 623 const struct sys_reg_desc *r) 624 { 625 u64 val; 626 627 if (!kvm_arm_pmu_v3_ready(vcpu)) 628 return trap_raz_wi(vcpu, p, r); 629 630 if (pmu_access_el0_disabled(vcpu)) 631 return false; 632 633 if (p->is_write) { 634 /* Only update writeable bits of PMCR */ 635 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 636 val &= ~ARMV8_PMU_PMCR_MASK; 637 val |= p->regval & ARMV8_PMU_PMCR_MASK; 638 __vcpu_sys_reg(vcpu, PMCR_EL0) = val; 639 kvm_pmu_handle_pmcr(vcpu, val); 640 } else { 641 /* PMCR.P & PMCR.C are RAZ */ 642 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 643 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 644 p->regval = val; 645 } 646 647 return true; 648 } 649 650 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 651 const struct sys_reg_desc *r) 652 { 653 if (!kvm_arm_pmu_v3_ready(vcpu)) 654 return trap_raz_wi(vcpu, p, r); 655 656 if (pmu_access_event_counter_el0_disabled(vcpu)) 657 return false; 658 659 if (p->is_write) 660 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 661 else 662 /* return PMSELR.SEL field */ 663 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 664 & ARMV8_PMU_COUNTER_MASK; 665 666 return true; 667 } 668 669 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 670 const struct sys_reg_desc *r) 671 { 672 u64 pmceid; 673 674 if (!kvm_arm_pmu_v3_ready(vcpu)) 675 return trap_raz_wi(vcpu, p, r); 676 677 BUG_ON(p->is_write); 678 679 if (pmu_access_el0_disabled(vcpu)) 680 return false; 681 682 if (!(p->Op2 & 1)) 683 pmceid = read_sysreg(pmceid0_el0); 684 else 685 pmceid = read_sysreg(pmceid1_el0); 686 687 p->regval = pmceid; 688 689 return true; 690 } 691 692 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 693 { 694 u64 pmcr, val; 695 696 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 697 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 698 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 699 kvm_inject_undefined(vcpu); 700 return false; 701 } 702 703 return true; 704 } 705 706 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 707 struct sys_reg_params *p, 708 const struct sys_reg_desc *r) 709 { 710 u64 idx; 711 712 if (!kvm_arm_pmu_v3_ready(vcpu)) 713 return trap_raz_wi(vcpu, p, r); 714 715 if (r->CRn == 9 && r->CRm == 13) { 716 if (r->Op2 == 2) { 717 /* PMXEVCNTR_EL0 */ 718 if (pmu_access_event_counter_el0_disabled(vcpu)) 719 return false; 720 721 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 722 & ARMV8_PMU_COUNTER_MASK; 723 } else if (r->Op2 == 0) { 724 /* PMCCNTR_EL0 */ 725 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 726 return false; 727 728 idx = ARMV8_PMU_CYCLE_IDX; 729 } else { 730 return false; 731 } 732 } else if (r->CRn == 0 && r->CRm == 9) { 733 /* PMCCNTR */ 734 if (pmu_access_event_counter_el0_disabled(vcpu)) 735 return false; 736 737 idx = ARMV8_PMU_CYCLE_IDX; 738 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 739 /* PMEVCNTRn_EL0 */ 740 if (pmu_access_event_counter_el0_disabled(vcpu)) 741 return false; 742 743 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 744 } else { 745 return false; 746 } 747 748 if (!pmu_counter_idx_valid(vcpu, idx)) 749 return false; 750 751 if (p->is_write) { 752 if (pmu_access_el0_disabled(vcpu)) 753 return false; 754 755 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 756 } else { 757 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 758 } 759 760 return true; 761 } 762 763 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 764 const struct sys_reg_desc *r) 765 { 766 u64 idx, reg; 767 768 if (!kvm_arm_pmu_v3_ready(vcpu)) 769 return trap_raz_wi(vcpu, p, r); 770 771 if (pmu_access_el0_disabled(vcpu)) 772 return false; 773 774 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 775 /* PMXEVTYPER_EL0 */ 776 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 777 reg = PMEVTYPER0_EL0 + idx; 778 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 779 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 780 if (idx == ARMV8_PMU_CYCLE_IDX) 781 reg = PMCCFILTR_EL0; 782 else 783 /* PMEVTYPERn_EL0 */ 784 reg = PMEVTYPER0_EL0 + idx; 785 } else { 786 BUG(); 787 } 788 789 if (!pmu_counter_idx_valid(vcpu, idx)) 790 return false; 791 792 if (p->is_write) { 793 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 794 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 795 } else { 796 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 797 } 798 799 return true; 800 } 801 802 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 803 const struct sys_reg_desc *r) 804 { 805 u64 val, mask; 806 807 if (!kvm_arm_pmu_v3_ready(vcpu)) 808 return trap_raz_wi(vcpu, p, r); 809 810 if (pmu_access_el0_disabled(vcpu)) 811 return false; 812 813 mask = kvm_pmu_valid_counter_mask(vcpu); 814 if (p->is_write) { 815 val = p->regval & mask; 816 if (r->Op2 & 0x1) { 817 /* accessing PMCNTENSET_EL0 */ 818 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 819 kvm_pmu_enable_counter(vcpu, val); 820 } else { 821 /* accessing PMCNTENCLR_EL0 */ 822 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 823 kvm_pmu_disable_counter(vcpu, val); 824 } 825 } else { 826 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; 827 } 828 829 return true; 830 } 831 832 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 833 const struct sys_reg_desc *r) 834 { 835 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 836 837 if (!kvm_arm_pmu_v3_ready(vcpu)) 838 return trap_raz_wi(vcpu, p, r); 839 840 if (!vcpu_mode_priv(vcpu)) { 841 kvm_inject_undefined(vcpu); 842 return false; 843 } 844 845 if (p->is_write) { 846 u64 val = p->regval & mask; 847 848 if (r->Op2 & 0x1) 849 /* accessing PMINTENSET_EL1 */ 850 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 851 else 852 /* accessing PMINTENCLR_EL1 */ 853 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 854 } else { 855 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; 856 } 857 858 return true; 859 } 860 861 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 862 const struct sys_reg_desc *r) 863 { 864 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 865 866 if (!kvm_arm_pmu_v3_ready(vcpu)) 867 return trap_raz_wi(vcpu, p, r); 868 869 if (pmu_access_el0_disabled(vcpu)) 870 return false; 871 872 if (p->is_write) { 873 if (r->CRm & 0x2) 874 /* accessing PMOVSSET_EL0 */ 875 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 876 else 877 /* accessing PMOVSCLR_EL0 */ 878 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 879 } else { 880 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; 881 } 882 883 return true; 884 } 885 886 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 887 const struct sys_reg_desc *r) 888 { 889 u64 mask; 890 891 if (!kvm_arm_pmu_v3_ready(vcpu)) 892 return trap_raz_wi(vcpu, p, r); 893 894 if (!p->is_write) 895 return read_from_write_only(vcpu, p, r); 896 897 if (pmu_write_swinc_el0_disabled(vcpu)) 898 return false; 899 900 mask = kvm_pmu_valid_counter_mask(vcpu); 901 kvm_pmu_software_increment(vcpu, p->regval & mask); 902 return true; 903 } 904 905 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 906 const struct sys_reg_desc *r) 907 { 908 if (!kvm_arm_pmu_v3_ready(vcpu)) 909 return trap_raz_wi(vcpu, p, r); 910 911 if (p->is_write) { 912 if (!vcpu_mode_priv(vcpu)) { 913 kvm_inject_undefined(vcpu); 914 return false; 915 } 916 917 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 918 p->regval & ARMV8_PMU_USERENR_MASK; 919 } else { 920 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 921 & ARMV8_PMU_USERENR_MASK; 922 } 923 924 return true; 925 } 926 927 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 928 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 929 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 930 trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \ 931 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 932 trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \ 933 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 934 trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \ 935 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 936 trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr } 937 938 /* Macro to expand the PMEVCNTRn_EL0 register */ 939 #define PMU_PMEVCNTR_EL0(n) \ 940 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \ 941 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), } 942 943 /* Macro to expand the PMEVTYPERn_EL0 register */ 944 #define PMU_PMEVTYPER_EL0(n) \ 945 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \ 946 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), } 947 948 static bool access_cntp_tval(struct kvm_vcpu *vcpu, 949 struct sys_reg_params *p, 950 const struct sys_reg_desc *r) 951 { 952 u64 now = kvm_phys_timer_read(); 953 u64 cval; 954 955 if (p->is_write) { 956 kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, 957 p->regval + now); 958 } else { 959 cval = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL); 960 p->regval = cval - now; 961 } 962 963 return true; 964 } 965 966 static bool access_cntp_ctl(struct kvm_vcpu *vcpu, 967 struct sys_reg_params *p, 968 const struct sys_reg_desc *r) 969 { 970 if (p->is_write) 971 kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CTL, p->regval); 972 else 973 p->regval = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CTL); 974 975 return true; 976 } 977 978 static bool access_cntp_cval(struct kvm_vcpu *vcpu, 979 struct sys_reg_params *p, 980 const struct sys_reg_desc *r) 981 { 982 if (p->is_write) 983 kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, p->regval); 984 else 985 p->regval = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL); 986 987 return true; 988 } 989 990 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 991 static u64 read_id_reg(struct sys_reg_desc const *r, bool raz) 992 { 993 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, 994 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 995 u64 val = raz ? 0 : read_sanitised_ftr_reg(id); 996 997 if (id == SYS_ID_AA64PFR0_EL1) { 998 if (val & (0xfUL << ID_AA64PFR0_SVE_SHIFT)) 999 pr_err_once("kvm [%i]: SVE unsupported for guests, suppressing\n", 1000 task_pid_nr(current)); 1001 1002 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); 1003 } else if (id == SYS_ID_AA64MMFR1_EL1) { 1004 if (val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT)) 1005 pr_err_once("kvm [%i]: LORegions unsupported for guests, suppressing\n", 1006 task_pid_nr(current)); 1007 1008 val &= ~(0xfUL << ID_AA64MMFR1_LOR_SHIFT); 1009 } 1010 1011 return val; 1012 } 1013 1014 /* cpufeature ID register access trap handlers */ 1015 1016 static bool __access_id_reg(struct kvm_vcpu *vcpu, 1017 struct sys_reg_params *p, 1018 const struct sys_reg_desc *r, 1019 bool raz) 1020 { 1021 if (p->is_write) 1022 return write_to_read_only(vcpu, p, r); 1023 1024 p->regval = read_id_reg(r, raz); 1025 return true; 1026 } 1027 1028 static bool access_id_reg(struct kvm_vcpu *vcpu, 1029 struct sys_reg_params *p, 1030 const struct sys_reg_desc *r) 1031 { 1032 return __access_id_reg(vcpu, p, r, false); 1033 } 1034 1035 static bool access_raz_id_reg(struct kvm_vcpu *vcpu, 1036 struct sys_reg_params *p, 1037 const struct sys_reg_desc *r) 1038 { 1039 return __access_id_reg(vcpu, p, r, true); 1040 } 1041 1042 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); 1043 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); 1044 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 1045 1046 /* 1047 * cpufeature ID register user accessors 1048 * 1049 * For now, these registers are immutable for userspace, so no values 1050 * are stored, and for set_id_reg() we don't allow the effective value 1051 * to be changed. 1052 */ 1053 static int __get_id_reg(const struct sys_reg_desc *rd, void __user *uaddr, 1054 bool raz) 1055 { 1056 const u64 id = sys_reg_to_index(rd); 1057 const u64 val = read_id_reg(rd, raz); 1058 1059 return reg_to_user(uaddr, &val, id); 1060 } 1061 1062 static int __set_id_reg(const struct sys_reg_desc *rd, void __user *uaddr, 1063 bool raz) 1064 { 1065 const u64 id = sys_reg_to_index(rd); 1066 int err; 1067 u64 val; 1068 1069 err = reg_from_user(&val, uaddr, id); 1070 if (err) 1071 return err; 1072 1073 /* This is what we mean by invariant: you can't change it. */ 1074 if (val != read_id_reg(rd, raz)) 1075 return -EINVAL; 1076 1077 return 0; 1078 } 1079 1080 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1081 const struct kvm_one_reg *reg, void __user *uaddr) 1082 { 1083 return __get_id_reg(rd, uaddr, false); 1084 } 1085 1086 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1087 const struct kvm_one_reg *reg, void __user *uaddr) 1088 { 1089 return __set_id_reg(rd, uaddr, false); 1090 } 1091 1092 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1093 const struct kvm_one_reg *reg, void __user *uaddr) 1094 { 1095 return __get_id_reg(rd, uaddr, true); 1096 } 1097 1098 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1099 const struct kvm_one_reg *reg, void __user *uaddr) 1100 { 1101 return __set_id_reg(rd, uaddr, true); 1102 } 1103 1104 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1105 #define ID_SANITISED(name) { \ 1106 SYS_DESC(SYS_##name), \ 1107 .access = access_id_reg, \ 1108 .get_user = get_id_reg, \ 1109 .set_user = set_id_reg, \ 1110 } 1111 1112 /* 1113 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1114 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1115 * (1 <= crm < 8, 0 <= Op2 < 8). 1116 */ 1117 #define ID_UNALLOCATED(crm, op2) { \ 1118 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1119 .access = access_raz_id_reg, \ 1120 .get_user = get_raz_id_reg, \ 1121 .set_user = set_raz_id_reg, \ 1122 } 1123 1124 /* 1125 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1126 * For now, these are exposed just like unallocated ID regs: they appear 1127 * RAZ for the guest. 1128 */ 1129 #define ID_HIDDEN(name) { \ 1130 SYS_DESC(SYS_##name), \ 1131 .access = access_raz_id_reg, \ 1132 .get_user = get_raz_id_reg, \ 1133 .set_user = set_raz_id_reg, \ 1134 } 1135 1136 /* 1137 * Architected system registers. 1138 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1139 * 1140 * Debug handling: We do trap most, if not all debug related system 1141 * registers. The implementation is good enough to ensure that a guest 1142 * can use these with minimal performance degradation. The drawback is 1143 * that we don't implement any of the external debug, none of the 1144 * OSlock protocol. This should be revisited if we ever encounter a 1145 * more demanding guest... 1146 */ 1147 static const struct sys_reg_desc sys_reg_descs[] = { 1148 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1149 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1150 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1151 1152 DBG_BCR_BVR_WCR_WVR_EL1(0), 1153 DBG_BCR_BVR_WCR_WVR_EL1(1), 1154 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1155 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1156 DBG_BCR_BVR_WCR_WVR_EL1(2), 1157 DBG_BCR_BVR_WCR_WVR_EL1(3), 1158 DBG_BCR_BVR_WCR_WVR_EL1(4), 1159 DBG_BCR_BVR_WCR_WVR_EL1(5), 1160 DBG_BCR_BVR_WCR_WVR_EL1(6), 1161 DBG_BCR_BVR_WCR_WVR_EL1(7), 1162 DBG_BCR_BVR_WCR_WVR_EL1(8), 1163 DBG_BCR_BVR_WCR_WVR_EL1(9), 1164 DBG_BCR_BVR_WCR_WVR_EL1(10), 1165 DBG_BCR_BVR_WCR_WVR_EL1(11), 1166 DBG_BCR_BVR_WCR_WVR_EL1(12), 1167 DBG_BCR_BVR_WCR_WVR_EL1(13), 1168 DBG_BCR_BVR_WCR_WVR_EL1(14), 1169 DBG_BCR_BVR_WCR_WVR_EL1(15), 1170 1171 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1172 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, 1173 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, 1174 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1175 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1176 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1177 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1178 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1179 1180 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1181 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1182 // DBGDTR[TR]X_EL0 share the same encoding 1183 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1184 1185 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1186 1187 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1188 1189 /* 1190 * ID regs: all ID_SANITISED() entries here must have corresponding 1191 * entries in arm64_ftr_regs[]. 1192 */ 1193 1194 /* AArch64 mappings of the AArch32 ID registers */ 1195 /* CRm=1 */ 1196 ID_SANITISED(ID_PFR0_EL1), 1197 ID_SANITISED(ID_PFR1_EL1), 1198 ID_SANITISED(ID_DFR0_EL1), 1199 ID_HIDDEN(ID_AFR0_EL1), 1200 ID_SANITISED(ID_MMFR0_EL1), 1201 ID_SANITISED(ID_MMFR1_EL1), 1202 ID_SANITISED(ID_MMFR2_EL1), 1203 ID_SANITISED(ID_MMFR3_EL1), 1204 1205 /* CRm=2 */ 1206 ID_SANITISED(ID_ISAR0_EL1), 1207 ID_SANITISED(ID_ISAR1_EL1), 1208 ID_SANITISED(ID_ISAR2_EL1), 1209 ID_SANITISED(ID_ISAR3_EL1), 1210 ID_SANITISED(ID_ISAR4_EL1), 1211 ID_SANITISED(ID_ISAR5_EL1), 1212 ID_SANITISED(ID_MMFR4_EL1), 1213 ID_UNALLOCATED(2,7), 1214 1215 /* CRm=3 */ 1216 ID_SANITISED(MVFR0_EL1), 1217 ID_SANITISED(MVFR1_EL1), 1218 ID_SANITISED(MVFR2_EL1), 1219 ID_UNALLOCATED(3,3), 1220 ID_UNALLOCATED(3,4), 1221 ID_UNALLOCATED(3,5), 1222 ID_UNALLOCATED(3,6), 1223 ID_UNALLOCATED(3,7), 1224 1225 /* AArch64 ID registers */ 1226 /* CRm=4 */ 1227 ID_SANITISED(ID_AA64PFR0_EL1), 1228 ID_SANITISED(ID_AA64PFR1_EL1), 1229 ID_UNALLOCATED(4,2), 1230 ID_UNALLOCATED(4,3), 1231 ID_UNALLOCATED(4,4), 1232 ID_UNALLOCATED(4,5), 1233 ID_UNALLOCATED(4,6), 1234 ID_UNALLOCATED(4,7), 1235 1236 /* CRm=5 */ 1237 ID_SANITISED(ID_AA64DFR0_EL1), 1238 ID_SANITISED(ID_AA64DFR1_EL1), 1239 ID_UNALLOCATED(5,2), 1240 ID_UNALLOCATED(5,3), 1241 ID_HIDDEN(ID_AA64AFR0_EL1), 1242 ID_HIDDEN(ID_AA64AFR1_EL1), 1243 ID_UNALLOCATED(5,6), 1244 ID_UNALLOCATED(5,7), 1245 1246 /* CRm=6 */ 1247 ID_SANITISED(ID_AA64ISAR0_EL1), 1248 ID_SANITISED(ID_AA64ISAR1_EL1), 1249 ID_UNALLOCATED(6,2), 1250 ID_UNALLOCATED(6,3), 1251 ID_UNALLOCATED(6,4), 1252 ID_UNALLOCATED(6,5), 1253 ID_UNALLOCATED(6,6), 1254 ID_UNALLOCATED(6,7), 1255 1256 /* CRm=7 */ 1257 ID_SANITISED(ID_AA64MMFR0_EL1), 1258 ID_SANITISED(ID_AA64MMFR1_EL1), 1259 ID_SANITISED(ID_AA64MMFR2_EL1), 1260 ID_UNALLOCATED(7,3), 1261 ID_UNALLOCATED(7,4), 1262 ID_UNALLOCATED(7,5), 1263 ID_UNALLOCATED(7,6), 1264 ID_UNALLOCATED(7,7), 1265 1266 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1267 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1268 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1269 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1270 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1271 1272 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1273 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1274 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1275 1276 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1277 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1278 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1279 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1280 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1281 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1282 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1283 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1284 1285 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1286 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1287 1288 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, 1289 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 }, 1290 1291 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1292 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1293 1294 { SYS_DESC(SYS_LORSA_EL1), trap_undef }, 1295 { SYS_DESC(SYS_LOREA_EL1), trap_undef }, 1296 { SYS_DESC(SYS_LORN_EL1), trap_undef }, 1297 { SYS_DESC(SYS_LORC_EL1), trap_undef }, 1298 { SYS_DESC(SYS_LORID_EL1), trap_undef }, 1299 1300 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, 1301 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1302 1303 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1304 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1305 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1306 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1307 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1308 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1309 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1310 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1311 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1312 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1313 1314 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1315 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1316 1317 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1318 1319 { SYS_DESC(SYS_CSSELR_EL1), NULL, reset_unknown, CSSELR_EL1 }, 1320 1321 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, }, 1322 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, 1323 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 }, 1324 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 }, 1325 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 }, 1326 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 }, 1327 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid }, 1328 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid }, 1329 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 }, 1330 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper }, 1331 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr }, 1332 /* 1333 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1334 * in 32bit mode. Here we choose to reset it as zero for consistency. 1335 */ 1336 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 }, 1337 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, 1338 1339 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 1340 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 1341 1342 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_cntp_tval }, 1343 { SYS_DESC(SYS_CNTP_CTL_EL0), access_cntp_ctl }, 1344 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_cntp_cval }, 1345 1346 /* PMEVCNTRn_EL0 */ 1347 PMU_PMEVCNTR_EL0(0), 1348 PMU_PMEVCNTR_EL0(1), 1349 PMU_PMEVCNTR_EL0(2), 1350 PMU_PMEVCNTR_EL0(3), 1351 PMU_PMEVCNTR_EL0(4), 1352 PMU_PMEVCNTR_EL0(5), 1353 PMU_PMEVCNTR_EL0(6), 1354 PMU_PMEVCNTR_EL0(7), 1355 PMU_PMEVCNTR_EL0(8), 1356 PMU_PMEVCNTR_EL0(9), 1357 PMU_PMEVCNTR_EL0(10), 1358 PMU_PMEVCNTR_EL0(11), 1359 PMU_PMEVCNTR_EL0(12), 1360 PMU_PMEVCNTR_EL0(13), 1361 PMU_PMEVCNTR_EL0(14), 1362 PMU_PMEVCNTR_EL0(15), 1363 PMU_PMEVCNTR_EL0(16), 1364 PMU_PMEVCNTR_EL0(17), 1365 PMU_PMEVCNTR_EL0(18), 1366 PMU_PMEVCNTR_EL0(19), 1367 PMU_PMEVCNTR_EL0(20), 1368 PMU_PMEVCNTR_EL0(21), 1369 PMU_PMEVCNTR_EL0(22), 1370 PMU_PMEVCNTR_EL0(23), 1371 PMU_PMEVCNTR_EL0(24), 1372 PMU_PMEVCNTR_EL0(25), 1373 PMU_PMEVCNTR_EL0(26), 1374 PMU_PMEVCNTR_EL0(27), 1375 PMU_PMEVCNTR_EL0(28), 1376 PMU_PMEVCNTR_EL0(29), 1377 PMU_PMEVCNTR_EL0(30), 1378 /* PMEVTYPERn_EL0 */ 1379 PMU_PMEVTYPER_EL0(0), 1380 PMU_PMEVTYPER_EL0(1), 1381 PMU_PMEVTYPER_EL0(2), 1382 PMU_PMEVTYPER_EL0(3), 1383 PMU_PMEVTYPER_EL0(4), 1384 PMU_PMEVTYPER_EL0(5), 1385 PMU_PMEVTYPER_EL0(6), 1386 PMU_PMEVTYPER_EL0(7), 1387 PMU_PMEVTYPER_EL0(8), 1388 PMU_PMEVTYPER_EL0(9), 1389 PMU_PMEVTYPER_EL0(10), 1390 PMU_PMEVTYPER_EL0(11), 1391 PMU_PMEVTYPER_EL0(12), 1392 PMU_PMEVTYPER_EL0(13), 1393 PMU_PMEVTYPER_EL0(14), 1394 PMU_PMEVTYPER_EL0(15), 1395 PMU_PMEVTYPER_EL0(16), 1396 PMU_PMEVTYPER_EL0(17), 1397 PMU_PMEVTYPER_EL0(18), 1398 PMU_PMEVTYPER_EL0(19), 1399 PMU_PMEVTYPER_EL0(20), 1400 PMU_PMEVTYPER_EL0(21), 1401 PMU_PMEVTYPER_EL0(22), 1402 PMU_PMEVTYPER_EL0(23), 1403 PMU_PMEVTYPER_EL0(24), 1404 PMU_PMEVTYPER_EL0(25), 1405 PMU_PMEVTYPER_EL0(26), 1406 PMU_PMEVTYPER_EL0(27), 1407 PMU_PMEVTYPER_EL0(28), 1408 PMU_PMEVTYPER_EL0(29), 1409 PMU_PMEVTYPER_EL0(30), 1410 /* 1411 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 1412 * in 32bit mode. Here we choose to reset it as zero for consistency. 1413 */ 1414 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 }, 1415 1416 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 1417 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 1418 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x70 }, 1419 }; 1420 1421 static bool trap_dbgidr(struct kvm_vcpu *vcpu, 1422 struct sys_reg_params *p, 1423 const struct sys_reg_desc *r) 1424 { 1425 if (p->is_write) { 1426 return ignore_write(vcpu, p); 1427 } else { 1428 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1429 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1430 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); 1431 1432 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | 1433 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | 1434 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) 1435 | (6 << 16) | (el3 << 14) | (el3 << 12)); 1436 return true; 1437 } 1438 } 1439 1440 static bool trap_debug32(struct kvm_vcpu *vcpu, 1441 struct sys_reg_params *p, 1442 const struct sys_reg_desc *r) 1443 { 1444 if (p->is_write) { 1445 vcpu_cp14(vcpu, r->reg) = p->regval; 1446 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY; 1447 } else { 1448 p->regval = vcpu_cp14(vcpu, r->reg); 1449 } 1450 1451 return true; 1452 } 1453 1454 /* AArch32 debug register mappings 1455 * 1456 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 1457 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 1458 * 1459 * All control registers and watchpoint value registers are mapped to 1460 * the lower 32 bits of their AArch64 equivalents. We share the trap 1461 * handlers with the above AArch64 code which checks what mode the 1462 * system is in. 1463 */ 1464 1465 static bool trap_xvr(struct kvm_vcpu *vcpu, 1466 struct sys_reg_params *p, 1467 const struct sys_reg_desc *rd) 1468 { 1469 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 1470 1471 if (p->is_write) { 1472 u64 val = *dbg_reg; 1473 1474 val &= 0xffffffffUL; 1475 val |= p->regval << 32; 1476 *dbg_reg = val; 1477 1478 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY; 1479 } else { 1480 p->regval = *dbg_reg >> 32; 1481 } 1482 1483 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 1484 1485 return true; 1486 } 1487 1488 #define DBG_BCR_BVR_WCR_WVR(n) \ 1489 /* DBGBVRn */ \ 1490 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 1491 /* DBGBCRn */ \ 1492 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 1493 /* DBGWVRn */ \ 1494 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 1495 /* DBGWCRn */ \ 1496 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 1497 1498 #define DBGBXVR(n) \ 1499 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n } 1500 1501 /* 1502 * Trapped cp14 registers. We generally ignore most of the external 1503 * debug, on the principle that they don't really make sense to a 1504 * guest. Revisit this one day, would this principle change. 1505 */ 1506 static const struct sys_reg_desc cp14_regs[] = { 1507 /* DBGIDR */ 1508 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr }, 1509 /* DBGDTRRXext */ 1510 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 1511 1512 DBG_BCR_BVR_WCR_WVR(0), 1513 /* DBGDSCRint */ 1514 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 1515 DBG_BCR_BVR_WCR_WVR(1), 1516 /* DBGDCCINT */ 1517 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 }, 1518 /* DBGDSCRext */ 1519 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 }, 1520 DBG_BCR_BVR_WCR_WVR(2), 1521 /* DBGDTR[RT]Xint */ 1522 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 1523 /* DBGDTR[RT]Xext */ 1524 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 1525 DBG_BCR_BVR_WCR_WVR(3), 1526 DBG_BCR_BVR_WCR_WVR(4), 1527 DBG_BCR_BVR_WCR_WVR(5), 1528 /* DBGWFAR */ 1529 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 1530 /* DBGOSECCR */ 1531 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 1532 DBG_BCR_BVR_WCR_WVR(6), 1533 /* DBGVCR */ 1534 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 }, 1535 DBG_BCR_BVR_WCR_WVR(7), 1536 DBG_BCR_BVR_WCR_WVR(8), 1537 DBG_BCR_BVR_WCR_WVR(9), 1538 DBG_BCR_BVR_WCR_WVR(10), 1539 DBG_BCR_BVR_WCR_WVR(11), 1540 DBG_BCR_BVR_WCR_WVR(12), 1541 DBG_BCR_BVR_WCR_WVR(13), 1542 DBG_BCR_BVR_WCR_WVR(14), 1543 DBG_BCR_BVR_WCR_WVR(15), 1544 1545 /* DBGDRAR (32bit) */ 1546 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 1547 1548 DBGBXVR(0), 1549 /* DBGOSLAR */ 1550 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, 1551 DBGBXVR(1), 1552 /* DBGOSLSR */ 1553 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, 1554 DBGBXVR(2), 1555 DBGBXVR(3), 1556 /* DBGOSDLR */ 1557 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 1558 DBGBXVR(4), 1559 /* DBGPRCR */ 1560 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 1561 DBGBXVR(5), 1562 DBGBXVR(6), 1563 DBGBXVR(7), 1564 DBGBXVR(8), 1565 DBGBXVR(9), 1566 DBGBXVR(10), 1567 DBGBXVR(11), 1568 DBGBXVR(12), 1569 DBGBXVR(13), 1570 DBGBXVR(14), 1571 DBGBXVR(15), 1572 1573 /* DBGDSAR (32bit) */ 1574 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 1575 1576 /* DBGDEVID2 */ 1577 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 1578 /* DBGDEVID1 */ 1579 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 1580 /* DBGDEVID */ 1581 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 1582 /* DBGCLAIMSET */ 1583 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 1584 /* DBGCLAIMCLR */ 1585 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 1586 /* DBGAUTHSTATUS */ 1587 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 1588 }; 1589 1590 /* Trapped cp14 64bit registers */ 1591 static const struct sys_reg_desc cp14_64_regs[] = { 1592 /* DBGDRAR (64bit) */ 1593 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 1594 1595 /* DBGDSAR (64bit) */ 1596 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 1597 }; 1598 1599 /* Macro to expand the PMEVCNTRn register */ 1600 #define PMU_PMEVCNTR(n) \ 1601 /* PMEVCNTRn */ \ 1602 { Op1(0), CRn(0b1110), \ 1603 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1604 access_pmu_evcntr } 1605 1606 /* Macro to expand the PMEVTYPERn register */ 1607 #define PMU_PMEVTYPER(n) \ 1608 /* PMEVTYPERn */ \ 1609 { Op1(0), CRn(0b1110), \ 1610 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1611 access_pmu_evtyper } 1612 1613 /* 1614 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 1615 * depending on the way they are accessed (as a 32bit or a 64bit 1616 * register). 1617 */ 1618 static const struct sys_reg_desc cp15_regs[] = { 1619 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, 1620 1621 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR }, 1622 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 1623 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 }, 1624 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR }, 1625 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR }, 1626 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR }, 1627 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR }, 1628 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR }, 1629 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR }, 1630 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR }, 1631 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR }, 1632 1633 /* 1634 * DC{C,I,CI}SW operations: 1635 */ 1636 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 1637 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 1638 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 1639 1640 /* PMU */ 1641 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, 1642 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, 1643 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, 1644 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, 1645 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, 1646 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, 1647 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, 1648 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, 1649 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, 1650 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, 1651 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, 1652 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, 1653 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, 1654 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, 1655 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, 1656 1657 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, 1658 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, 1659 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 }, 1660 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, 1661 1662 /* ICC_SRE */ 1663 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 1664 1665 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, 1666 1667 /* CNTP_TVAL */ 1668 { Op1( 0), CRn(14), CRm( 2), Op2( 0), access_cntp_tval }, 1669 /* CNTP_CTL */ 1670 { Op1( 0), CRn(14), CRm( 2), Op2( 1), access_cntp_ctl }, 1671 1672 /* PMEVCNTRn */ 1673 PMU_PMEVCNTR(0), 1674 PMU_PMEVCNTR(1), 1675 PMU_PMEVCNTR(2), 1676 PMU_PMEVCNTR(3), 1677 PMU_PMEVCNTR(4), 1678 PMU_PMEVCNTR(5), 1679 PMU_PMEVCNTR(6), 1680 PMU_PMEVCNTR(7), 1681 PMU_PMEVCNTR(8), 1682 PMU_PMEVCNTR(9), 1683 PMU_PMEVCNTR(10), 1684 PMU_PMEVCNTR(11), 1685 PMU_PMEVCNTR(12), 1686 PMU_PMEVCNTR(13), 1687 PMU_PMEVCNTR(14), 1688 PMU_PMEVCNTR(15), 1689 PMU_PMEVCNTR(16), 1690 PMU_PMEVCNTR(17), 1691 PMU_PMEVCNTR(18), 1692 PMU_PMEVCNTR(19), 1693 PMU_PMEVCNTR(20), 1694 PMU_PMEVCNTR(21), 1695 PMU_PMEVCNTR(22), 1696 PMU_PMEVCNTR(23), 1697 PMU_PMEVCNTR(24), 1698 PMU_PMEVCNTR(25), 1699 PMU_PMEVCNTR(26), 1700 PMU_PMEVCNTR(27), 1701 PMU_PMEVCNTR(28), 1702 PMU_PMEVCNTR(29), 1703 PMU_PMEVCNTR(30), 1704 /* PMEVTYPERn */ 1705 PMU_PMEVTYPER(0), 1706 PMU_PMEVTYPER(1), 1707 PMU_PMEVTYPER(2), 1708 PMU_PMEVTYPER(3), 1709 PMU_PMEVTYPER(4), 1710 PMU_PMEVTYPER(5), 1711 PMU_PMEVTYPER(6), 1712 PMU_PMEVTYPER(7), 1713 PMU_PMEVTYPER(8), 1714 PMU_PMEVTYPER(9), 1715 PMU_PMEVTYPER(10), 1716 PMU_PMEVTYPER(11), 1717 PMU_PMEVTYPER(12), 1718 PMU_PMEVTYPER(13), 1719 PMU_PMEVTYPER(14), 1720 PMU_PMEVTYPER(15), 1721 PMU_PMEVTYPER(16), 1722 PMU_PMEVTYPER(17), 1723 PMU_PMEVTYPER(18), 1724 PMU_PMEVTYPER(19), 1725 PMU_PMEVTYPER(20), 1726 PMU_PMEVTYPER(21), 1727 PMU_PMEVTYPER(22), 1728 PMU_PMEVTYPER(23), 1729 PMU_PMEVTYPER(24), 1730 PMU_PMEVTYPER(25), 1731 PMU_PMEVTYPER(26), 1732 PMU_PMEVTYPER(27), 1733 PMU_PMEVTYPER(28), 1734 PMU_PMEVTYPER(29), 1735 PMU_PMEVTYPER(30), 1736 /* PMCCFILTR */ 1737 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, 1738 }; 1739 1740 static const struct sys_reg_desc cp15_64_regs[] = { 1741 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 1742 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, 1743 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, 1744 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, 1745 { Op1( 2), CRn( 0), CRm(14), Op2( 0), access_cntp_cval }, 1746 }; 1747 1748 /* Target specific emulation tables */ 1749 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS]; 1750 1751 void kvm_register_target_sys_reg_table(unsigned int target, 1752 struct kvm_sys_reg_target_table *table) 1753 { 1754 target_tables[target] = table; 1755 } 1756 1757 /* Get specific register table for this target. */ 1758 static const struct sys_reg_desc *get_target_table(unsigned target, 1759 bool mode_is_64, 1760 size_t *num) 1761 { 1762 struct kvm_sys_reg_target_table *table; 1763 1764 table = target_tables[target]; 1765 if (mode_is_64) { 1766 *num = table->table64.num; 1767 return table->table64.table; 1768 } else { 1769 *num = table->table32.num; 1770 return table->table32.table; 1771 } 1772 } 1773 1774 #define reg_to_match_value(x) \ 1775 ({ \ 1776 unsigned long val; \ 1777 val = (x)->Op0 << 14; \ 1778 val |= (x)->Op1 << 11; \ 1779 val |= (x)->CRn << 7; \ 1780 val |= (x)->CRm << 3; \ 1781 val |= (x)->Op2; \ 1782 val; \ 1783 }) 1784 1785 static int match_sys_reg(const void *key, const void *elt) 1786 { 1787 const unsigned long pval = (unsigned long)key; 1788 const struct sys_reg_desc *r = elt; 1789 1790 return pval - reg_to_match_value(r); 1791 } 1792 1793 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params, 1794 const struct sys_reg_desc table[], 1795 unsigned int num) 1796 { 1797 unsigned long pval = reg_to_match_value(params); 1798 1799 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg); 1800 } 1801 1802 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run) 1803 { 1804 kvm_inject_undefined(vcpu); 1805 return 1; 1806 } 1807 1808 static void perform_access(struct kvm_vcpu *vcpu, 1809 struct sys_reg_params *params, 1810 const struct sys_reg_desc *r) 1811 { 1812 /* 1813 * Not having an accessor means that we have configured a trap 1814 * that we don't know how to handle. This certainly qualifies 1815 * as a gross bug that should be fixed right away. 1816 */ 1817 BUG_ON(!r->access); 1818 1819 /* Skip instruction if instructed so */ 1820 if (likely(r->access(vcpu, params, r))) 1821 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); 1822 } 1823 1824 /* 1825 * emulate_cp -- tries to match a sys_reg access in a handling table, and 1826 * call the corresponding trap handler. 1827 * 1828 * @params: pointer to the descriptor of the access 1829 * @table: array of trap descriptors 1830 * @num: size of the trap descriptor array 1831 * 1832 * Return 0 if the access has been handled, and -1 if not. 1833 */ 1834 static int emulate_cp(struct kvm_vcpu *vcpu, 1835 struct sys_reg_params *params, 1836 const struct sys_reg_desc *table, 1837 size_t num) 1838 { 1839 const struct sys_reg_desc *r; 1840 1841 if (!table) 1842 return -1; /* Not handled */ 1843 1844 r = find_reg(params, table, num); 1845 1846 if (r) { 1847 perform_access(vcpu, params, r); 1848 return 0; 1849 } 1850 1851 /* Not handled */ 1852 return -1; 1853 } 1854 1855 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 1856 struct sys_reg_params *params) 1857 { 1858 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu); 1859 int cp = -1; 1860 1861 switch(hsr_ec) { 1862 case ESR_ELx_EC_CP15_32: 1863 case ESR_ELx_EC_CP15_64: 1864 cp = 15; 1865 break; 1866 case ESR_ELx_EC_CP14_MR: 1867 case ESR_ELx_EC_CP14_64: 1868 cp = 14; 1869 break; 1870 default: 1871 WARN_ON(1); 1872 } 1873 1874 kvm_err("Unsupported guest CP%d access at: %08lx\n", 1875 cp, *vcpu_pc(vcpu)); 1876 print_sys_reg_instr(params); 1877 kvm_inject_undefined(vcpu); 1878 } 1879 1880 /** 1881 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 1882 * @vcpu: The VCPU pointer 1883 * @run: The kvm_run struct 1884 */ 1885 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 1886 const struct sys_reg_desc *global, 1887 size_t nr_global, 1888 const struct sys_reg_desc *target_specific, 1889 size_t nr_specific) 1890 { 1891 struct sys_reg_params params; 1892 u32 hsr = kvm_vcpu_get_hsr(vcpu); 1893 int Rt = kvm_vcpu_sys_get_rt(vcpu); 1894 int Rt2 = (hsr >> 10) & 0x1f; 1895 1896 params.is_aarch32 = true; 1897 params.is_32bit = false; 1898 params.CRm = (hsr >> 1) & 0xf; 1899 params.is_write = ((hsr & 1) == 0); 1900 1901 params.Op0 = 0; 1902 params.Op1 = (hsr >> 16) & 0xf; 1903 params.Op2 = 0; 1904 params.CRn = 0; 1905 1906 /* 1907 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 1908 * backends between AArch32 and AArch64, we get away with it. 1909 */ 1910 if (params.is_write) { 1911 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 1912 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 1913 } 1914 1915 /* 1916 * Try to emulate the coprocessor access using the target 1917 * specific table first, and using the global table afterwards. 1918 * If either of the tables contains a handler, handle the 1919 * potential register operation in the case of a read and return 1920 * with success. 1921 */ 1922 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) || 1923 !emulate_cp(vcpu, ¶ms, global, nr_global)) { 1924 /* Split up the value between registers for the read side */ 1925 if (!params.is_write) { 1926 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 1927 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 1928 } 1929 1930 return 1; 1931 } 1932 1933 unhandled_cp_access(vcpu, ¶ms); 1934 return 1; 1935 } 1936 1937 /** 1938 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 1939 * @vcpu: The VCPU pointer 1940 * @run: The kvm_run struct 1941 */ 1942 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 1943 const struct sys_reg_desc *global, 1944 size_t nr_global, 1945 const struct sys_reg_desc *target_specific, 1946 size_t nr_specific) 1947 { 1948 struct sys_reg_params params; 1949 u32 hsr = kvm_vcpu_get_hsr(vcpu); 1950 int Rt = kvm_vcpu_sys_get_rt(vcpu); 1951 1952 params.is_aarch32 = true; 1953 params.is_32bit = true; 1954 params.CRm = (hsr >> 1) & 0xf; 1955 params.regval = vcpu_get_reg(vcpu, Rt); 1956 params.is_write = ((hsr & 1) == 0); 1957 params.CRn = (hsr >> 10) & 0xf; 1958 params.Op0 = 0; 1959 params.Op1 = (hsr >> 14) & 0x7; 1960 params.Op2 = (hsr >> 17) & 0x7; 1961 1962 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) || 1963 !emulate_cp(vcpu, ¶ms, global, nr_global)) { 1964 if (!params.is_write) 1965 vcpu_set_reg(vcpu, Rt, params.regval); 1966 return 1; 1967 } 1968 1969 unhandled_cp_access(vcpu, ¶ms); 1970 return 1; 1971 } 1972 1973 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run) 1974 { 1975 const struct sys_reg_desc *target_specific; 1976 size_t num; 1977 1978 target_specific = get_target_table(vcpu->arch.target, false, &num); 1979 return kvm_handle_cp_64(vcpu, 1980 cp15_64_regs, ARRAY_SIZE(cp15_64_regs), 1981 target_specific, num); 1982 } 1983 1984 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run) 1985 { 1986 const struct sys_reg_desc *target_specific; 1987 size_t num; 1988 1989 target_specific = get_target_table(vcpu->arch.target, false, &num); 1990 return kvm_handle_cp_32(vcpu, 1991 cp15_regs, ARRAY_SIZE(cp15_regs), 1992 target_specific, num); 1993 } 1994 1995 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run) 1996 { 1997 return kvm_handle_cp_64(vcpu, 1998 cp14_64_regs, ARRAY_SIZE(cp14_64_regs), 1999 NULL, 0); 2000 } 2001 2002 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run) 2003 { 2004 return kvm_handle_cp_32(vcpu, 2005 cp14_regs, ARRAY_SIZE(cp14_regs), 2006 NULL, 0); 2007 } 2008 2009 static int emulate_sys_reg(struct kvm_vcpu *vcpu, 2010 struct sys_reg_params *params) 2011 { 2012 size_t num; 2013 const struct sys_reg_desc *table, *r; 2014 2015 table = get_target_table(vcpu->arch.target, true, &num); 2016 2017 /* Search target-specific then generic table. */ 2018 r = find_reg(params, table, num); 2019 if (!r) 2020 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2021 2022 if (likely(r)) { 2023 perform_access(vcpu, params, r); 2024 } else { 2025 kvm_err("Unsupported guest sys_reg access at: %lx\n", 2026 *vcpu_pc(vcpu)); 2027 print_sys_reg_instr(params); 2028 kvm_inject_undefined(vcpu); 2029 } 2030 return 1; 2031 } 2032 2033 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu, 2034 const struct sys_reg_desc *table, size_t num) 2035 { 2036 unsigned long i; 2037 2038 for (i = 0; i < num; i++) 2039 if (table[i].reset) 2040 table[i].reset(vcpu, &table[i]); 2041 } 2042 2043 /** 2044 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2045 * @vcpu: The VCPU pointer 2046 * @run: The kvm_run struct 2047 */ 2048 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run) 2049 { 2050 struct sys_reg_params params; 2051 unsigned long esr = kvm_vcpu_get_hsr(vcpu); 2052 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2053 int ret; 2054 2055 trace_kvm_handle_sys_reg(esr); 2056 2057 params.is_aarch32 = false; 2058 params.is_32bit = false; 2059 params.Op0 = (esr >> 20) & 3; 2060 params.Op1 = (esr >> 14) & 0x7; 2061 params.CRn = (esr >> 10) & 0xf; 2062 params.CRm = (esr >> 1) & 0xf; 2063 params.Op2 = (esr >> 17) & 0x7; 2064 params.regval = vcpu_get_reg(vcpu, Rt); 2065 params.is_write = !(esr & 1); 2066 2067 ret = emulate_sys_reg(vcpu, ¶ms); 2068 2069 if (!params.is_write) 2070 vcpu_set_reg(vcpu, Rt, params.regval); 2071 return ret; 2072 } 2073 2074 /****************************************************************************** 2075 * Userspace API 2076 *****************************************************************************/ 2077 2078 static bool index_to_params(u64 id, struct sys_reg_params *params) 2079 { 2080 switch (id & KVM_REG_SIZE_MASK) { 2081 case KVM_REG_SIZE_U64: 2082 /* Any unused index bits means it's not valid. */ 2083 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2084 | KVM_REG_ARM_COPROC_MASK 2085 | KVM_REG_ARM64_SYSREG_OP0_MASK 2086 | KVM_REG_ARM64_SYSREG_OP1_MASK 2087 | KVM_REG_ARM64_SYSREG_CRN_MASK 2088 | KVM_REG_ARM64_SYSREG_CRM_MASK 2089 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2090 return false; 2091 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2092 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2093 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2094 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2095 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2096 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2097 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2098 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2099 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2100 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2101 return true; 2102 default: 2103 return false; 2104 } 2105 } 2106 2107 const struct sys_reg_desc *find_reg_by_id(u64 id, 2108 struct sys_reg_params *params, 2109 const struct sys_reg_desc table[], 2110 unsigned int num) 2111 { 2112 if (!index_to_params(id, params)) 2113 return NULL; 2114 2115 return find_reg(params, table, num); 2116 } 2117 2118 /* Decode an index value, and find the sys_reg_desc entry. */ 2119 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, 2120 u64 id) 2121 { 2122 size_t num; 2123 const struct sys_reg_desc *table, *r; 2124 struct sys_reg_params params; 2125 2126 /* We only do sys_reg for now. */ 2127 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2128 return NULL; 2129 2130 table = get_target_table(vcpu->arch.target, true, &num); 2131 r = find_reg_by_id(id, ¶ms, table, num); 2132 if (!r) 2133 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2134 2135 /* Not saved in the sys_reg array and not otherwise accessible? */ 2136 if (r && !(r->reg || r->get_user)) 2137 r = NULL; 2138 2139 return r; 2140 } 2141 2142 /* 2143 * These are the invariant sys_reg registers: we let the guest see the 2144 * host versions of these, so they're part of the guest state. 2145 * 2146 * A future CPU may provide a mechanism to present different values to 2147 * the guest, or a future kvm may trap them. 2148 */ 2149 2150 #define FUNCTION_INVARIANT(reg) \ 2151 static void get_##reg(struct kvm_vcpu *v, \ 2152 const struct sys_reg_desc *r) \ 2153 { \ 2154 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 2155 } 2156 2157 FUNCTION_INVARIANT(midr_el1) 2158 FUNCTION_INVARIANT(ctr_el0) 2159 FUNCTION_INVARIANT(revidr_el1) 2160 FUNCTION_INVARIANT(clidr_el1) 2161 FUNCTION_INVARIANT(aidr_el1) 2162 2163 /* ->val is filled in by kvm_sys_reg_table_init() */ 2164 static struct sys_reg_desc invariant_sys_regs[] = { 2165 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 2166 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 2167 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, 2168 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 2169 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 2170 }; 2171 2172 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) 2173 { 2174 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) 2175 return -EFAULT; 2176 return 0; 2177 } 2178 2179 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) 2180 { 2181 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) 2182 return -EFAULT; 2183 return 0; 2184 } 2185 2186 static int get_invariant_sys_reg(u64 id, void __user *uaddr) 2187 { 2188 struct sys_reg_params params; 2189 const struct sys_reg_desc *r; 2190 2191 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2192 ARRAY_SIZE(invariant_sys_regs)); 2193 if (!r) 2194 return -ENOENT; 2195 2196 return reg_to_user(uaddr, &r->val, id); 2197 } 2198 2199 static int set_invariant_sys_reg(u64 id, void __user *uaddr) 2200 { 2201 struct sys_reg_params params; 2202 const struct sys_reg_desc *r; 2203 int err; 2204 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ 2205 2206 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2207 ARRAY_SIZE(invariant_sys_regs)); 2208 if (!r) 2209 return -ENOENT; 2210 2211 err = reg_from_user(&val, uaddr, id); 2212 if (err) 2213 return err; 2214 2215 /* This is what we mean by invariant: you can't change it. */ 2216 if (r->val != val) 2217 return -EINVAL; 2218 2219 return 0; 2220 } 2221 2222 static bool is_valid_cache(u32 val) 2223 { 2224 u32 level, ctype; 2225 2226 if (val >= CSSELR_MAX) 2227 return false; 2228 2229 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 2230 level = (val >> 1); 2231 ctype = (cache_levels >> (level * 3)) & 7; 2232 2233 switch (ctype) { 2234 case 0: /* No cache */ 2235 return false; 2236 case 1: /* Instruction cache only */ 2237 return (val & 1); 2238 case 2: /* Data cache only */ 2239 case 4: /* Unified cache */ 2240 return !(val & 1); 2241 case 3: /* Separate instruction and data caches */ 2242 return true; 2243 default: /* Reserved: we can't know instruction or data. */ 2244 return false; 2245 } 2246 } 2247 2248 static int demux_c15_get(u64 id, void __user *uaddr) 2249 { 2250 u32 val; 2251 u32 __user *uval = uaddr; 2252 2253 /* Fail if we have unknown bits set. */ 2254 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2255 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2256 return -ENOENT; 2257 2258 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2259 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2260 if (KVM_REG_SIZE(id) != 4) 2261 return -ENOENT; 2262 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2263 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2264 if (!is_valid_cache(val)) 2265 return -ENOENT; 2266 2267 return put_user(get_ccsidr(val), uval); 2268 default: 2269 return -ENOENT; 2270 } 2271 } 2272 2273 static int demux_c15_set(u64 id, void __user *uaddr) 2274 { 2275 u32 val, newval; 2276 u32 __user *uval = uaddr; 2277 2278 /* Fail if we have unknown bits set. */ 2279 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2280 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2281 return -ENOENT; 2282 2283 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2284 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2285 if (KVM_REG_SIZE(id) != 4) 2286 return -ENOENT; 2287 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2288 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2289 if (!is_valid_cache(val)) 2290 return -ENOENT; 2291 2292 if (get_user(newval, uval)) 2293 return -EFAULT; 2294 2295 /* This is also invariant: you can't change it. */ 2296 if (newval != get_ccsidr(val)) 2297 return -EINVAL; 2298 return 0; 2299 default: 2300 return -ENOENT; 2301 } 2302 } 2303 2304 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2305 { 2306 const struct sys_reg_desc *r; 2307 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2308 2309 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2310 return demux_c15_get(reg->id, uaddr); 2311 2312 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2313 return -ENOENT; 2314 2315 r = index_to_sys_reg_desc(vcpu, reg->id); 2316 if (!r) 2317 return get_invariant_sys_reg(reg->id, uaddr); 2318 2319 if (r->get_user) 2320 return (r->get_user)(vcpu, r, reg, uaddr); 2321 2322 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); 2323 } 2324 2325 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2326 { 2327 const struct sys_reg_desc *r; 2328 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2329 2330 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2331 return demux_c15_set(reg->id, uaddr); 2332 2333 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2334 return -ENOENT; 2335 2336 r = index_to_sys_reg_desc(vcpu, reg->id); 2337 if (!r) 2338 return set_invariant_sys_reg(reg->id, uaddr); 2339 2340 if (r->set_user) 2341 return (r->set_user)(vcpu, r, reg, uaddr); 2342 2343 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); 2344 } 2345 2346 static unsigned int num_demux_regs(void) 2347 { 2348 unsigned int i, count = 0; 2349 2350 for (i = 0; i < CSSELR_MAX; i++) 2351 if (is_valid_cache(i)) 2352 count++; 2353 2354 return count; 2355 } 2356 2357 static int write_demux_regids(u64 __user *uindices) 2358 { 2359 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 2360 unsigned int i; 2361 2362 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 2363 for (i = 0; i < CSSELR_MAX; i++) { 2364 if (!is_valid_cache(i)) 2365 continue; 2366 if (put_user(val | i, uindices)) 2367 return -EFAULT; 2368 uindices++; 2369 } 2370 return 0; 2371 } 2372 2373 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 2374 { 2375 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 2376 KVM_REG_ARM64_SYSREG | 2377 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 2378 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 2379 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 2380 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 2381 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 2382 } 2383 2384 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 2385 { 2386 if (!*uind) 2387 return true; 2388 2389 if (put_user(sys_reg_to_index(reg), *uind)) 2390 return false; 2391 2392 (*uind)++; 2393 return true; 2394 } 2395 2396 static int walk_one_sys_reg(const struct sys_reg_desc *rd, 2397 u64 __user **uind, 2398 unsigned int *total) 2399 { 2400 /* 2401 * Ignore registers we trap but don't save, 2402 * and for which no custom user accessor is provided. 2403 */ 2404 if (!(rd->reg || rd->get_user)) 2405 return 0; 2406 2407 if (!copy_reg_to_user(rd, uind)) 2408 return -EFAULT; 2409 2410 (*total)++; 2411 return 0; 2412 } 2413 2414 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 2415 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 2416 { 2417 const struct sys_reg_desc *i1, *i2, *end1, *end2; 2418 unsigned int total = 0; 2419 size_t num; 2420 int err; 2421 2422 /* We check for duplicates here, to allow arch-specific overrides. */ 2423 i1 = get_target_table(vcpu->arch.target, true, &num); 2424 end1 = i1 + num; 2425 i2 = sys_reg_descs; 2426 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 2427 2428 BUG_ON(i1 == end1 || i2 == end2); 2429 2430 /* Walk carefully, as both tables may refer to the same register. */ 2431 while (i1 || i2) { 2432 int cmp = cmp_sys_reg(i1, i2); 2433 /* target-specific overrides generic entry. */ 2434 if (cmp <= 0) 2435 err = walk_one_sys_reg(i1, &uind, &total); 2436 else 2437 err = walk_one_sys_reg(i2, &uind, &total); 2438 2439 if (err) 2440 return err; 2441 2442 if (cmp <= 0 && ++i1 == end1) 2443 i1 = NULL; 2444 if (cmp >= 0 && ++i2 == end2) 2445 i2 = NULL; 2446 } 2447 return total; 2448 } 2449 2450 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 2451 { 2452 return ARRAY_SIZE(invariant_sys_regs) 2453 + num_demux_regs() 2454 + walk_sys_regs(vcpu, (u64 __user *)NULL); 2455 } 2456 2457 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 2458 { 2459 unsigned int i; 2460 int err; 2461 2462 /* Then give them all the invariant registers' indices. */ 2463 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 2464 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 2465 return -EFAULT; 2466 uindices++; 2467 } 2468 2469 err = walk_sys_regs(vcpu, uindices); 2470 if (err < 0) 2471 return err; 2472 uindices += err; 2473 2474 return write_demux_regids(uindices); 2475 } 2476 2477 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n) 2478 { 2479 unsigned int i; 2480 2481 for (i = 1; i < n; i++) { 2482 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2483 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); 2484 return 1; 2485 } 2486 } 2487 2488 return 0; 2489 } 2490 2491 void kvm_sys_reg_table_init(void) 2492 { 2493 unsigned int i; 2494 struct sys_reg_desc clidr; 2495 2496 /* Make sure tables are unique and in order. */ 2497 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs))); 2498 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs))); 2499 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs))); 2500 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs))); 2501 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs))); 2502 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs))); 2503 2504 /* We abuse the reset function to overwrite the table itself. */ 2505 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 2506 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 2507 2508 /* 2509 * CLIDR format is awkward, so clean it up. See ARM B4.1.20: 2510 * 2511 * If software reads the Cache Type fields from Ctype1 2512 * upwards, once it has seen a value of 0b000, no caches 2513 * exist at further-out levels of the hierarchy. So, for 2514 * example, if Ctype3 is the first Cache Type field with a 2515 * value of 0b000, the values of Ctype4 to Ctype7 must be 2516 * ignored. 2517 */ 2518 get_clidr_el1(NULL, &clidr); /* Ugly... */ 2519 cache_levels = clidr.val; 2520 for (i = 0; i < 7; i++) 2521 if (((cache_levels >> (i*3)) & 7) == 0) 2522 break; 2523 /* Clear all higher bits. */ 2524 cache_levels &= (1 << (i*3))-1; 2525 } 2526 2527 /** 2528 * kvm_reset_sys_regs - sets system registers to reset value 2529 * @vcpu: The VCPU pointer 2530 * 2531 * This function finds the right table above and sets the registers on the 2532 * virtual CPU struct to their architecturally defined reset values. 2533 */ 2534 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2535 { 2536 size_t num; 2537 const struct sys_reg_desc *table; 2538 2539 /* Catch someone adding a register without putting in reset entry. */ 2540 memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs)); 2541 2542 /* Generic chip reset first (so target could override). */ 2543 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2544 2545 table = get_target_table(vcpu->arch.target, true, &num); 2546 reset_sys_reg_descs(vcpu, table, num); 2547 2548 for (num = 1; num < NR_SYS_REGS; num++) 2549 if (__vcpu_sys_reg(vcpu, num) == 0x4242424242424242) 2550 panic("Didn't reset __vcpu_sys_reg(%zi)", num); 2551 } 2552