1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/kvm_host.h> 15 #include <linux/mm.h> 16 #include <linux/printk.h> 17 #include <linux/uaccess.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/cputype.h> 21 #include <asm/debug-monitors.h> 22 #include <asm/esr.h> 23 #include <asm/kvm_arm.h> 24 #include <asm/kvm_emulate.h> 25 #include <asm/kvm_hyp.h> 26 #include <asm/kvm_mmu.h> 27 #include <asm/perf_event.h> 28 #include <asm/sysreg.h> 29 30 #include <trace/events/kvm.h> 31 32 #include "sys_regs.h" 33 34 #include "trace.h" 35 36 /* 37 * All of this file is extremely similar to the ARM coproc.c, but the 38 * types are different. My gut feeling is that it should be pretty 39 * easy to merge, but that would be an ABI breakage -- again. VFP 40 * would also need to be abstracted. 41 * 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); 48 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); 49 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 50 51 static bool read_from_write_only(struct kvm_vcpu *vcpu, 52 struct sys_reg_params *params, 53 const struct sys_reg_desc *r) 54 { 55 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 56 print_sys_reg_instr(params); 57 kvm_inject_undefined(vcpu); 58 return false; 59 } 60 61 static bool write_to_read_only(struct kvm_vcpu *vcpu, 62 struct sys_reg_params *params, 63 const struct sys_reg_desc *r) 64 { 65 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 66 print_sys_reg_instr(params); 67 kvm_inject_undefined(vcpu); 68 return false; 69 } 70 71 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 72 { 73 u64 val = 0x8badf00d8badf00d; 74 75 if (vcpu->arch.sysregs_loaded_on_cpu && 76 __vcpu_read_sys_reg_from_cpu(reg, &val)) 77 return val; 78 79 return __vcpu_sys_reg(vcpu, reg); 80 } 81 82 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 83 { 84 if (vcpu->arch.sysregs_loaded_on_cpu && 85 __vcpu_write_sys_reg_to_cpu(val, reg)) 86 return; 87 88 __vcpu_sys_reg(vcpu, reg) = val; 89 } 90 91 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ 92 static u32 cache_levels; 93 94 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 95 #define CSSELR_MAX 14 96 97 /* Which cache CCSIDR represents depends on CSSELR value. */ 98 static u32 get_ccsidr(u32 csselr) 99 { 100 u32 ccsidr; 101 102 /* Make sure noone else changes CSSELR during this! */ 103 local_irq_disable(); 104 write_sysreg(csselr, csselr_el1); 105 isb(); 106 ccsidr = read_sysreg(ccsidr_el1); 107 local_irq_enable(); 108 109 return ccsidr; 110 } 111 112 /* 113 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 114 */ 115 static bool access_dcsw(struct kvm_vcpu *vcpu, 116 struct sys_reg_params *p, 117 const struct sys_reg_desc *r) 118 { 119 if (!p->is_write) 120 return read_from_write_only(vcpu, p, r); 121 122 /* 123 * Only track S/W ops if we don't have FWB. It still indicates 124 * that the guest is a bit broken (S/W operations should only 125 * be done by firmware, knowing that there is only a single 126 * CPU left in the system, and certainly not from non-secure 127 * software). 128 */ 129 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 130 kvm_set_way_flush(vcpu); 131 132 return true; 133 } 134 135 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 136 { 137 switch (r->aarch32_map) { 138 case AA32_LO: 139 *mask = GENMASK_ULL(31, 0); 140 *shift = 0; 141 break; 142 case AA32_HI: 143 *mask = GENMASK_ULL(63, 32); 144 *shift = 32; 145 break; 146 default: 147 *mask = GENMASK_ULL(63, 0); 148 *shift = 0; 149 break; 150 } 151 } 152 153 /* 154 * Generic accessor for VM registers. Only called as long as HCR_TVM 155 * is set. If the guest enables the MMU, we stop trapping the VM 156 * sys_regs and leave it in complete control of the caches. 157 */ 158 static bool access_vm_reg(struct kvm_vcpu *vcpu, 159 struct sys_reg_params *p, 160 const struct sys_reg_desc *r) 161 { 162 bool was_enabled = vcpu_has_cache_enabled(vcpu); 163 u64 val, mask, shift; 164 165 BUG_ON(!p->is_write); 166 167 get_access_mask(r, &mask, &shift); 168 169 if (~mask) { 170 val = vcpu_read_sys_reg(vcpu, r->reg); 171 val &= ~mask; 172 } else { 173 val = 0; 174 } 175 176 val |= (p->regval & (mask >> shift)) << shift; 177 vcpu_write_sys_reg(vcpu, val, r->reg); 178 179 kvm_toggle_cache(vcpu, was_enabled); 180 return true; 181 } 182 183 static bool access_actlr(struct kvm_vcpu *vcpu, 184 struct sys_reg_params *p, 185 const struct sys_reg_desc *r) 186 { 187 u64 mask, shift; 188 189 if (p->is_write) 190 return ignore_write(vcpu, p); 191 192 get_access_mask(r, &mask, &shift); 193 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 194 195 return true; 196 } 197 198 /* 199 * Trap handler for the GICv3 SGI generation system register. 200 * Forward the request to the VGIC emulation. 201 * The cp15_64 code makes sure this automatically works 202 * for both AArch64 and AArch32 accesses. 203 */ 204 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 205 struct sys_reg_params *p, 206 const struct sys_reg_desc *r) 207 { 208 bool g1; 209 210 if (!p->is_write) 211 return read_from_write_only(vcpu, p, r); 212 213 /* 214 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 215 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 216 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 217 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 218 * group. 219 */ 220 if (p->Op0 == 0) { /* AArch32 */ 221 switch (p->Op1) { 222 default: /* Keep GCC quiet */ 223 case 0: /* ICC_SGI1R */ 224 g1 = true; 225 break; 226 case 1: /* ICC_ASGI1R */ 227 case 2: /* ICC_SGI0R */ 228 g1 = false; 229 break; 230 } 231 } else { /* AArch64 */ 232 switch (p->Op2) { 233 default: /* Keep GCC quiet */ 234 case 5: /* ICC_SGI1R_EL1 */ 235 g1 = true; 236 break; 237 case 6: /* ICC_ASGI1R_EL1 */ 238 case 7: /* ICC_SGI0R_EL1 */ 239 g1 = false; 240 break; 241 } 242 } 243 244 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 245 246 return true; 247 } 248 249 static bool access_gic_sre(struct kvm_vcpu *vcpu, 250 struct sys_reg_params *p, 251 const struct sys_reg_desc *r) 252 { 253 if (p->is_write) 254 return ignore_write(vcpu, p); 255 256 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 257 return true; 258 } 259 260 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 261 struct sys_reg_params *p, 262 const struct sys_reg_desc *r) 263 { 264 if (p->is_write) 265 return ignore_write(vcpu, p); 266 else 267 return read_zero(vcpu, p); 268 } 269 270 /* 271 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 272 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 273 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 274 * treat it separately. 275 */ 276 static bool trap_loregion(struct kvm_vcpu *vcpu, 277 struct sys_reg_params *p, 278 const struct sys_reg_desc *r) 279 { 280 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 281 u32 sr = reg_to_encoding(r); 282 283 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { 284 kvm_inject_undefined(vcpu); 285 return false; 286 } 287 288 if (p->is_write && sr == SYS_LORID_EL1) 289 return write_to_read_only(vcpu, p, r); 290 291 return trap_raz_wi(vcpu, p, r); 292 } 293 294 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 295 struct sys_reg_params *p, 296 const struct sys_reg_desc *r) 297 { 298 u64 oslsr; 299 300 if (!p->is_write) 301 return read_from_write_only(vcpu, p, r); 302 303 /* Forward the OSLK bit to OSLSR */ 304 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK; 305 if (p->regval & SYS_OSLAR_OSLK) 306 oslsr |= SYS_OSLSR_OSLK; 307 308 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; 309 return true; 310 } 311 312 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 313 struct sys_reg_params *p, 314 const struct sys_reg_desc *r) 315 { 316 if (p->is_write) 317 return write_to_read_only(vcpu, p, r); 318 319 p->regval = __vcpu_sys_reg(vcpu, r->reg); 320 return true; 321 } 322 323 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 324 const struct kvm_one_reg *reg, void __user *uaddr) 325 { 326 u64 id = sys_reg_to_index(rd); 327 u64 val; 328 int err; 329 330 err = reg_from_user(&val, uaddr, id); 331 if (err) 332 return err; 333 334 /* 335 * The only modifiable bit is the OSLK bit. Refuse the write if 336 * userspace attempts to change any other bit in the register. 337 */ 338 if ((val ^ rd->val) & ~SYS_OSLSR_OSLK) 339 return -EINVAL; 340 341 __vcpu_sys_reg(vcpu, rd->reg) = val; 342 return 0; 343 } 344 345 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 346 struct sys_reg_params *p, 347 const struct sys_reg_desc *r) 348 { 349 if (p->is_write) { 350 return ignore_write(vcpu, p); 351 } else { 352 p->regval = read_sysreg(dbgauthstatus_el1); 353 return true; 354 } 355 } 356 357 /* 358 * We want to avoid world-switching all the DBG registers all the 359 * time: 360 * 361 * - If we've touched any debug register, it is likely that we're 362 * going to touch more of them. It then makes sense to disable the 363 * traps and start doing the save/restore dance 364 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 365 * then mandatory to save/restore the registers, as the guest 366 * depends on them. 367 * 368 * For this, we use a DIRTY bit, indicating the guest has modified the 369 * debug registers, used as follow: 370 * 371 * On guest entry: 372 * - If the dirty bit is set (because we're coming back from trapping), 373 * disable the traps, save host registers, restore guest registers. 374 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 375 * set the dirty bit, disable the traps, save host registers, 376 * restore guest registers. 377 * - Otherwise, enable the traps 378 * 379 * On guest exit: 380 * - If the dirty bit is set, save guest registers, restore host 381 * registers and clear the dirty bit. This ensure that the host can 382 * now use the debug registers. 383 */ 384 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 385 struct sys_reg_params *p, 386 const struct sys_reg_desc *r) 387 { 388 if (p->is_write) { 389 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 390 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 391 } else { 392 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 393 } 394 395 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 396 397 return true; 398 } 399 400 /* 401 * reg_to_dbg/dbg_to_reg 402 * 403 * A 32 bit write to a debug register leave top bits alone 404 * A 32 bit read from a debug register only returns the bottom bits 405 * 406 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the 407 * hyp.S code switches between host and guest values in future. 408 */ 409 static void reg_to_dbg(struct kvm_vcpu *vcpu, 410 struct sys_reg_params *p, 411 const struct sys_reg_desc *rd, 412 u64 *dbg_reg) 413 { 414 u64 mask, shift, val; 415 416 get_access_mask(rd, &mask, &shift); 417 418 val = *dbg_reg; 419 val &= ~mask; 420 val |= (p->regval & (mask >> shift)) << shift; 421 *dbg_reg = val; 422 423 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 424 } 425 426 static void dbg_to_reg(struct kvm_vcpu *vcpu, 427 struct sys_reg_params *p, 428 const struct sys_reg_desc *rd, 429 u64 *dbg_reg) 430 { 431 u64 mask, shift; 432 433 get_access_mask(rd, &mask, &shift); 434 p->regval = (*dbg_reg & mask) >> shift; 435 } 436 437 static bool trap_bvr(struct kvm_vcpu *vcpu, 438 struct sys_reg_params *p, 439 const struct sys_reg_desc *rd) 440 { 441 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 442 443 if (p->is_write) 444 reg_to_dbg(vcpu, p, rd, dbg_reg); 445 else 446 dbg_to_reg(vcpu, p, rd, dbg_reg); 447 448 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 449 450 return true; 451 } 452 453 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 454 const struct kvm_one_reg *reg, void __user *uaddr) 455 { 456 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 457 458 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 459 return -EFAULT; 460 return 0; 461 } 462 463 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 464 const struct kvm_one_reg *reg, void __user *uaddr) 465 { 466 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; 467 468 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 469 return -EFAULT; 470 return 0; 471 } 472 473 static void reset_bvr(struct kvm_vcpu *vcpu, 474 const struct sys_reg_desc *rd) 475 { 476 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; 477 } 478 479 static bool trap_bcr(struct kvm_vcpu *vcpu, 480 struct sys_reg_params *p, 481 const struct sys_reg_desc *rd) 482 { 483 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 484 485 if (p->is_write) 486 reg_to_dbg(vcpu, p, rd, dbg_reg); 487 else 488 dbg_to_reg(vcpu, p, rd, dbg_reg); 489 490 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 491 492 return true; 493 } 494 495 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 496 const struct kvm_one_reg *reg, void __user *uaddr) 497 { 498 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 499 500 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 501 return -EFAULT; 502 503 return 0; 504 } 505 506 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 507 const struct kvm_one_reg *reg, void __user *uaddr) 508 { 509 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; 510 511 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 512 return -EFAULT; 513 return 0; 514 } 515 516 static void reset_bcr(struct kvm_vcpu *vcpu, 517 const struct sys_reg_desc *rd) 518 { 519 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; 520 } 521 522 static bool trap_wvr(struct kvm_vcpu *vcpu, 523 struct sys_reg_params *p, 524 const struct sys_reg_desc *rd) 525 { 526 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 527 528 if (p->is_write) 529 reg_to_dbg(vcpu, p, rd, dbg_reg); 530 else 531 dbg_to_reg(vcpu, p, rd, dbg_reg); 532 533 trace_trap_reg(__func__, rd->CRm, p->is_write, 534 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); 535 536 return true; 537 } 538 539 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 540 const struct kvm_one_reg *reg, void __user *uaddr) 541 { 542 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 543 544 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 545 return -EFAULT; 546 return 0; 547 } 548 549 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 550 const struct kvm_one_reg *reg, void __user *uaddr) 551 { 552 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; 553 554 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 555 return -EFAULT; 556 return 0; 557 } 558 559 static void reset_wvr(struct kvm_vcpu *vcpu, 560 const struct sys_reg_desc *rd) 561 { 562 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; 563 } 564 565 static bool trap_wcr(struct kvm_vcpu *vcpu, 566 struct sys_reg_params *p, 567 const struct sys_reg_desc *rd) 568 { 569 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 570 571 if (p->is_write) 572 reg_to_dbg(vcpu, p, rd, dbg_reg); 573 else 574 dbg_to_reg(vcpu, p, rd, dbg_reg); 575 576 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); 577 578 return true; 579 } 580 581 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 582 const struct kvm_one_reg *reg, void __user *uaddr) 583 { 584 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 585 586 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 587 return -EFAULT; 588 return 0; 589 } 590 591 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 592 const struct kvm_one_reg *reg, void __user *uaddr) 593 { 594 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; 595 596 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 597 return -EFAULT; 598 return 0; 599 } 600 601 static void reset_wcr(struct kvm_vcpu *vcpu, 602 const struct sys_reg_desc *rd) 603 { 604 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; 605 } 606 607 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 608 { 609 u64 amair = read_sysreg(amair_el1); 610 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 611 } 612 613 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 614 { 615 u64 actlr = read_sysreg(actlr_el1); 616 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 617 } 618 619 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 620 { 621 u64 mpidr; 622 623 /* 624 * Map the vcpu_id into the first three affinity level fields of 625 * the MPIDR. We limit the number of VCPUs in level 0 due to a 626 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 627 * of the GICv3 to be able to address each CPU directly when 628 * sending IPIs. 629 */ 630 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 631 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 632 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 633 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 634 } 635 636 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 637 const struct sys_reg_desc *r) 638 { 639 if (kvm_vcpu_has_pmu(vcpu)) 640 return 0; 641 642 return REG_HIDDEN; 643 } 644 645 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 646 { 647 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); 648 649 /* No PMU available, any PMU reg may UNDEF... */ 650 if (!kvm_arm_support_pmu_v3()) 651 return; 652 653 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; 654 n &= ARMV8_PMU_PMCR_N_MASK; 655 if (n) 656 mask |= GENMASK(n - 1, 0); 657 658 reset_unknown(vcpu, r); 659 __vcpu_sys_reg(vcpu, r->reg) &= mask; 660 } 661 662 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 663 { 664 reset_unknown(vcpu, r); 665 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 666 } 667 668 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 669 { 670 reset_unknown(vcpu, r); 671 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK; 672 } 673 674 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 675 { 676 reset_unknown(vcpu, r); 677 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; 678 } 679 680 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 681 { 682 u64 pmcr, val; 683 684 /* No PMU available, PMCR_EL0 may UNDEF... */ 685 if (!kvm_arm_support_pmu_v3()) 686 return; 687 688 pmcr = read_sysreg(pmcr_el0); 689 /* 690 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN 691 * except PMCR.E resetting to zero. 692 */ 693 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) 694 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); 695 if (!system_supports_32bit_el0()) 696 val |= ARMV8_PMU_PMCR_LC; 697 __vcpu_sys_reg(vcpu, r->reg) = val; 698 } 699 700 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 701 { 702 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 703 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 704 705 if (!enabled) 706 kvm_inject_undefined(vcpu); 707 708 return !enabled; 709 } 710 711 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 712 { 713 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 714 } 715 716 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 717 { 718 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 719 } 720 721 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 722 { 723 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 724 } 725 726 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 727 { 728 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 729 } 730 731 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 732 const struct sys_reg_desc *r) 733 { 734 u64 val; 735 736 if (pmu_access_el0_disabled(vcpu)) 737 return false; 738 739 if (p->is_write) { 740 /* Only update writeable bits of PMCR */ 741 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 742 val &= ~ARMV8_PMU_PMCR_MASK; 743 val |= p->regval & ARMV8_PMU_PMCR_MASK; 744 if (!system_supports_32bit_el0()) 745 val |= ARMV8_PMU_PMCR_LC; 746 __vcpu_sys_reg(vcpu, PMCR_EL0) = val; 747 kvm_pmu_handle_pmcr(vcpu, val); 748 kvm_vcpu_pmu_restore_guest(vcpu); 749 } else { 750 /* PMCR.P & PMCR.C are RAZ */ 751 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 752 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 753 p->regval = val; 754 } 755 756 return true; 757 } 758 759 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 760 const struct sys_reg_desc *r) 761 { 762 if (pmu_access_event_counter_el0_disabled(vcpu)) 763 return false; 764 765 if (p->is_write) 766 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 767 else 768 /* return PMSELR.SEL field */ 769 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 770 & ARMV8_PMU_COUNTER_MASK; 771 772 return true; 773 } 774 775 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 776 const struct sys_reg_desc *r) 777 { 778 u64 pmceid, mask, shift; 779 780 BUG_ON(p->is_write); 781 782 if (pmu_access_el0_disabled(vcpu)) 783 return false; 784 785 get_access_mask(r, &mask, &shift); 786 787 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 788 pmceid &= mask; 789 pmceid >>= shift; 790 791 p->regval = pmceid; 792 793 return true; 794 } 795 796 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 797 { 798 u64 pmcr, val; 799 800 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 801 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 802 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 803 kvm_inject_undefined(vcpu); 804 return false; 805 } 806 807 return true; 808 } 809 810 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 811 struct sys_reg_params *p, 812 const struct sys_reg_desc *r) 813 { 814 u64 idx = ~0UL; 815 816 if (r->CRn == 9 && r->CRm == 13) { 817 if (r->Op2 == 2) { 818 /* PMXEVCNTR_EL0 */ 819 if (pmu_access_event_counter_el0_disabled(vcpu)) 820 return false; 821 822 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 823 & ARMV8_PMU_COUNTER_MASK; 824 } else if (r->Op2 == 0) { 825 /* PMCCNTR_EL0 */ 826 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 827 return false; 828 829 idx = ARMV8_PMU_CYCLE_IDX; 830 } 831 } else if (r->CRn == 0 && r->CRm == 9) { 832 /* PMCCNTR */ 833 if (pmu_access_event_counter_el0_disabled(vcpu)) 834 return false; 835 836 idx = ARMV8_PMU_CYCLE_IDX; 837 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 838 /* PMEVCNTRn_EL0 */ 839 if (pmu_access_event_counter_el0_disabled(vcpu)) 840 return false; 841 842 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 843 } 844 845 /* Catch any decoding mistake */ 846 WARN_ON(idx == ~0UL); 847 848 if (!pmu_counter_idx_valid(vcpu, idx)) 849 return false; 850 851 if (p->is_write) { 852 if (pmu_access_el0_disabled(vcpu)) 853 return false; 854 855 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 856 } else { 857 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 858 } 859 860 return true; 861 } 862 863 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 864 const struct sys_reg_desc *r) 865 { 866 u64 idx, reg; 867 868 if (pmu_access_el0_disabled(vcpu)) 869 return false; 870 871 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 872 /* PMXEVTYPER_EL0 */ 873 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 874 reg = PMEVTYPER0_EL0 + idx; 875 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 876 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 877 if (idx == ARMV8_PMU_CYCLE_IDX) 878 reg = PMCCFILTR_EL0; 879 else 880 /* PMEVTYPERn_EL0 */ 881 reg = PMEVTYPER0_EL0 + idx; 882 } else { 883 BUG(); 884 } 885 886 if (!pmu_counter_idx_valid(vcpu, idx)) 887 return false; 888 889 if (p->is_write) { 890 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 891 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 892 kvm_vcpu_pmu_restore_guest(vcpu); 893 } else { 894 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 895 } 896 897 return true; 898 } 899 900 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 901 const struct sys_reg_desc *r) 902 { 903 u64 val, mask; 904 905 if (pmu_access_el0_disabled(vcpu)) 906 return false; 907 908 mask = kvm_pmu_valid_counter_mask(vcpu); 909 if (p->is_write) { 910 val = p->regval & mask; 911 if (r->Op2 & 0x1) { 912 /* accessing PMCNTENSET_EL0 */ 913 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 914 kvm_pmu_enable_counter_mask(vcpu, val); 915 kvm_vcpu_pmu_restore_guest(vcpu); 916 } else { 917 /* accessing PMCNTENCLR_EL0 */ 918 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 919 kvm_pmu_disable_counter_mask(vcpu, val); 920 } 921 } else { 922 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 923 } 924 925 return true; 926 } 927 928 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 929 const struct sys_reg_desc *r) 930 { 931 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 932 933 if (check_pmu_access_disabled(vcpu, 0)) 934 return false; 935 936 if (p->is_write) { 937 u64 val = p->regval & mask; 938 939 if (r->Op2 & 0x1) 940 /* accessing PMINTENSET_EL1 */ 941 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 942 else 943 /* accessing PMINTENCLR_EL1 */ 944 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 945 } else { 946 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 947 } 948 949 return true; 950 } 951 952 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 953 const struct sys_reg_desc *r) 954 { 955 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 956 957 if (pmu_access_el0_disabled(vcpu)) 958 return false; 959 960 if (p->is_write) { 961 if (r->CRm & 0x2) 962 /* accessing PMOVSSET_EL0 */ 963 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 964 else 965 /* accessing PMOVSCLR_EL0 */ 966 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 967 } else { 968 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 969 } 970 971 return true; 972 } 973 974 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 975 const struct sys_reg_desc *r) 976 { 977 u64 mask; 978 979 if (!p->is_write) 980 return read_from_write_only(vcpu, p, r); 981 982 if (pmu_write_swinc_el0_disabled(vcpu)) 983 return false; 984 985 mask = kvm_pmu_valid_counter_mask(vcpu); 986 kvm_pmu_software_increment(vcpu, p->regval & mask); 987 return true; 988 } 989 990 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 991 const struct sys_reg_desc *r) 992 { 993 if (p->is_write) { 994 if (!vcpu_mode_priv(vcpu)) { 995 kvm_inject_undefined(vcpu); 996 return false; 997 } 998 999 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1000 p->regval & ARMV8_PMU_USERENR_MASK; 1001 } else { 1002 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1003 & ARMV8_PMU_USERENR_MASK; 1004 } 1005 1006 return true; 1007 } 1008 1009 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1010 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1011 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1012 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1013 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1014 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1015 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1016 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1017 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1018 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1019 1020 #define PMU_SYS_REG(r) \ 1021 SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility 1022 1023 /* Macro to expand the PMEVCNTRn_EL0 register */ 1024 #define PMU_PMEVCNTR_EL0(n) \ 1025 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \ 1026 .reset = reset_pmevcntr, \ 1027 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1028 1029 /* Macro to expand the PMEVTYPERn_EL0 register */ 1030 #define PMU_PMEVTYPER_EL0(n) \ 1031 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \ 1032 .reset = reset_pmevtyper, \ 1033 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1034 1035 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1036 const struct sys_reg_desc *r) 1037 { 1038 kvm_inject_undefined(vcpu); 1039 1040 return false; 1041 } 1042 1043 /* Macro to expand the AMU counter and type registers*/ 1044 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1045 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1046 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1047 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1048 1049 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1050 const struct sys_reg_desc *rd) 1051 { 1052 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1053 } 1054 1055 /* 1056 * If we land here on a PtrAuth access, that is because we didn't 1057 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1058 * way this happens is when the guest does not have PtrAuth support 1059 * enabled. 1060 */ 1061 #define __PTRAUTH_KEY(k) \ 1062 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1063 .visibility = ptrauth_visibility} 1064 1065 #define PTRAUTH_KEY(k) \ 1066 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1067 __PTRAUTH_KEY(k ## KEYHI_EL1) 1068 1069 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1070 struct sys_reg_params *p, 1071 const struct sys_reg_desc *r) 1072 { 1073 enum kvm_arch_timers tmr; 1074 enum kvm_arch_timer_regs treg; 1075 u64 reg = reg_to_encoding(r); 1076 1077 switch (reg) { 1078 case SYS_CNTP_TVAL_EL0: 1079 case SYS_AARCH32_CNTP_TVAL: 1080 tmr = TIMER_PTIMER; 1081 treg = TIMER_REG_TVAL; 1082 break; 1083 case SYS_CNTP_CTL_EL0: 1084 case SYS_AARCH32_CNTP_CTL: 1085 tmr = TIMER_PTIMER; 1086 treg = TIMER_REG_CTL; 1087 break; 1088 case SYS_CNTP_CVAL_EL0: 1089 case SYS_AARCH32_CNTP_CVAL: 1090 tmr = TIMER_PTIMER; 1091 treg = TIMER_REG_CVAL; 1092 break; 1093 default: 1094 BUG(); 1095 } 1096 1097 if (p->is_write) 1098 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1099 else 1100 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1101 1102 return true; 1103 } 1104 1105 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1106 static u64 read_id_reg(const struct kvm_vcpu *vcpu, 1107 struct sys_reg_desc const *r, bool raz) 1108 { 1109 u32 id = reg_to_encoding(r); 1110 u64 val; 1111 1112 if (raz) 1113 return 0; 1114 1115 val = read_sanitised_ftr_reg(id); 1116 1117 switch (id) { 1118 case SYS_ID_AA64PFR0_EL1: 1119 if (!vcpu_has_sve(vcpu)) 1120 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE); 1121 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU); 1122 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2); 1123 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); 1124 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3); 1125 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); 1126 if (kvm_vgic_global_state.type == VGIC_V3) { 1127 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC); 1128 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1); 1129 } 1130 break; 1131 case SYS_ID_AA64PFR1_EL1: 1132 if (!kvm_has_mte(vcpu->kvm)) 1133 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); 1134 break; 1135 case SYS_ID_AA64ISAR1_EL1: 1136 if (!vcpu_has_ptrauth(vcpu)) 1137 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | 1138 ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | 1139 ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | 1140 ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI)); 1141 break; 1142 case SYS_ID_AA64ISAR2_EL1: 1143 if (!vcpu_has_ptrauth(vcpu)) 1144 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | 1145 ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); 1146 break; 1147 case SYS_ID_AA64DFR0_EL1: 1148 /* Limit debug to ARMv8.0 */ 1149 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); 1150 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6); 1151 /* Limit guests to PMUv3 for ARMv8.4 */ 1152 val = cpuid_feature_cap_perfmon_field(val, 1153 ID_AA64DFR0_PMUVER_SHIFT, 1154 kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); 1155 /* Hide SPE from guests */ 1156 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); 1157 break; 1158 case SYS_ID_DFR0_EL1: 1159 /* Limit guests to PMUv3 for ARMv8.4 */ 1160 val = cpuid_feature_cap_perfmon_field(val, 1161 ID_DFR0_PERFMON_SHIFT, 1162 kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); 1163 break; 1164 } 1165 1166 return val; 1167 } 1168 1169 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1170 const struct sys_reg_desc *r) 1171 { 1172 u32 id = reg_to_encoding(r); 1173 1174 switch (id) { 1175 case SYS_ID_AA64ZFR0_EL1: 1176 if (!vcpu_has_sve(vcpu)) 1177 return REG_RAZ; 1178 break; 1179 } 1180 1181 return 0; 1182 } 1183 1184 /* cpufeature ID register access trap handlers */ 1185 1186 static bool __access_id_reg(struct kvm_vcpu *vcpu, 1187 struct sys_reg_params *p, 1188 const struct sys_reg_desc *r, 1189 bool raz) 1190 { 1191 if (p->is_write) 1192 return write_to_read_only(vcpu, p, r); 1193 1194 p->regval = read_id_reg(vcpu, r, raz); 1195 return true; 1196 } 1197 1198 static bool access_id_reg(struct kvm_vcpu *vcpu, 1199 struct sys_reg_params *p, 1200 const struct sys_reg_desc *r) 1201 { 1202 bool raz = sysreg_visible_as_raz(vcpu, r); 1203 1204 return __access_id_reg(vcpu, p, r, raz); 1205 } 1206 1207 static bool access_raz_id_reg(struct kvm_vcpu *vcpu, 1208 struct sys_reg_params *p, 1209 const struct sys_reg_desc *r) 1210 { 1211 return __access_id_reg(vcpu, p, r, true); 1212 } 1213 1214 /* Visibility overrides for SVE-specific control registers */ 1215 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1216 const struct sys_reg_desc *rd) 1217 { 1218 if (vcpu_has_sve(vcpu)) 1219 return 0; 1220 1221 return REG_HIDDEN; 1222 } 1223 1224 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1225 const struct sys_reg_desc *rd, 1226 const struct kvm_one_reg *reg, void __user *uaddr) 1227 { 1228 const u64 id = sys_reg_to_index(rd); 1229 u8 csv2, csv3; 1230 int err; 1231 u64 val; 1232 1233 err = reg_from_user(&val, uaddr, id); 1234 if (err) 1235 return err; 1236 1237 /* 1238 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as 1239 * it doesn't promise more than what is actually provided (the 1240 * guest could otherwise be covered in ectoplasmic residue). 1241 */ 1242 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT); 1243 if (csv2 > 1 || 1244 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) 1245 return -EINVAL; 1246 1247 /* Same thing for CSV3 */ 1248 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT); 1249 if (csv3 > 1 || 1250 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) 1251 return -EINVAL; 1252 1253 /* We can only differ with CSV[23], and anything else is an error */ 1254 val ^= read_id_reg(vcpu, rd, false); 1255 val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) | 1256 (0xFUL << ID_AA64PFR0_CSV3_SHIFT)); 1257 if (val) 1258 return -EINVAL; 1259 1260 vcpu->kvm->arch.pfr0_csv2 = csv2; 1261 vcpu->kvm->arch.pfr0_csv3 = csv3 ; 1262 1263 return 0; 1264 } 1265 1266 /* 1267 * cpufeature ID register user accessors 1268 * 1269 * For now, these registers are immutable for userspace, so no values 1270 * are stored, and for set_id_reg() we don't allow the effective value 1271 * to be changed. 1272 */ 1273 static int __get_id_reg(const struct kvm_vcpu *vcpu, 1274 const struct sys_reg_desc *rd, void __user *uaddr, 1275 bool raz) 1276 { 1277 const u64 id = sys_reg_to_index(rd); 1278 const u64 val = read_id_reg(vcpu, rd, raz); 1279 1280 return reg_to_user(uaddr, &val, id); 1281 } 1282 1283 static int __set_id_reg(const struct kvm_vcpu *vcpu, 1284 const struct sys_reg_desc *rd, void __user *uaddr, 1285 bool raz) 1286 { 1287 const u64 id = sys_reg_to_index(rd); 1288 int err; 1289 u64 val; 1290 1291 err = reg_from_user(&val, uaddr, id); 1292 if (err) 1293 return err; 1294 1295 /* This is what we mean by invariant: you can't change it. */ 1296 if (val != read_id_reg(vcpu, rd, raz)) 1297 return -EINVAL; 1298 1299 return 0; 1300 } 1301 1302 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1303 const struct kvm_one_reg *reg, void __user *uaddr) 1304 { 1305 bool raz = sysreg_visible_as_raz(vcpu, rd); 1306 1307 return __get_id_reg(vcpu, rd, uaddr, raz); 1308 } 1309 1310 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1311 const struct kvm_one_reg *reg, void __user *uaddr) 1312 { 1313 bool raz = sysreg_visible_as_raz(vcpu, rd); 1314 1315 return __set_id_reg(vcpu, rd, uaddr, raz); 1316 } 1317 1318 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1319 const struct kvm_one_reg *reg, void __user *uaddr) 1320 { 1321 return __set_id_reg(vcpu, rd, uaddr, true); 1322 } 1323 1324 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1325 const struct kvm_one_reg *reg, void __user *uaddr) 1326 { 1327 const u64 id = sys_reg_to_index(rd); 1328 const u64 val = 0; 1329 1330 return reg_to_user(uaddr, &val, id); 1331 } 1332 1333 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1334 const struct kvm_one_reg *reg, void __user *uaddr) 1335 { 1336 int err; 1337 u64 val; 1338 1339 /* Perform the access even if we are going to ignore the value */ 1340 err = reg_from_user(&val, uaddr, sys_reg_to_index(rd)); 1341 if (err) 1342 return err; 1343 1344 return 0; 1345 } 1346 1347 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1348 const struct sys_reg_desc *r) 1349 { 1350 if (p->is_write) 1351 return write_to_read_only(vcpu, p, r); 1352 1353 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1354 return true; 1355 } 1356 1357 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1358 const struct sys_reg_desc *r) 1359 { 1360 if (p->is_write) 1361 return write_to_read_only(vcpu, p, r); 1362 1363 p->regval = read_sysreg(clidr_el1); 1364 return true; 1365 } 1366 1367 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1368 const struct sys_reg_desc *r) 1369 { 1370 int reg = r->reg; 1371 1372 if (p->is_write) 1373 vcpu_write_sys_reg(vcpu, p->regval, reg); 1374 else 1375 p->regval = vcpu_read_sys_reg(vcpu, reg); 1376 return true; 1377 } 1378 1379 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1380 const struct sys_reg_desc *r) 1381 { 1382 u32 csselr; 1383 1384 if (p->is_write) 1385 return write_to_read_only(vcpu, p, r); 1386 1387 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1388 p->regval = get_ccsidr(csselr); 1389 1390 /* 1391 * Guests should not be doing cache operations by set/way at all, and 1392 * for this reason, we trap them and attempt to infer the intent, so 1393 * that we can flush the entire guest's address space at the appropriate 1394 * time. 1395 * To prevent this trapping from causing performance problems, let's 1396 * expose the geometry of all data and unified caches (which are 1397 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. 1398 * [If guests should attempt to infer aliasing properties from the 1399 * geometry (which is not permitted by the architecture), they would 1400 * only do so for virtually indexed caches.] 1401 */ 1402 if (!(csselr & 1)) // data or unified cache 1403 p->regval &= ~GENMASK(27, 3); 1404 return true; 1405 } 1406 1407 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 1408 const struct sys_reg_desc *rd) 1409 { 1410 if (kvm_has_mte(vcpu->kvm)) 1411 return 0; 1412 1413 return REG_HIDDEN; 1414 } 1415 1416 #define MTE_REG(name) { \ 1417 SYS_DESC(SYS_##name), \ 1418 .access = undef_access, \ 1419 .reset = reset_unknown, \ 1420 .reg = name, \ 1421 .visibility = mte_visibility, \ 1422 } 1423 1424 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1425 #define ID_SANITISED(name) { \ 1426 SYS_DESC(SYS_##name), \ 1427 .access = access_id_reg, \ 1428 .get_user = get_id_reg, \ 1429 .set_user = set_id_reg, \ 1430 .visibility = id_visibility, \ 1431 } 1432 1433 /* 1434 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1435 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1436 * (1 <= crm < 8, 0 <= Op2 < 8). 1437 */ 1438 #define ID_UNALLOCATED(crm, op2) { \ 1439 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1440 .access = access_raz_id_reg, \ 1441 .get_user = get_raz_reg, \ 1442 .set_user = set_raz_id_reg, \ 1443 } 1444 1445 /* 1446 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1447 * For now, these are exposed just like unallocated ID regs: they appear 1448 * RAZ for the guest. 1449 */ 1450 #define ID_HIDDEN(name) { \ 1451 SYS_DESC(SYS_##name), \ 1452 .access = access_raz_id_reg, \ 1453 .get_user = get_raz_reg, \ 1454 .set_user = set_raz_id_reg, \ 1455 } 1456 1457 /* 1458 * Architected system registers. 1459 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1460 * 1461 * Debug handling: We do trap most, if not all debug related system 1462 * registers. The implementation is good enough to ensure that a guest 1463 * can use these with minimal performance degradation. The drawback is 1464 * that we don't implement any of the external debug architecture. 1465 * This should be revisited if we ever encounter a more demanding 1466 * guest... 1467 */ 1468 static const struct sys_reg_desc sys_reg_descs[] = { 1469 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1470 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1471 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1472 1473 DBG_BCR_BVR_WCR_WVR_EL1(0), 1474 DBG_BCR_BVR_WCR_WVR_EL1(1), 1475 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1476 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1477 DBG_BCR_BVR_WCR_WVR_EL1(2), 1478 DBG_BCR_BVR_WCR_WVR_EL1(3), 1479 DBG_BCR_BVR_WCR_WVR_EL1(4), 1480 DBG_BCR_BVR_WCR_WVR_EL1(5), 1481 DBG_BCR_BVR_WCR_WVR_EL1(6), 1482 DBG_BCR_BVR_WCR_WVR_EL1(7), 1483 DBG_BCR_BVR_WCR_WVR_EL1(8), 1484 DBG_BCR_BVR_WCR_WVR_EL1(9), 1485 DBG_BCR_BVR_WCR_WVR_EL1(10), 1486 DBG_BCR_BVR_WCR_WVR_EL1(11), 1487 DBG_BCR_BVR_WCR_WVR_EL1(12), 1488 DBG_BCR_BVR_WCR_WVR_EL1(13), 1489 DBG_BCR_BVR_WCR_WVR_EL1(14), 1490 DBG_BCR_BVR_WCR_WVR_EL1(15), 1491 1492 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1493 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 1494 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 1495 SYS_OSLSR_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 1496 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1497 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1498 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1499 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1500 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1501 1502 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1503 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1504 // DBGDTR[TR]X_EL0 share the same encoding 1505 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1506 1507 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1508 1509 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1510 1511 /* 1512 * ID regs: all ID_SANITISED() entries here must have corresponding 1513 * entries in arm64_ftr_regs[]. 1514 */ 1515 1516 /* AArch64 mappings of the AArch32 ID registers */ 1517 /* CRm=1 */ 1518 ID_SANITISED(ID_PFR0_EL1), 1519 ID_SANITISED(ID_PFR1_EL1), 1520 ID_SANITISED(ID_DFR0_EL1), 1521 ID_HIDDEN(ID_AFR0_EL1), 1522 ID_SANITISED(ID_MMFR0_EL1), 1523 ID_SANITISED(ID_MMFR1_EL1), 1524 ID_SANITISED(ID_MMFR2_EL1), 1525 ID_SANITISED(ID_MMFR3_EL1), 1526 1527 /* CRm=2 */ 1528 ID_SANITISED(ID_ISAR0_EL1), 1529 ID_SANITISED(ID_ISAR1_EL1), 1530 ID_SANITISED(ID_ISAR2_EL1), 1531 ID_SANITISED(ID_ISAR3_EL1), 1532 ID_SANITISED(ID_ISAR4_EL1), 1533 ID_SANITISED(ID_ISAR5_EL1), 1534 ID_SANITISED(ID_MMFR4_EL1), 1535 ID_SANITISED(ID_ISAR6_EL1), 1536 1537 /* CRm=3 */ 1538 ID_SANITISED(MVFR0_EL1), 1539 ID_SANITISED(MVFR1_EL1), 1540 ID_SANITISED(MVFR2_EL1), 1541 ID_UNALLOCATED(3,3), 1542 ID_SANITISED(ID_PFR2_EL1), 1543 ID_HIDDEN(ID_DFR1_EL1), 1544 ID_SANITISED(ID_MMFR5_EL1), 1545 ID_UNALLOCATED(3,7), 1546 1547 /* AArch64 ID registers */ 1548 /* CRm=4 */ 1549 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, 1550 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, 1551 ID_SANITISED(ID_AA64PFR1_EL1), 1552 ID_UNALLOCATED(4,2), 1553 ID_UNALLOCATED(4,3), 1554 ID_SANITISED(ID_AA64ZFR0_EL1), 1555 ID_UNALLOCATED(4,5), 1556 ID_UNALLOCATED(4,6), 1557 ID_UNALLOCATED(4,7), 1558 1559 /* CRm=5 */ 1560 ID_SANITISED(ID_AA64DFR0_EL1), 1561 ID_SANITISED(ID_AA64DFR1_EL1), 1562 ID_UNALLOCATED(5,2), 1563 ID_UNALLOCATED(5,3), 1564 ID_HIDDEN(ID_AA64AFR0_EL1), 1565 ID_HIDDEN(ID_AA64AFR1_EL1), 1566 ID_UNALLOCATED(5,6), 1567 ID_UNALLOCATED(5,7), 1568 1569 /* CRm=6 */ 1570 ID_SANITISED(ID_AA64ISAR0_EL1), 1571 ID_SANITISED(ID_AA64ISAR1_EL1), 1572 ID_SANITISED(ID_AA64ISAR2_EL1), 1573 ID_UNALLOCATED(6,3), 1574 ID_UNALLOCATED(6,4), 1575 ID_UNALLOCATED(6,5), 1576 ID_UNALLOCATED(6,6), 1577 ID_UNALLOCATED(6,7), 1578 1579 /* CRm=7 */ 1580 ID_SANITISED(ID_AA64MMFR0_EL1), 1581 ID_SANITISED(ID_AA64MMFR1_EL1), 1582 ID_SANITISED(ID_AA64MMFR2_EL1), 1583 ID_UNALLOCATED(7,3), 1584 ID_UNALLOCATED(7,4), 1585 ID_UNALLOCATED(7,5), 1586 ID_UNALLOCATED(7,6), 1587 ID_UNALLOCATED(7,7), 1588 1589 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1590 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1591 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1592 1593 MTE_REG(RGSR_EL1), 1594 MTE_REG(GCR_EL1), 1595 1596 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1597 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 1598 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1599 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1600 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1601 1602 PTRAUTH_KEY(APIA), 1603 PTRAUTH_KEY(APIB), 1604 PTRAUTH_KEY(APDA), 1605 PTRAUTH_KEY(APDB), 1606 PTRAUTH_KEY(APGA), 1607 1608 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1609 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1610 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1611 1612 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1613 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1614 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1615 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1616 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1617 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1618 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1619 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1620 1621 MTE_REG(TFSR_EL1), 1622 MTE_REG(TFSRE0_EL1), 1623 1624 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1625 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1626 1627 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 1628 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 1629 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 1630 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 1631 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 1632 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 1633 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 1634 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 1635 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 1636 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 1637 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 1638 /* PMBIDR_EL1 is not trapped */ 1639 1640 { PMU_SYS_REG(SYS_PMINTENSET_EL1), 1641 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1642 { PMU_SYS_REG(SYS_PMINTENCLR_EL1), 1643 .access = access_pminten, .reg = PMINTENSET_EL1 }, 1644 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 1645 1646 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1647 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1648 1649 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1650 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1651 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1652 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1653 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1654 1655 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, 1656 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1657 1658 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1659 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1660 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1661 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1662 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1663 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1664 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1665 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1666 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1667 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1668 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1669 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1670 1671 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1672 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1673 1674 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 1675 1676 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1677 1678 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1679 { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, 1680 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1681 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1682 1683 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, 1684 .reset = reset_pmcr, .reg = PMCR_EL0 }, 1685 { PMU_SYS_REG(SYS_PMCNTENSET_EL0), 1686 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1687 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0), 1688 .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, 1689 { PMU_SYS_REG(SYS_PMOVSCLR_EL0), 1690 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1691 /* 1692 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 1693 * previously (and pointlessly) advertised in the past... 1694 */ 1695 { PMU_SYS_REG(SYS_PMSWINC_EL0), 1696 .get_user = get_raz_reg, .set_user = set_wi_reg, 1697 .access = access_pmswinc, .reset = NULL }, 1698 { PMU_SYS_REG(SYS_PMSELR_EL0), 1699 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 1700 { PMU_SYS_REG(SYS_PMCEID0_EL0), 1701 .access = access_pmceid, .reset = NULL }, 1702 { PMU_SYS_REG(SYS_PMCEID1_EL0), 1703 .access = access_pmceid, .reset = NULL }, 1704 { PMU_SYS_REG(SYS_PMCCNTR_EL0), 1705 .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 }, 1706 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0), 1707 .access = access_pmu_evtyper, .reset = NULL }, 1708 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0), 1709 .access = access_pmu_evcntr, .reset = NULL }, 1710 /* 1711 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1712 * in 32bit mode. Here we choose to reset it as zero for consistency. 1713 */ 1714 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr, 1715 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 1716 { PMU_SYS_REG(SYS_PMOVSSET_EL0), 1717 .access = access_pmovs, .reg = PMOVSSET_EL0 }, 1718 1719 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 1720 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 1721 1722 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 1723 1724 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 1725 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 1726 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 1727 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 1728 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 1729 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 1730 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 1731 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 1732 AMU_AMEVCNTR0_EL0(0), 1733 AMU_AMEVCNTR0_EL0(1), 1734 AMU_AMEVCNTR0_EL0(2), 1735 AMU_AMEVCNTR0_EL0(3), 1736 AMU_AMEVCNTR0_EL0(4), 1737 AMU_AMEVCNTR0_EL0(5), 1738 AMU_AMEVCNTR0_EL0(6), 1739 AMU_AMEVCNTR0_EL0(7), 1740 AMU_AMEVCNTR0_EL0(8), 1741 AMU_AMEVCNTR0_EL0(9), 1742 AMU_AMEVCNTR0_EL0(10), 1743 AMU_AMEVCNTR0_EL0(11), 1744 AMU_AMEVCNTR0_EL0(12), 1745 AMU_AMEVCNTR0_EL0(13), 1746 AMU_AMEVCNTR0_EL0(14), 1747 AMU_AMEVCNTR0_EL0(15), 1748 AMU_AMEVTYPER0_EL0(0), 1749 AMU_AMEVTYPER0_EL0(1), 1750 AMU_AMEVTYPER0_EL0(2), 1751 AMU_AMEVTYPER0_EL0(3), 1752 AMU_AMEVTYPER0_EL0(4), 1753 AMU_AMEVTYPER0_EL0(5), 1754 AMU_AMEVTYPER0_EL0(6), 1755 AMU_AMEVTYPER0_EL0(7), 1756 AMU_AMEVTYPER0_EL0(8), 1757 AMU_AMEVTYPER0_EL0(9), 1758 AMU_AMEVTYPER0_EL0(10), 1759 AMU_AMEVTYPER0_EL0(11), 1760 AMU_AMEVTYPER0_EL0(12), 1761 AMU_AMEVTYPER0_EL0(13), 1762 AMU_AMEVTYPER0_EL0(14), 1763 AMU_AMEVTYPER0_EL0(15), 1764 AMU_AMEVCNTR1_EL0(0), 1765 AMU_AMEVCNTR1_EL0(1), 1766 AMU_AMEVCNTR1_EL0(2), 1767 AMU_AMEVCNTR1_EL0(3), 1768 AMU_AMEVCNTR1_EL0(4), 1769 AMU_AMEVCNTR1_EL0(5), 1770 AMU_AMEVCNTR1_EL0(6), 1771 AMU_AMEVCNTR1_EL0(7), 1772 AMU_AMEVCNTR1_EL0(8), 1773 AMU_AMEVCNTR1_EL0(9), 1774 AMU_AMEVCNTR1_EL0(10), 1775 AMU_AMEVCNTR1_EL0(11), 1776 AMU_AMEVCNTR1_EL0(12), 1777 AMU_AMEVCNTR1_EL0(13), 1778 AMU_AMEVCNTR1_EL0(14), 1779 AMU_AMEVCNTR1_EL0(15), 1780 AMU_AMEVTYPER1_EL0(0), 1781 AMU_AMEVTYPER1_EL0(1), 1782 AMU_AMEVTYPER1_EL0(2), 1783 AMU_AMEVTYPER1_EL0(3), 1784 AMU_AMEVTYPER1_EL0(4), 1785 AMU_AMEVTYPER1_EL0(5), 1786 AMU_AMEVTYPER1_EL0(6), 1787 AMU_AMEVTYPER1_EL0(7), 1788 AMU_AMEVTYPER1_EL0(8), 1789 AMU_AMEVTYPER1_EL0(9), 1790 AMU_AMEVTYPER1_EL0(10), 1791 AMU_AMEVTYPER1_EL0(11), 1792 AMU_AMEVTYPER1_EL0(12), 1793 AMU_AMEVTYPER1_EL0(13), 1794 AMU_AMEVTYPER1_EL0(14), 1795 AMU_AMEVTYPER1_EL0(15), 1796 1797 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 1798 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 1799 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 1800 1801 /* PMEVCNTRn_EL0 */ 1802 PMU_PMEVCNTR_EL0(0), 1803 PMU_PMEVCNTR_EL0(1), 1804 PMU_PMEVCNTR_EL0(2), 1805 PMU_PMEVCNTR_EL0(3), 1806 PMU_PMEVCNTR_EL0(4), 1807 PMU_PMEVCNTR_EL0(5), 1808 PMU_PMEVCNTR_EL0(6), 1809 PMU_PMEVCNTR_EL0(7), 1810 PMU_PMEVCNTR_EL0(8), 1811 PMU_PMEVCNTR_EL0(9), 1812 PMU_PMEVCNTR_EL0(10), 1813 PMU_PMEVCNTR_EL0(11), 1814 PMU_PMEVCNTR_EL0(12), 1815 PMU_PMEVCNTR_EL0(13), 1816 PMU_PMEVCNTR_EL0(14), 1817 PMU_PMEVCNTR_EL0(15), 1818 PMU_PMEVCNTR_EL0(16), 1819 PMU_PMEVCNTR_EL0(17), 1820 PMU_PMEVCNTR_EL0(18), 1821 PMU_PMEVCNTR_EL0(19), 1822 PMU_PMEVCNTR_EL0(20), 1823 PMU_PMEVCNTR_EL0(21), 1824 PMU_PMEVCNTR_EL0(22), 1825 PMU_PMEVCNTR_EL0(23), 1826 PMU_PMEVCNTR_EL0(24), 1827 PMU_PMEVCNTR_EL0(25), 1828 PMU_PMEVCNTR_EL0(26), 1829 PMU_PMEVCNTR_EL0(27), 1830 PMU_PMEVCNTR_EL0(28), 1831 PMU_PMEVCNTR_EL0(29), 1832 PMU_PMEVCNTR_EL0(30), 1833 /* PMEVTYPERn_EL0 */ 1834 PMU_PMEVTYPER_EL0(0), 1835 PMU_PMEVTYPER_EL0(1), 1836 PMU_PMEVTYPER_EL0(2), 1837 PMU_PMEVTYPER_EL0(3), 1838 PMU_PMEVTYPER_EL0(4), 1839 PMU_PMEVTYPER_EL0(5), 1840 PMU_PMEVTYPER_EL0(6), 1841 PMU_PMEVTYPER_EL0(7), 1842 PMU_PMEVTYPER_EL0(8), 1843 PMU_PMEVTYPER_EL0(9), 1844 PMU_PMEVTYPER_EL0(10), 1845 PMU_PMEVTYPER_EL0(11), 1846 PMU_PMEVTYPER_EL0(12), 1847 PMU_PMEVTYPER_EL0(13), 1848 PMU_PMEVTYPER_EL0(14), 1849 PMU_PMEVTYPER_EL0(15), 1850 PMU_PMEVTYPER_EL0(16), 1851 PMU_PMEVTYPER_EL0(17), 1852 PMU_PMEVTYPER_EL0(18), 1853 PMU_PMEVTYPER_EL0(19), 1854 PMU_PMEVTYPER_EL0(20), 1855 PMU_PMEVTYPER_EL0(21), 1856 PMU_PMEVTYPER_EL0(22), 1857 PMU_PMEVTYPER_EL0(23), 1858 PMU_PMEVTYPER_EL0(24), 1859 PMU_PMEVTYPER_EL0(25), 1860 PMU_PMEVTYPER_EL0(26), 1861 PMU_PMEVTYPER_EL0(27), 1862 PMU_PMEVTYPER_EL0(28), 1863 PMU_PMEVTYPER_EL0(29), 1864 PMU_PMEVTYPER_EL0(30), 1865 /* 1866 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 1867 * in 32bit mode. Here we choose to reset it as zero for consistency. 1868 */ 1869 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper, 1870 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 1871 1872 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 1873 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 1874 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 1875 }; 1876 1877 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 1878 struct sys_reg_params *p, 1879 const struct sys_reg_desc *r) 1880 { 1881 if (p->is_write) { 1882 return ignore_write(vcpu, p); 1883 } else { 1884 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1885 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1886 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); 1887 1888 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | 1889 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | 1890 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) 1891 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); 1892 return true; 1893 } 1894 } 1895 1896 /* 1897 * AArch32 debug register mappings 1898 * 1899 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 1900 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 1901 * 1902 * None of the other registers share their location, so treat them as 1903 * if they were 64bit. 1904 */ 1905 #define DBG_BCR_BVR_WCR_WVR(n) \ 1906 /* DBGBVRn */ \ 1907 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 1908 /* DBGBCRn */ \ 1909 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 1910 /* DBGWVRn */ \ 1911 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 1912 /* DBGWCRn */ \ 1913 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 1914 1915 #define DBGBXVR(n) \ 1916 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 1917 1918 /* 1919 * Trapped cp14 registers. We generally ignore most of the external 1920 * debug, on the principle that they don't really make sense to a 1921 * guest. Revisit this one day, would this principle change. 1922 */ 1923 static const struct sys_reg_desc cp14_regs[] = { 1924 /* DBGDIDR */ 1925 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 1926 /* DBGDTRRXext */ 1927 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 1928 1929 DBG_BCR_BVR_WCR_WVR(0), 1930 /* DBGDSCRint */ 1931 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 1932 DBG_BCR_BVR_WCR_WVR(1), 1933 /* DBGDCCINT */ 1934 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 1935 /* DBGDSCRext */ 1936 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 1937 DBG_BCR_BVR_WCR_WVR(2), 1938 /* DBGDTR[RT]Xint */ 1939 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 1940 /* DBGDTR[RT]Xext */ 1941 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 1942 DBG_BCR_BVR_WCR_WVR(3), 1943 DBG_BCR_BVR_WCR_WVR(4), 1944 DBG_BCR_BVR_WCR_WVR(5), 1945 /* DBGWFAR */ 1946 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 1947 /* DBGOSECCR */ 1948 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 1949 DBG_BCR_BVR_WCR_WVR(6), 1950 /* DBGVCR */ 1951 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 1952 DBG_BCR_BVR_WCR_WVR(7), 1953 DBG_BCR_BVR_WCR_WVR(8), 1954 DBG_BCR_BVR_WCR_WVR(9), 1955 DBG_BCR_BVR_WCR_WVR(10), 1956 DBG_BCR_BVR_WCR_WVR(11), 1957 DBG_BCR_BVR_WCR_WVR(12), 1958 DBG_BCR_BVR_WCR_WVR(13), 1959 DBG_BCR_BVR_WCR_WVR(14), 1960 DBG_BCR_BVR_WCR_WVR(15), 1961 1962 /* DBGDRAR (32bit) */ 1963 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 1964 1965 DBGBXVR(0), 1966 /* DBGOSLAR */ 1967 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 1968 DBGBXVR(1), 1969 /* DBGOSLSR */ 1970 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 1971 DBGBXVR(2), 1972 DBGBXVR(3), 1973 /* DBGOSDLR */ 1974 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 1975 DBGBXVR(4), 1976 /* DBGPRCR */ 1977 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 1978 DBGBXVR(5), 1979 DBGBXVR(6), 1980 DBGBXVR(7), 1981 DBGBXVR(8), 1982 DBGBXVR(9), 1983 DBGBXVR(10), 1984 DBGBXVR(11), 1985 DBGBXVR(12), 1986 DBGBXVR(13), 1987 DBGBXVR(14), 1988 DBGBXVR(15), 1989 1990 /* DBGDSAR (32bit) */ 1991 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 1992 1993 /* DBGDEVID2 */ 1994 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 1995 /* DBGDEVID1 */ 1996 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 1997 /* DBGDEVID */ 1998 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 1999 /* DBGCLAIMSET */ 2000 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 2001 /* DBGCLAIMCLR */ 2002 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 2003 /* DBGAUTHSTATUS */ 2004 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 2005 }; 2006 2007 /* Trapped cp14 64bit registers */ 2008 static const struct sys_reg_desc cp14_64_regs[] = { 2009 /* DBGDRAR (64bit) */ 2010 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 2011 2012 /* DBGDSAR (64bit) */ 2013 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 2014 }; 2015 2016 /* Macro to expand the PMEVCNTRn register */ 2017 #define PMU_PMEVCNTR(n) \ 2018 /* PMEVCNTRn */ \ 2019 { Op1(0), CRn(0b1110), \ 2020 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 2021 access_pmu_evcntr } 2022 2023 /* Macro to expand the PMEVTYPERn register */ 2024 #define PMU_PMEVTYPER(n) \ 2025 /* PMEVTYPERn */ \ 2026 { Op1(0), CRn(0b1110), \ 2027 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 2028 access_pmu_evtyper } 2029 2030 /* 2031 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 2032 * depending on the way they are accessed (as a 32bit or a 64bit 2033 * register). 2034 */ 2035 static const struct sys_reg_desc cp15_regs[] = { 2036 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 2037 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 2038 /* ACTLR */ 2039 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 2040 /* ACTLR2 */ 2041 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 2042 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2043 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 2044 /* TTBCR */ 2045 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 2046 /* TTBCR2 */ 2047 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 2048 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 2049 /* DFSR */ 2050 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 2051 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 2052 /* ADFSR */ 2053 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 2054 /* AIFSR */ 2055 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 2056 /* DFAR */ 2057 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 2058 /* IFAR */ 2059 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 2060 2061 /* 2062 * DC{C,I,CI}SW operations: 2063 */ 2064 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 2065 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 2066 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 2067 2068 /* PMU */ 2069 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, 2070 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, 2071 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, 2072 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, 2073 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, 2074 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, 2075 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, 2076 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, 2077 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, 2078 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, 2079 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, 2080 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, 2081 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, 2082 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, 2083 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, 2084 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid }, 2085 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid }, 2086 /* PMMIR */ 2087 { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi }, 2088 2089 /* PRRR/MAIR0 */ 2090 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 2091 /* NMRR/MAIR1 */ 2092 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 2093 /* AMAIR0 */ 2094 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 2095 /* AMAIR1 */ 2096 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 2097 2098 /* ICC_SRE */ 2099 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 2100 2101 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 2102 2103 /* Arch Tmers */ 2104 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 2105 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 2106 2107 /* PMEVCNTRn */ 2108 PMU_PMEVCNTR(0), 2109 PMU_PMEVCNTR(1), 2110 PMU_PMEVCNTR(2), 2111 PMU_PMEVCNTR(3), 2112 PMU_PMEVCNTR(4), 2113 PMU_PMEVCNTR(5), 2114 PMU_PMEVCNTR(6), 2115 PMU_PMEVCNTR(7), 2116 PMU_PMEVCNTR(8), 2117 PMU_PMEVCNTR(9), 2118 PMU_PMEVCNTR(10), 2119 PMU_PMEVCNTR(11), 2120 PMU_PMEVCNTR(12), 2121 PMU_PMEVCNTR(13), 2122 PMU_PMEVCNTR(14), 2123 PMU_PMEVCNTR(15), 2124 PMU_PMEVCNTR(16), 2125 PMU_PMEVCNTR(17), 2126 PMU_PMEVCNTR(18), 2127 PMU_PMEVCNTR(19), 2128 PMU_PMEVCNTR(20), 2129 PMU_PMEVCNTR(21), 2130 PMU_PMEVCNTR(22), 2131 PMU_PMEVCNTR(23), 2132 PMU_PMEVCNTR(24), 2133 PMU_PMEVCNTR(25), 2134 PMU_PMEVCNTR(26), 2135 PMU_PMEVCNTR(27), 2136 PMU_PMEVCNTR(28), 2137 PMU_PMEVCNTR(29), 2138 PMU_PMEVCNTR(30), 2139 /* PMEVTYPERn */ 2140 PMU_PMEVTYPER(0), 2141 PMU_PMEVTYPER(1), 2142 PMU_PMEVTYPER(2), 2143 PMU_PMEVTYPER(3), 2144 PMU_PMEVTYPER(4), 2145 PMU_PMEVTYPER(5), 2146 PMU_PMEVTYPER(6), 2147 PMU_PMEVTYPER(7), 2148 PMU_PMEVTYPER(8), 2149 PMU_PMEVTYPER(9), 2150 PMU_PMEVTYPER(10), 2151 PMU_PMEVTYPER(11), 2152 PMU_PMEVTYPER(12), 2153 PMU_PMEVTYPER(13), 2154 PMU_PMEVTYPER(14), 2155 PMU_PMEVTYPER(15), 2156 PMU_PMEVTYPER(16), 2157 PMU_PMEVTYPER(17), 2158 PMU_PMEVTYPER(18), 2159 PMU_PMEVTYPER(19), 2160 PMU_PMEVTYPER(20), 2161 PMU_PMEVTYPER(21), 2162 PMU_PMEVTYPER(22), 2163 PMU_PMEVTYPER(23), 2164 PMU_PMEVTYPER(24), 2165 PMU_PMEVTYPER(25), 2166 PMU_PMEVTYPER(26), 2167 PMU_PMEVTYPER(27), 2168 PMU_PMEVTYPER(28), 2169 PMU_PMEVTYPER(29), 2170 PMU_PMEVTYPER(30), 2171 /* PMCCFILTR */ 2172 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, 2173 2174 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2175 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2176 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 2177 }; 2178 2179 static const struct sys_reg_desc cp15_64_regs[] = { 2180 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2181 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, 2182 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2183 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 2184 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2185 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2186 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2187 }; 2188 2189 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2190 bool is_32) 2191 { 2192 unsigned int i; 2193 2194 for (i = 0; i < n; i++) { 2195 if (!is_32 && table[i].reg && !table[i].reset) { 2196 kvm_err("sys_reg table %p entry %d has lacks reset\n", 2197 table, i); 2198 return 1; 2199 } 2200 2201 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2202 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); 2203 return 1; 2204 } 2205 } 2206 2207 return 0; 2208 } 2209 2210 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2211 { 2212 kvm_inject_undefined(vcpu); 2213 return 1; 2214 } 2215 2216 static void perform_access(struct kvm_vcpu *vcpu, 2217 struct sys_reg_params *params, 2218 const struct sys_reg_desc *r) 2219 { 2220 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2221 2222 /* Check for regs disabled by runtime config */ 2223 if (sysreg_hidden(vcpu, r)) { 2224 kvm_inject_undefined(vcpu); 2225 return; 2226 } 2227 2228 /* 2229 * Not having an accessor means that we have configured a trap 2230 * that we don't know how to handle. This certainly qualifies 2231 * as a gross bug that should be fixed right away. 2232 */ 2233 BUG_ON(!r->access); 2234 2235 /* Skip instruction if instructed so */ 2236 if (likely(r->access(vcpu, params, r))) 2237 kvm_incr_pc(vcpu); 2238 } 2239 2240 /* 2241 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2242 * call the corresponding trap handler. 2243 * 2244 * @params: pointer to the descriptor of the access 2245 * @table: array of trap descriptors 2246 * @num: size of the trap descriptor array 2247 * 2248 * Return 0 if the access has been handled, and -1 if not. 2249 */ 2250 static int emulate_cp(struct kvm_vcpu *vcpu, 2251 struct sys_reg_params *params, 2252 const struct sys_reg_desc *table, 2253 size_t num) 2254 { 2255 const struct sys_reg_desc *r; 2256 2257 if (!table) 2258 return -1; /* Not handled */ 2259 2260 r = find_reg(params, table, num); 2261 2262 if (r) { 2263 perform_access(vcpu, params, r); 2264 return 0; 2265 } 2266 2267 /* Not handled */ 2268 return -1; 2269 } 2270 2271 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2272 struct sys_reg_params *params) 2273 { 2274 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2275 int cp = -1; 2276 2277 switch (esr_ec) { 2278 case ESR_ELx_EC_CP15_32: 2279 case ESR_ELx_EC_CP15_64: 2280 cp = 15; 2281 break; 2282 case ESR_ELx_EC_CP14_MR: 2283 case ESR_ELx_EC_CP14_64: 2284 cp = 14; 2285 break; 2286 default: 2287 WARN_ON(1); 2288 } 2289 2290 print_sys_reg_msg(params, 2291 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2292 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2293 kvm_inject_undefined(vcpu); 2294 } 2295 2296 /** 2297 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2298 * @vcpu: The VCPU pointer 2299 * @run: The kvm_run struct 2300 */ 2301 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2302 const struct sys_reg_desc *global, 2303 size_t nr_global) 2304 { 2305 struct sys_reg_params params; 2306 u32 esr = kvm_vcpu_get_esr(vcpu); 2307 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2308 int Rt2 = (esr >> 10) & 0x1f; 2309 2310 params.CRm = (esr >> 1) & 0xf; 2311 params.is_write = ((esr & 1) == 0); 2312 2313 params.Op0 = 0; 2314 params.Op1 = (esr >> 16) & 0xf; 2315 params.Op2 = 0; 2316 params.CRn = 0; 2317 2318 /* 2319 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2320 * backends between AArch32 and AArch64, we get away with it. 2321 */ 2322 if (params.is_write) { 2323 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2324 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2325 } 2326 2327 /* 2328 * If the table contains a handler, handle the 2329 * potential register operation in the case of a read and return 2330 * with success. 2331 */ 2332 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2333 /* Split up the value between registers for the read side */ 2334 if (!params.is_write) { 2335 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2336 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2337 } 2338 2339 return 1; 2340 } 2341 2342 unhandled_cp_access(vcpu, ¶ms); 2343 return 1; 2344 } 2345 2346 /** 2347 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2348 * @vcpu: The VCPU pointer 2349 * @run: The kvm_run struct 2350 */ 2351 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2352 const struct sys_reg_desc *global, 2353 size_t nr_global) 2354 { 2355 struct sys_reg_params params; 2356 u32 esr = kvm_vcpu_get_esr(vcpu); 2357 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2358 2359 params.CRm = (esr >> 1) & 0xf; 2360 params.regval = vcpu_get_reg(vcpu, Rt); 2361 params.is_write = ((esr & 1) == 0); 2362 params.CRn = (esr >> 10) & 0xf; 2363 params.Op0 = 0; 2364 params.Op1 = (esr >> 14) & 0x7; 2365 params.Op2 = (esr >> 17) & 0x7; 2366 2367 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2368 if (!params.is_write) 2369 vcpu_set_reg(vcpu, Rt, params.regval); 2370 return 1; 2371 } 2372 2373 unhandled_cp_access(vcpu, ¶ms); 2374 return 1; 2375 } 2376 2377 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2378 { 2379 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2380 } 2381 2382 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2383 { 2384 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); 2385 } 2386 2387 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2388 { 2389 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2390 } 2391 2392 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2393 { 2394 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs)); 2395 } 2396 2397 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2398 { 2399 // See ARM DDI 0487E.a, section D12.3.2 2400 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2401 } 2402 2403 static int emulate_sys_reg(struct kvm_vcpu *vcpu, 2404 struct sys_reg_params *params) 2405 { 2406 const struct sys_reg_desc *r; 2407 2408 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2409 2410 if (likely(r)) { 2411 perform_access(vcpu, params, r); 2412 } else if (is_imp_def_sys_reg(params)) { 2413 kvm_inject_undefined(vcpu); 2414 } else { 2415 print_sys_reg_msg(params, 2416 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2417 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2418 kvm_inject_undefined(vcpu); 2419 } 2420 return 1; 2421 } 2422 2423 /** 2424 * kvm_reset_sys_regs - sets system registers to reset value 2425 * @vcpu: The VCPU pointer 2426 * 2427 * This function finds the right table above and sets the registers on the 2428 * virtual CPU struct to their architecturally defined reset values. 2429 */ 2430 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2431 { 2432 unsigned long i; 2433 2434 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2435 if (sys_reg_descs[i].reset) 2436 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2437 } 2438 2439 /** 2440 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2441 * @vcpu: The VCPU pointer 2442 */ 2443 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2444 { 2445 struct sys_reg_params params; 2446 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2447 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2448 int ret; 2449 2450 trace_kvm_handle_sys_reg(esr); 2451 2452 params = esr_sys64_to_params(esr); 2453 params.regval = vcpu_get_reg(vcpu, Rt); 2454 2455 ret = emulate_sys_reg(vcpu, ¶ms); 2456 2457 if (!params.is_write) 2458 vcpu_set_reg(vcpu, Rt, params.regval); 2459 return ret; 2460 } 2461 2462 /****************************************************************************** 2463 * Userspace API 2464 *****************************************************************************/ 2465 2466 static bool index_to_params(u64 id, struct sys_reg_params *params) 2467 { 2468 switch (id & KVM_REG_SIZE_MASK) { 2469 case KVM_REG_SIZE_U64: 2470 /* Any unused index bits means it's not valid. */ 2471 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2472 | KVM_REG_ARM_COPROC_MASK 2473 | KVM_REG_ARM64_SYSREG_OP0_MASK 2474 | KVM_REG_ARM64_SYSREG_OP1_MASK 2475 | KVM_REG_ARM64_SYSREG_CRN_MASK 2476 | KVM_REG_ARM64_SYSREG_CRM_MASK 2477 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2478 return false; 2479 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2480 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2481 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2482 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2483 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2484 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2485 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2486 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2487 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2488 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2489 return true; 2490 default: 2491 return false; 2492 } 2493 } 2494 2495 const struct sys_reg_desc *find_reg_by_id(u64 id, 2496 struct sys_reg_params *params, 2497 const struct sys_reg_desc table[], 2498 unsigned int num) 2499 { 2500 if (!index_to_params(id, params)) 2501 return NULL; 2502 2503 return find_reg(params, table, num); 2504 } 2505 2506 /* Decode an index value, and find the sys_reg_desc entry. */ 2507 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, 2508 u64 id) 2509 { 2510 const struct sys_reg_desc *r; 2511 struct sys_reg_params params; 2512 2513 /* We only do sys_reg for now. */ 2514 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2515 return NULL; 2516 2517 if (!index_to_params(id, ¶ms)) 2518 return NULL; 2519 2520 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2521 2522 /* Not saved in the sys_reg array and not otherwise accessible? */ 2523 if (r && !(r->reg || r->get_user)) 2524 r = NULL; 2525 2526 return r; 2527 } 2528 2529 /* 2530 * These are the invariant sys_reg registers: we let the guest see the 2531 * host versions of these, so they're part of the guest state. 2532 * 2533 * A future CPU may provide a mechanism to present different values to 2534 * the guest, or a future kvm may trap them. 2535 */ 2536 2537 #define FUNCTION_INVARIANT(reg) \ 2538 static void get_##reg(struct kvm_vcpu *v, \ 2539 const struct sys_reg_desc *r) \ 2540 { \ 2541 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 2542 } 2543 2544 FUNCTION_INVARIANT(midr_el1) 2545 FUNCTION_INVARIANT(revidr_el1) 2546 FUNCTION_INVARIANT(clidr_el1) 2547 FUNCTION_INVARIANT(aidr_el1) 2548 2549 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 2550 { 2551 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 2552 } 2553 2554 /* ->val is filled in by kvm_sys_reg_table_init() */ 2555 static struct sys_reg_desc invariant_sys_regs[] = { 2556 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 2557 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 2558 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, 2559 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 2560 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 2561 }; 2562 2563 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) 2564 { 2565 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) 2566 return -EFAULT; 2567 return 0; 2568 } 2569 2570 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) 2571 { 2572 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) 2573 return -EFAULT; 2574 return 0; 2575 } 2576 2577 static int get_invariant_sys_reg(u64 id, void __user *uaddr) 2578 { 2579 struct sys_reg_params params; 2580 const struct sys_reg_desc *r; 2581 2582 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2583 ARRAY_SIZE(invariant_sys_regs)); 2584 if (!r) 2585 return -ENOENT; 2586 2587 return reg_to_user(uaddr, &r->val, id); 2588 } 2589 2590 static int set_invariant_sys_reg(u64 id, void __user *uaddr) 2591 { 2592 struct sys_reg_params params; 2593 const struct sys_reg_desc *r; 2594 int err; 2595 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ 2596 2597 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2598 ARRAY_SIZE(invariant_sys_regs)); 2599 if (!r) 2600 return -ENOENT; 2601 2602 err = reg_from_user(&val, uaddr, id); 2603 if (err) 2604 return err; 2605 2606 /* This is what we mean by invariant: you can't change it. */ 2607 if (r->val != val) 2608 return -EINVAL; 2609 2610 return 0; 2611 } 2612 2613 static bool is_valid_cache(u32 val) 2614 { 2615 u32 level, ctype; 2616 2617 if (val >= CSSELR_MAX) 2618 return false; 2619 2620 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 2621 level = (val >> 1); 2622 ctype = (cache_levels >> (level * 3)) & 7; 2623 2624 switch (ctype) { 2625 case 0: /* No cache */ 2626 return false; 2627 case 1: /* Instruction cache only */ 2628 return (val & 1); 2629 case 2: /* Data cache only */ 2630 case 4: /* Unified cache */ 2631 return !(val & 1); 2632 case 3: /* Separate instruction and data caches */ 2633 return true; 2634 default: /* Reserved: we can't know instruction or data. */ 2635 return false; 2636 } 2637 } 2638 2639 static int demux_c15_get(u64 id, void __user *uaddr) 2640 { 2641 u32 val; 2642 u32 __user *uval = uaddr; 2643 2644 /* Fail if we have unknown bits set. */ 2645 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2646 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2647 return -ENOENT; 2648 2649 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2650 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2651 if (KVM_REG_SIZE(id) != 4) 2652 return -ENOENT; 2653 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2654 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2655 if (!is_valid_cache(val)) 2656 return -ENOENT; 2657 2658 return put_user(get_ccsidr(val), uval); 2659 default: 2660 return -ENOENT; 2661 } 2662 } 2663 2664 static int demux_c15_set(u64 id, void __user *uaddr) 2665 { 2666 u32 val, newval; 2667 u32 __user *uval = uaddr; 2668 2669 /* Fail if we have unknown bits set. */ 2670 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2671 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2672 return -ENOENT; 2673 2674 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2675 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2676 if (KVM_REG_SIZE(id) != 4) 2677 return -ENOENT; 2678 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2679 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2680 if (!is_valid_cache(val)) 2681 return -ENOENT; 2682 2683 if (get_user(newval, uval)) 2684 return -EFAULT; 2685 2686 /* This is also invariant: you can't change it. */ 2687 if (newval != get_ccsidr(val)) 2688 return -EINVAL; 2689 return 0; 2690 default: 2691 return -ENOENT; 2692 } 2693 } 2694 2695 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2696 { 2697 const struct sys_reg_desc *r; 2698 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2699 2700 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2701 return demux_c15_get(reg->id, uaddr); 2702 2703 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2704 return -ENOENT; 2705 2706 r = index_to_sys_reg_desc(vcpu, reg->id); 2707 if (!r) 2708 return get_invariant_sys_reg(reg->id, uaddr); 2709 2710 /* Check for regs disabled by runtime config */ 2711 if (sysreg_hidden(vcpu, r)) 2712 return -ENOENT; 2713 2714 if (r->get_user) 2715 return (r->get_user)(vcpu, r, reg, uaddr); 2716 2717 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); 2718 } 2719 2720 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2721 { 2722 const struct sys_reg_desc *r; 2723 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2724 2725 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2726 return demux_c15_set(reg->id, uaddr); 2727 2728 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2729 return -ENOENT; 2730 2731 r = index_to_sys_reg_desc(vcpu, reg->id); 2732 if (!r) 2733 return set_invariant_sys_reg(reg->id, uaddr); 2734 2735 /* Check for regs disabled by runtime config */ 2736 if (sysreg_hidden(vcpu, r)) 2737 return -ENOENT; 2738 2739 if (r->set_user) 2740 return (r->set_user)(vcpu, r, reg, uaddr); 2741 2742 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); 2743 } 2744 2745 static unsigned int num_demux_regs(void) 2746 { 2747 unsigned int i, count = 0; 2748 2749 for (i = 0; i < CSSELR_MAX; i++) 2750 if (is_valid_cache(i)) 2751 count++; 2752 2753 return count; 2754 } 2755 2756 static int write_demux_regids(u64 __user *uindices) 2757 { 2758 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 2759 unsigned int i; 2760 2761 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 2762 for (i = 0; i < CSSELR_MAX; i++) { 2763 if (!is_valid_cache(i)) 2764 continue; 2765 if (put_user(val | i, uindices)) 2766 return -EFAULT; 2767 uindices++; 2768 } 2769 return 0; 2770 } 2771 2772 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 2773 { 2774 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 2775 KVM_REG_ARM64_SYSREG | 2776 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 2777 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 2778 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 2779 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 2780 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 2781 } 2782 2783 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 2784 { 2785 if (!*uind) 2786 return true; 2787 2788 if (put_user(sys_reg_to_index(reg), *uind)) 2789 return false; 2790 2791 (*uind)++; 2792 return true; 2793 } 2794 2795 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 2796 const struct sys_reg_desc *rd, 2797 u64 __user **uind, 2798 unsigned int *total) 2799 { 2800 /* 2801 * Ignore registers we trap but don't save, 2802 * and for which no custom user accessor is provided. 2803 */ 2804 if (!(rd->reg || rd->get_user)) 2805 return 0; 2806 2807 if (sysreg_hidden(vcpu, rd)) 2808 return 0; 2809 2810 if (!copy_reg_to_user(rd, uind)) 2811 return -EFAULT; 2812 2813 (*total)++; 2814 return 0; 2815 } 2816 2817 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 2818 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 2819 { 2820 const struct sys_reg_desc *i2, *end2; 2821 unsigned int total = 0; 2822 int err; 2823 2824 i2 = sys_reg_descs; 2825 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 2826 2827 while (i2 != end2) { 2828 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 2829 if (err) 2830 return err; 2831 } 2832 return total; 2833 } 2834 2835 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 2836 { 2837 return ARRAY_SIZE(invariant_sys_regs) 2838 + num_demux_regs() 2839 + walk_sys_regs(vcpu, (u64 __user *)NULL); 2840 } 2841 2842 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 2843 { 2844 unsigned int i; 2845 int err; 2846 2847 /* Then give them all the invariant registers' indices. */ 2848 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 2849 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 2850 return -EFAULT; 2851 uindices++; 2852 } 2853 2854 err = walk_sys_regs(vcpu, uindices); 2855 if (err < 0) 2856 return err; 2857 uindices += err; 2858 2859 return write_demux_regids(uindices); 2860 } 2861 2862 void kvm_sys_reg_table_init(void) 2863 { 2864 unsigned int i; 2865 struct sys_reg_desc clidr; 2866 2867 /* Make sure tables are unique and in order. */ 2868 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false)); 2869 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true)); 2870 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true)); 2871 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true)); 2872 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true)); 2873 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false)); 2874 2875 /* We abuse the reset function to overwrite the table itself. */ 2876 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 2877 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 2878 2879 /* 2880 * CLIDR format is awkward, so clean it up. See ARM B4.1.20: 2881 * 2882 * If software reads the Cache Type fields from Ctype1 2883 * upwards, once it has seen a value of 0b000, no caches 2884 * exist at further-out levels of the hierarchy. So, for 2885 * example, if Ctype3 is the first Cache Type field with a 2886 * value of 0b000, the values of Ctype4 to Ctype7 must be 2887 * ignored. 2888 */ 2889 get_clidr_el1(NULL, &clidr); /* Ugly... */ 2890 cache_levels = clidr.val; 2891 for (i = 0; i < 7; i++) 2892 if (((cache_levels >> (i*3)) & 7) == 0) 2893 break; 2894 /* Clear all higher bits. */ 2895 cache_levels &= (1 << (i*3))-1; 2896 } 2897