1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/reset.c 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #include <linux/errno.h> 12 #include <linux/kernel.h> 13 #include <linux/kvm_host.h> 14 #include <linux/kvm.h> 15 #include <linux/hw_breakpoint.h> 16 #include <linux/slab.h> 17 #include <linux/string.h> 18 #include <linux/types.h> 19 20 #include <kvm/arm_arch_timer.h> 21 22 #include <asm/cpufeature.h> 23 #include <asm/cputype.h> 24 #include <asm/fpsimd.h> 25 #include <asm/ptrace.h> 26 #include <asm/kvm_arm.h> 27 #include <asm/kvm_asm.h> 28 #include <asm/kvm_emulate.h> 29 #include <asm/kvm_mmu.h> 30 #include <asm/virt.h> 31 32 /* Maximum phys_shift supported for any VM on this host */ 33 static u32 kvm_ipa_limit; 34 35 /* 36 * ARMv8 Reset Values 37 */ 38 #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ 39 PSR_F_BIT | PSR_D_BIT) 40 41 #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ 42 PSR_AA32_I_BIT | PSR_AA32_F_BIT) 43 44 unsigned int kvm_sve_max_vl; 45 46 int kvm_arm_init_sve(void) 47 { 48 if (system_supports_sve()) { 49 kvm_sve_max_vl = sve_max_virtualisable_vl; 50 51 /* 52 * The get_sve_reg()/set_sve_reg() ioctl interface will need 53 * to be extended with multiple register slice support in 54 * order to support vector lengths greater than 55 * SVE_VL_ARCH_MAX: 56 */ 57 if (WARN_ON(kvm_sve_max_vl > SVE_VL_ARCH_MAX)) 58 kvm_sve_max_vl = SVE_VL_ARCH_MAX; 59 60 /* 61 * Don't even try to make use of vector lengths that 62 * aren't available on all CPUs, for now: 63 */ 64 if (kvm_sve_max_vl < sve_max_vl) 65 pr_warn("KVM: SVE vector length for guests limited to %u bytes\n", 66 kvm_sve_max_vl); 67 } 68 69 return 0; 70 } 71 72 static int kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu) 73 { 74 if (!system_supports_sve()) 75 return -EINVAL; 76 77 /* Verify that KVM startup enforced this when SVE was detected: */ 78 if (WARN_ON(!has_vhe())) 79 return -EINVAL; 80 81 vcpu->arch.sve_max_vl = kvm_sve_max_vl; 82 83 /* 84 * Userspace can still customize the vector lengths by writing 85 * KVM_REG_ARM64_SVE_VLS. Allocation is deferred until 86 * kvm_arm_vcpu_finalize(), which freezes the configuration. 87 */ 88 vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE; 89 90 return 0; 91 } 92 93 /* 94 * Finalize vcpu's maximum SVE vector length, allocating 95 * vcpu->arch.sve_state as necessary. 96 */ 97 static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu) 98 { 99 void *buf; 100 unsigned int vl; 101 102 vl = vcpu->arch.sve_max_vl; 103 104 /* 105 * Responsibility for these properties is shared between 106 * kvm_arm_init_arch_resources(), kvm_vcpu_enable_sve() and 107 * set_sve_vls(). Double-check here just to be sure: 108 */ 109 if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl || 110 vl > SVE_VL_ARCH_MAX)) 111 return -EIO; 112 113 buf = kzalloc(SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl)), GFP_KERNEL); 114 if (!buf) 115 return -ENOMEM; 116 117 vcpu->arch.sve_state = buf; 118 vcpu->arch.flags |= KVM_ARM64_VCPU_SVE_FINALIZED; 119 return 0; 120 } 121 122 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature) 123 { 124 switch (feature) { 125 case KVM_ARM_VCPU_SVE: 126 if (!vcpu_has_sve(vcpu)) 127 return -EINVAL; 128 129 if (kvm_arm_vcpu_sve_finalized(vcpu)) 130 return -EPERM; 131 132 return kvm_vcpu_finalize_sve(vcpu); 133 } 134 135 return -EINVAL; 136 } 137 138 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu) 139 { 140 if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu)) 141 return false; 142 143 return true; 144 } 145 146 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) 147 { 148 kfree(vcpu->arch.sve_state); 149 } 150 151 static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) 152 { 153 if (vcpu_has_sve(vcpu)) 154 memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu)); 155 } 156 157 static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu) 158 { 159 /* 160 * For now make sure that both address/generic pointer authentication 161 * features are requested by the userspace together and the system 162 * supports these capabilities. 163 */ 164 if (!test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) || 165 !test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features) || 166 !system_has_full_ptr_auth()) 167 return -EINVAL; 168 169 vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_PTRAUTH; 170 return 0; 171 } 172 173 /** 174 * kvm_reset_vcpu - sets core registers and sys_regs to reset value 175 * @vcpu: The VCPU pointer 176 * 177 * This function finds the right table above and sets the registers on 178 * the virtual CPU struct to their architecturally defined reset 179 * values, except for registers whose reset is deferred until 180 * kvm_arm_vcpu_finalize(). 181 * 182 * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT 183 * ioctl or as part of handling a request issued by another VCPU in the PSCI 184 * handling code. In the first case, the VCPU will not be loaded, and in the 185 * second case the VCPU will be loaded. Because this function operates purely 186 * on the memory-backed values of system registers, we want to do a full put if 187 * we were loaded (handling a request) and load the values back at the end of 188 * the function. Otherwise we leave the state alone. In both cases, we 189 * disable preemption around the vcpu reset as we would otherwise race with 190 * preempt notifiers which also call put/load. 191 */ 192 int kvm_reset_vcpu(struct kvm_vcpu *vcpu) 193 { 194 int ret; 195 bool loaded; 196 u32 pstate; 197 198 /* Reset PMU outside of the non-preemptible section */ 199 kvm_pmu_vcpu_reset(vcpu); 200 201 preempt_disable(); 202 loaded = (vcpu->cpu != -1); 203 if (loaded) 204 kvm_arch_vcpu_put(vcpu); 205 206 if (!kvm_arm_vcpu_sve_finalized(vcpu)) { 207 if (test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) { 208 ret = kvm_vcpu_enable_sve(vcpu); 209 if (ret) 210 goto out; 211 } 212 } else { 213 kvm_vcpu_reset_sve(vcpu); 214 } 215 216 if (test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) || 217 test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features)) { 218 if (kvm_vcpu_enable_ptrauth(vcpu)) { 219 ret = -EINVAL; 220 goto out; 221 } 222 } 223 224 switch (vcpu->arch.target) { 225 default: 226 if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) { 227 if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1)) { 228 ret = -EINVAL; 229 goto out; 230 } 231 pstate = VCPU_RESET_PSTATE_SVC; 232 } else { 233 pstate = VCPU_RESET_PSTATE_EL1; 234 } 235 236 if (kvm_vcpu_has_pmu(vcpu) && !kvm_arm_support_pmu_v3()) { 237 ret = -EINVAL; 238 goto out; 239 } 240 break; 241 } 242 243 /* Reset core registers */ 244 memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu))); 245 vcpu_gp_regs(vcpu)->pstate = pstate; 246 247 /* Reset system registers */ 248 kvm_reset_sys_regs(vcpu); 249 250 /* 251 * Additional reset state handling that PSCI may have imposed on us. 252 * Must be done after all the sys_reg reset. 253 */ 254 if (vcpu->arch.reset_state.reset) { 255 unsigned long target_pc = vcpu->arch.reset_state.pc; 256 257 /* Gracefully handle Thumb2 entry point */ 258 if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) { 259 target_pc &= ~1UL; 260 vcpu_set_thumb(vcpu); 261 } 262 263 /* Propagate caller endianness */ 264 if (vcpu->arch.reset_state.be) 265 kvm_vcpu_set_be(vcpu); 266 267 *vcpu_pc(vcpu) = target_pc; 268 vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0); 269 270 vcpu->arch.reset_state.reset = false; 271 } 272 273 /* Reset timer */ 274 ret = kvm_timer_vcpu_reset(vcpu); 275 out: 276 if (loaded) 277 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 278 preempt_enable(); 279 return ret; 280 } 281 282 u32 get_kvm_ipa_limit(void) 283 { 284 return kvm_ipa_limit; 285 } 286 287 int kvm_set_ipa_limit(void) 288 { 289 unsigned int parange, tgran_2; 290 u64 mmfr0; 291 292 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 293 parange = cpuid_feature_extract_unsigned_field(mmfr0, 294 ID_AA64MMFR0_PARANGE_SHIFT); 295 296 /* 297 * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at 298 * Stage-2. If not, things will stop very quickly. 299 */ 300 switch (PAGE_SIZE) { 301 default: 302 case SZ_4K: 303 tgran_2 = ID_AA64MMFR0_TGRAN4_2_SHIFT; 304 break; 305 case SZ_16K: 306 tgran_2 = ID_AA64MMFR0_TGRAN16_2_SHIFT; 307 break; 308 case SZ_64K: 309 tgran_2 = ID_AA64MMFR0_TGRAN64_2_SHIFT; 310 break; 311 } 312 313 switch (cpuid_feature_extract_unsigned_field(mmfr0, tgran_2)) { 314 default: 315 case 1: 316 kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n"); 317 return -EINVAL; 318 case 0: 319 kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n"); 320 break; 321 case 2: 322 kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n"); 323 break; 324 } 325 326 kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange); 327 WARN(kvm_ipa_limit < KVM_PHYS_SHIFT, 328 "KVM IPA Size Limit (%d bits) is smaller than default size\n", 329 kvm_ipa_limit); 330 kvm_info("IPA Size Limit: %d bits\n", kvm_ipa_limit); 331 332 return 0; 333 } 334 335 /* 336 * Configure the VTCR_EL2 for this VM. The VTCR value is common 337 * across all the physical CPUs on the system. We use system wide 338 * sanitised values to fill in different fields, except for Hardware 339 * Management of Access Flags. HA Flag is set unconditionally on 340 * all CPUs, as it is safe to run with or without the feature and 341 * the bit is RES0 on CPUs that don't support it. 342 */ 343 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type) 344 { 345 u64 vtcr = VTCR_EL2_FLAGS, mmfr0; 346 u32 parange, phys_shift; 347 u8 lvls; 348 349 if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK) 350 return -EINVAL; 351 352 phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type); 353 if (phys_shift) { 354 if (phys_shift > kvm_ipa_limit || 355 phys_shift < 32) 356 return -EINVAL; 357 } else { 358 phys_shift = KVM_PHYS_SHIFT; 359 } 360 361 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 362 parange = cpuid_feature_extract_unsigned_field(mmfr0, 363 ID_AA64MMFR0_PARANGE_SHIFT); 364 if (parange > ID_AA64MMFR0_PARANGE_MAX) 365 parange = ID_AA64MMFR0_PARANGE_MAX; 366 vtcr |= parange << VTCR_EL2_PS_SHIFT; 367 368 vtcr |= VTCR_EL2_T0SZ(phys_shift); 369 /* 370 * Use a minimum 2 level page table to prevent splitting 371 * host PMD huge pages at stage2. 372 */ 373 lvls = stage2_pgtable_levels(phys_shift); 374 if (lvls < 2) 375 lvls = 2; 376 vtcr |= VTCR_EL2_LVLS_TO_SL0(lvls); 377 378 /* 379 * Enable the Hardware Access Flag management, unconditionally 380 * on all CPUs. The features is RES0 on CPUs without the support 381 * and must be ignored by the CPUs. 382 */ 383 vtcr |= VTCR_EL2_HA; 384 385 /* Set the vmid bits */ 386 vtcr |= (kvm_get_vmid_bits() == 16) ? 387 VTCR_EL2_VS_16BIT : 388 VTCR_EL2_VS_8BIT; 389 kvm->arch.vtcr = vtcr; 390 return 0; 391 } 392