1f4672752SMarc Zyngier /* 2f4672752SMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 3f4672752SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4f4672752SMarc Zyngier * 5f4672752SMarc Zyngier * Derived from arch/arm/kvm/reset.c 6f4672752SMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 7f4672752SMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 8f4672752SMarc Zyngier * 9f4672752SMarc Zyngier * This program is free software; you can redistribute it and/or modify 10f4672752SMarc Zyngier * it under the terms of the GNU General Public License, version 2, as 11f4672752SMarc Zyngier * published by the Free Software Foundation. 12f4672752SMarc Zyngier * 13f4672752SMarc Zyngier * This program is distributed in the hope that it will be useful, 14f4672752SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 15f4672752SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16f4672752SMarc Zyngier * GNU General Public License for more details. 17f4672752SMarc Zyngier * 18f4672752SMarc Zyngier * You should have received a copy of the GNU General Public License 19f4672752SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 20f4672752SMarc Zyngier */ 21f4672752SMarc Zyngier 22f4672752SMarc Zyngier #include <linux/errno.h> 23f4672752SMarc Zyngier #include <linux/kvm_host.h> 24f4672752SMarc Zyngier #include <linux/kvm.h> 25834bf887SAlex Bennée #include <linux/hw_breakpoint.h> 26f4672752SMarc Zyngier 27003300deSMarc Zyngier #include <kvm/arm_arch_timer.h> 28003300deSMarc Zyngier 297665f3a8SSuzuki K Poulose #include <asm/cpufeature.h> 30f4672752SMarc Zyngier #include <asm/cputype.h> 31f4672752SMarc Zyngier #include <asm/ptrace.h> 32f4672752SMarc Zyngier #include <asm/kvm_arm.h> 3367f69197SAKASHI Takahiro #include <asm/kvm_asm.h> 34f4672752SMarc Zyngier #include <asm/kvm_coproc.h> 35358b28f0SMarc Zyngier #include <asm/kvm_emulate.h> 3667f69197SAKASHI Takahiro #include <asm/kvm_mmu.h> 37f4672752SMarc Zyngier 380f62f0e9SSuzuki K Poulose /* Maximum phys_shift supported for any VM on this host */ 390f62f0e9SSuzuki K Poulose static u32 kvm_ipa_limit; 400f62f0e9SSuzuki K Poulose 41f4672752SMarc Zyngier /* 42f4672752SMarc Zyngier * ARMv8 Reset Values 43f4672752SMarc Zyngier */ 44f4672752SMarc Zyngier static const struct kvm_regs default_regs_reset = { 45f4672752SMarc Zyngier .regs.pstate = (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | 46f4672752SMarc Zyngier PSR_F_BIT | PSR_D_BIT), 47f4672752SMarc Zyngier }; 48f4672752SMarc Zyngier 490d854a60SMarc Zyngier static const struct kvm_regs default_regs_reset32 = { 50256c0960SMark Rutland .regs.pstate = (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | 51256c0960SMark Rutland PSR_AA32_I_BIT | PSR_AA32_F_BIT), 520d854a60SMarc Zyngier }; 530d854a60SMarc Zyngier 540d854a60SMarc Zyngier static bool cpu_has_32bit_el1(void) 550d854a60SMarc Zyngier { 560d854a60SMarc Zyngier u64 pfr0; 570d854a60SMarc Zyngier 5846823dd1SDave Martin pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 590d854a60SMarc Zyngier return !!(pfr0 & 0x20); 600d854a60SMarc Zyngier } 610d854a60SMarc Zyngier 62834bf887SAlex Bennée /** 63375bdd3bSDongjiu Geng * kvm_arch_vm_ioctl_check_extension 64834bf887SAlex Bennée * 65834bf887SAlex Bennée * We currently assume that the number of HW registers is uniform 66834bf887SAlex Bennée * across all CPUs (see cpuinfo_sanity_check). 67834bf887SAlex Bennée */ 68375bdd3bSDongjiu Geng int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext) 69f4672752SMarc Zyngier { 70f4672752SMarc Zyngier int r; 71f4672752SMarc Zyngier 72f4672752SMarc Zyngier switch (ext) { 730d854a60SMarc Zyngier case KVM_CAP_ARM_EL1_32BIT: 740d854a60SMarc Zyngier r = cpu_has_32bit_el1(); 750d854a60SMarc Zyngier break; 76834bf887SAlex Bennée case KVM_CAP_GUEST_DEBUG_HW_BPS: 77834bf887SAlex Bennée r = get_num_brps(); 78834bf887SAlex Bennée break; 79834bf887SAlex Bennée case KVM_CAP_GUEST_DEBUG_HW_WPS: 80834bf887SAlex Bennée r = get_num_wrps(); 81834bf887SAlex Bennée break; 82808e7381SShannon Zhao case KVM_CAP_ARM_PMU_V3: 83808e7381SShannon Zhao r = kvm_arm_support_pmu_v3(); 84808e7381SShannon Zhao break; 85be26b3a7SDongjiu Geng case KVM_CAP_ARM_INJECT_SERROR_ESR: 86be26b3a7SDongjiu Geng r = cpus_have_const_cap(ARM64_HAS_RAS_EXTN); 87be26b3a7SDongjiu Geng break; 88834bf887SAlex Bennée case KVM_CAP_SET_GUEST_DEBUG: 89f577f6c2SShannon Zhao case KVM_CAP_VCPU_ATTRIBUTES: 90834bf887SAlex Bennée r = 1; 91834bf887SAlex Bennée break; 92233a7cb2SSuzuki K Poulose case KVM_CAP_ARM_VM_IPA_SIZE: 93233a7cb2SSuzuki K Poulose r = kvm_ipa_limit; 94233a7cb2SSuzuki K Poulose break; 95f4672752SMarc Zyngier default: 96f4672752SMarc Zyngier r = 0; 97f4672752SMarc Zyngier } 98f4672752SMarc Zyngier 99f4672752SMarc Zyngier return r; 100f4672752SMarc Zyngier } 101f4672752SMarc Zyngier 102f4672752SMarc Zyngier /** 103f4672752SMarc Zyngier * kvm_reset_vcpu - sets core registers and sys_regs to reset value 104f4672752SMarc Zyngier * @vcpu: The VCPU pointer 105f4672752SMarc Zyngier * 106f4672752SMarc Zyngier * This function finds the right table above and sets the registers on 107edce2292SAndrea Gelmini * the virtual CPU struct to their architecturally defined reset 108f4672752SMarc Zyngier * values. 109e761a927SChristoffer Dall * 110e761a927SChristoffer Dall * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT 111e761a927SChristoffer Dall * ioctl or as part of handling a request issued by another VCPU in the PSCI 112e761a927SChristoffer Dall * handling code. In the first case, the VCPU will not be loaded, and in the 113e761a927SChristoffer Dall * second case the VCPU will be loaded. Because this function operates purely 114e761a927SChristoffer Dall * on the memory-backed valus of system registers, we want to do a full put if 115e761a927SChristoffer Dall * we were loaded (handling a request) and load the values back at the end of 116e761a927SChristoffer Dall * the function. Otherwise we leave the state alone. In both cases, we 117e761a927SChristoffer Dall * disable preemption around the vcpu reset as we would otherwise race with 118e761a927SChristoffer Dall * preempt notifiers which also call put/load. 119f4672752SMarc Zyngier */ 120f4672752SMarc Zyngier int kvm_reset_vcpu(struct kvm_vcpu *vcpu) 121f4672752SMarc Zyngier { 122f4672752SMarc Zyngier const struct kvm_regs *cpu_reset; 123e761a927SChristoffer Dall int ret = -EINVAL; 124e761a927SChristoffer Dall bool loaded; 125e761a927SChristoffer Dall 126ebff0b0eSMarc Zyngier /* Reset PMU outside of the non-preemptible section */ 127ebff0b0eSMarc Zyngier kvm_pmu_vcpu_reset(vcpu); 128ebff0b0eSMarc Zyngier 129e761a927SChristoffer Dall preempt_disable(); 130e761a927SChristoffer Dall loaded = (vcpu->cpu != -1); 131e761a927SChristoffer Dall if (loaded) 132e761a927SChristoffer Dall kvm_arch_vcpu_put(vcpu); 133f4672752SMarc Zyngier 134f4672752SMarc Zyngier switch (vcpu->arch.target) { 135f4672752SMarc Zyngier default: 1360d854a60SMarc Zyngier if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) { 1370d854a60SMarc Zyngier if (!cpu_has_32bit_el1()) 138e761a927SChristoffer Dall goto out; 1390d854a60SMarc Zyngier cpu_reset = &default_regs_reset32; 1400d854a60SMarc Zyngier } else { 141f4672752SMarc Zyngier cpu_reset = &default_regs_reset; 1420d854a60SMarc Zyngier } 1430d854a60SMarc Zyngier 144f4672752SMarc Zyngier break; 145f4672752SMarc Zyngier } 146f4672752SMarc Zyngier 147f4672752SMarc Zyngier /* Reset core registers */ 148f4672752SMarc Zyngier memcpy(vcpu_gp_regs(vcpu), cpu_reset, sizeof(*cpu_reset)); 149f4672752SMarc Zyngier 150f4672752SMarc Zyngier /* Reset system registers */ 151f4672752SMarc Zyngier kvm_reset_sys_regs(vcpu); 152f4672752SMarc Zyngier 153358b28f0SMarc Zyngier /* 154358b28f0SMarc Zyngier * Additional reset state handling that PSCI may have imposed on us. 155358b28f0SMarc Zyngier * Must be done after all the sys_reg reset. 156358b28f0SMarc Zyngier */ 157358b28f0SMarc Zyngier if (vcpu->arch.reset_state.reset) { 158358b28f0SMarc Zyngier unsigned long target_pc = vcpu->arch.reset_state.pc; 159358b28f0SMarc Zyngier 160358b28f0SMarc Zyngier /* Gracefully handle Thumb2 entry point */ 161358b28f0SMarc Zyngier if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) { 162358b28f0SMarc Zyngier target_pc &= ~1UL; 163358b28f0SMarc Zyngier vcpu_set_thumb(vcpu); 164358b28f0SMarc Zyngier } 165358b28f0SMarc Zyngier 166358b28f0SMarc Zyngier /* Propagate caller endianness */ 167358b28f0SMarc Zyngier if (vcpu->arch.reset_state.be) 168358b28f0SMarc Zyngier kvm_vcpu_set_be(vcpu); 169358b28f0SMarc Zyngier 170358b28f0SMarc Zyngier *vcpu_pc(vcpu) = target_pc; 171358b28f0SMarc Zyngier vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0); 172358b28f0SMarc Zyngier 173358b28f0SMarc Zyngier vcpu->arch.reset_state.reset = false; 174358b28f0SMarc Zyngier } 175358b28f0SMarc Zyngier 1765d81f7dcSMarc Zyngier /* Default workaround setup is enabled (if supported) */ 1775d81f7dcSMarc Zyngier if (kvm_arm_have_ssbd() == KVM_SSBD_KERNEL) 1785d81f7dcSMarc Zyngier vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG; 1795d81f7dcSMarc Zyngier 180003300deSMarc Zyngier /* Reset timer */ 181e761a927SChristoffer Dall ret = kvm_timer_vcpu_reset(vcpu); 182e761a927SChristoffer Dall out: 183e761a927SChristoffer Dall if (loaded) 184e761a927SChristoffer Dall kvm_arch_vcpu_load(vcpu, smp_processor_id()); 185e761a927SChristoffer Dall preempt_enable(); 186e761a927SChristoffer Dall return ret; 187f4672752SMarc Zyngier } 1885b6c6742SSuzuki K Poulose 1890f62f0e9SSuzuki K Poulose void kvm_set_ipa_limit(void) 1900f62f0e9SSuzuki K Poulose { 1910f62f0e9SSuzuki K Poulose unsigned int ipa_max, pa_max, va_max, parange; 1920f62f0e9SSuzuki K Poulose 1930f62f0e9SSuzuki K Poulose parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 0x7; 1940f62f0e9SSuzuki K Poulose pa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 1950f62f0e9SSuzuki K Poulose 1960f62f0e9SSuzuki K Poulose /* Clamp the IPA limit to the PA size supported by the kernel */ 1970f62f0e9SSuzuki K Poulose ipa_max = (pa_max > PHYS_MASK_SHIFT) ? PHYS_MASK_SHIFT : pa_max; 1980f62f0e9SSuzuki K Poulose /* 1990f62f0e9SSuzuki K Poulose * Since our stage2 table is dependent on the stage1 page table code, 2000f62f0e9SSuzuki K Poulose * we must always honor the following condition: 2010f62f0e9SSuzuki K Poulose * 2020f62f0e9SSuzuki K Poulose * Number of levels in Stage1 >= Number of levels in Stage2. 2030f62f0e9SSuzuki K Poulose * 2040f62f0e9SSuzuki K Poulose * So clamp the ipa limit further down to limit the number of levels. 2050f62f0e9SSuzuki K Poulose * Since we can concatenate upto 16 tables at entry level, we could 2060f62f0e9SSuzuki K Poulose * go upto 4bits above the maximum VA addressible with the current 2070f62f0e9SSuzuki K Poulose * number of levels. 2080f62f0e9SSuzuki K Poulose */ 2090f62f0e9SSuzuki K Poulose va_max = PGDIR_SHIFT + PAGE_SHIFT - 3; 2100f62f0e9SSuzuki K Poulose va_max += 4; 2110f62f0e9SSuzuki K Poulose 2120f62f0e9SSuzuki K Poulose if (va_max < ipa_max) 2130f62f0e9SSuzuki K Poulose ipa_max = va_max; 2140f62f0e9SSuzuki K Poulose 2150f62f0e9SSuzuki K Poulose /* 2160f62f0e9SSuzuki K Poulose * If the final limit is lower than the real physical address 2170f62f0e9SSuzuki K Poulose * limit of the CPUs, report the reason. 2180f62f0e9SSuzuki K Poulose */ 2190f62f0e9SSuzuki K Poulose if (ipa_max < pa_max) 2200f62f0e9SSuzuki K Poulose pr_info("kvm: Limiting the IPA size due to kernel %s Address limit\n", 2210f62f0e9SSuzuki K Poulose (va_max < pa_max) ? "Virtual" : "Physical"); 2220f62f0e9SSuzuki K Poulose 2230f62f0e9SSuzuki K Poulose WARN(ipa_max < KVM_PHYS_SHIFT, 2240f62f0e9SSuzuki K Poulose "KVM IPA limit (%d bit) is smaller than default size\n", ipa_max); 2250f62f0e9SSuzuki K Poulose kvm_ipa_limit = ipa_max; 2260f62f0e9SSuzuki K Poulose kvm_info("IPA Size Limit: %dbits\n", kvm_ipa_limit); 2270f62f0e9SSuzuki K Poulose } 2280f62f0e9SSuzuki K Poulose 2297665f3a8SSuzuki K Poulose /* 2307665f3a8SSuzuki K Poulose * Configure the VTCR_EL2 for this VM. The VTCR value is common 2317665f3a8SSuzuki K Poulose * across all the physical CPUs on the system. We use system wide 2327665f3a8SSuzuki K Poulose * sanitised values to fill in different fields, except for Hardware 2337665f3a8SSuzuki K Poulose * Management of Access Flags. HA Flag is set unconditionally on 2347665f3a8SSuzuki K Poulose * all CPUs, as it is safe to run with or without the feature and 2357665f3a8SSuzuki K Poulose * the bit is RES0 on CPUs that don't support it. 2367665f3a8SSuzuki K Poulose */ 237bca607ebSMarc Zyngier int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type) 2385b6c6742SSuzuki K Poulose { 2397665f3a8SSuzuki K Poulose u64 vtcr = VTCR_EL2_FLAGS; 2407665f3a8SSuzuki K Poulose u32 parange, phys_shift; 24158b3efc8SSuzuki K Poulose u8 lvls; 2427665f3a8SSuzuki K Poulose 243233a7cb2SSuzuki K Poulose if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK) 2445b6c6742SSuzuki K Poulose return -EINVAL; 2457665f3a8SSuzuki K Poulose 246233a7cb2SSuzuki K Poulose phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type); 247233a7cb2SSuzuki K Poulose if (phys_shift) { 248233a7cb2SSuzuki K Poulose if (phys_shift > kvm_ipa_limit || 249233a7cb2SSuzuki K Poulose phys_shift < 32) 250233a7cb2SSuzuki K Poulose return -EINVAL; 251233a7cb2SSuzuki K Poulose } else { 252233a7cb2SSuzuki K Poulose phys_shift = KVM_PHYS_SHIFT; 253233a7cb2SSuzuki K Poulose } 254233a7cb2SSuzuki K Poulose 2557665f3a8SSuzuki K Poulose parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 7; 2567665f3a8SSuzuki K Poulose if (parange > ID_AA64MMFR0_PARANGE_MAX) 2577665f3a8SSuzuki K Poulose parange = ID_AA64MMFR0_PARANGE_MAX; 2587665f3a8SSuzuki K Poulose vtcr |= parange << VTCR_EL2_PS_SHIFT; 2597665f3a8SSuzuki K Poulose 2607665f3a8SSuzuki K Poulose vtcr |= VTCR_EL2_T0SZ(phys_shift); 26158b3efc8SSuzuki K Poulose /* 26258b3efc8SSuzuki K Poulose * Use a minimum 2 level page table to prevent splitting 26358b3efc8SSuzuki K Poulose * host PMD huge pages at stage2. 26458b3efc8SSuzuki K Poulose */ 26558b3efc8SSuzuki K Poulose lvls = stage2_pgtable_levels(phys_shift); 26658b3efc8SSuzuki K Poulose if (lvls < 2) 26758b3efc8SSuzuki K Poulose lvls = 2; 26858b3efc8SSuzuki K Poulose vtcr |= VTCR_EL2_LVLS_TO_SL0(lvls); 2697665f3a8SSuzuki K Poulose 2707665f3a8SSuzuki K Poulose /* 2717665f3a8SSuzuki K Poulose * Enable the Hardware Access Flag management, unconditionally 2727665f3a8SSuzuki K Poulose * on all CPUs. The features is RES0 on CPUs without the support 2737665f3a8SSuzuki K Poulose * and must be ignored by the CPUs. 2747665f3a8SSuzuki K Poulose */ 2757665f3a8SSuzuki K Poulose vtcr |= VTCR_EL2_HA; 2767665f3a8SSuzuki K Poulose 2777665f3a8SSuzuki K Poulose /* Set the vmid bits */ 2787665f3a8SSuzuki K Poulose vtcr |= (kvm_get_vmid_bits() == 16) ? 2797665f3a8SSuzuki K Poulose VTCR_EL2_VS_16BIT : 2807665f3a8SSuzuki K Poulose VTCR_EL2_VS_8BIT; 2817665f3a8SSuzuki K Poulose kvm->arch.vtcr = vtcr; 2825b6c6742SSuzuki K Poulose return 0; 2835b6c6742SSuzuki K Poulose } 284