1f4672752SMarc Zyngier /* 2f4672752SMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 3f4672752SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 4f4672752SMarc Zyngier * 5f4672752SMarc Zyngier * Derived from arch/arm/kvm/reset.c 6f4672752SMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 7f4672752SMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 8f4672752SMarc Zyngier * 9f4672752SMarc Zyngier * This program is free software; you can redistribute it and/or modify 10f4672752SMarc Zyngier * it under the terms of the GNU General Public License, version 2, as 11f4672752SMarc Zyngier * published by the Free Software Foundation. 12f4672752SMarc Zyngier * 13f4672752SMarc Zyngier * This program is distributed in the hope that it will be useful, 14f4672752SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 15f4672752SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16f4672752SMarc Zyngier * GNU General Public License for more details. 17f4672752SMarc Zyngier * 18f4672752SMarc Zyngier * You should have received a copy of the GNU General Public License 19f4672752SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 20f4672752SMarc Zyngier */ 21f4672752SMarc Zyngier 22f4672752SMarc Zyngier #include <linux/errno.h> 239a3cdf26SDave Martin #include <linux/kernel.h> 24f4672752SMarc Zyngier #include <linux/kvm_host.h> 25f4672752SMarc Zyngier #include <linux/kvm.h> 26834bf887SAlex Bennée #include <linux/hw_breakpoint.h> 279033bba4SDave Martin #include <linux/slab.h> 289a3cdf26SDave Martin #include <linux/string.h> 299033bba4SDave Martin #include <linux/types.h> 30f4672752SMarc Zyngier 31003300deSMarc Zyngier #include <kvm/arm_arch_timer.h> 32003300deSMarc Zyngier 337665f3a8SSuzuki K Poulose #include <asm/cpufeature.h> 34f4672752SMarc Zyngier #include <asm/cputype.h> 359033bba4SDave Martin #include <asm/fpsimd.h> 36f4672752SMarc Zyngier #include <asm/ptrace.h> 37f4672752SMarc Zyngier #include <asm/kvm_arm.h> 3867f69197SAKASHI Takahiro #include <asm/kvm_asm.h> 39f4672752SMarc Zyngier #include <asm/kvm_coproc.h> 40358b28f0SMarc Zyngier #include <asm/kvm_emulate.h> 4167f69197SAKASHI Takahiro #include <asm/kvm_mmu.h> 429a3cdf26SDave Martin #include <asm/virt.h> 43f4672752SMarc Zyngier 440f62f0e9SSuzuki K Poulose /* Maximum phys_shift supported for any VM on this host */ 450f62f0e9SSuzuki K Poulose static u32 kvm_ipa_limit; 460f62f0e9SSuzuki K Poulose 47f4672752SMarc Zyngier /* 48f4672752SMarc Zyngier * ARMv8 Reset Values 49f4672752SMarc Zyngier */ 50f4672752SMarc Zyngier static const struct kvm_regs default_regs_reset = { 51f4672752SMarc Zyngier .regs.pstate = (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | 52f4672752SMarc Zyngier PSR_F_BIT | PSR_D_BIT), 53f4672752SMarc Zyngier }; 54f4672752SMarc Zyngier 550d854a60SMarc Zyngier static const struct kvm_regs default_regs_reset32 = { 56256c0960SMark Rutland .regs.pstate = (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | 57256c0960SMark Rutland PSR_AA32_I_BIT | PSR_AA32_F_BIT), 580d854a60SMarc Zyngier }; 590d854a60SMarc Zyngier 600d854a60SMarc Zyngier static bool cpu_has_32bit_el1(void) 610d854a60SMarc Zyngier { 620d854a60SMarc Zyngier u64 pfr0; 630d854a60SMarc Zyngier 6446823dd1SDave Martin pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 650d854a60SMarc Zyngier return !!(pfr0 & 0x20); 660d854a60SMarc Zyngier } 670d854a60SMarc Zyngier 68834bf887SAlex Bennée /** 69375bdd3bSDongjiu Geng * kvm_arch_vm_ioctl_check_extension 70834bf887SAlex Bennée * 71834bf887SAlex Bennée * We currently assume that the number of HW registers is uniform 72834bf887SAlex Bennée * across all CPUs (see cpuinfo_sanity_check). 73834bf887SAlex Bennée */ 74375bdd3bSDongjiu Geng int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext) 75f4672752SMarc Zyngier { 76f4672752SMarc Zyngier int r; 77f4672752SMarc Zyngier 78f4672752SMarc Zyngier switch (ext) { 790d854a60SMarc Zyngier case KVM_CAP_ARM_EL1_32BIT: 800d854a60SMarc Zyngier r = cpu_has_32bit_el1(); 810d854a60SMarc Zyngier break; 82834bf887SAlex Bennée case KVM_CAP_GUEST_DEBUG_HW_BPS: 83834bf887SAlex Bennée r = get_num_brps(); 84834bf887SAlex Bennée break; 85834bf887SAlex Bennée case KVM_CAP_GUEST_DEBUG_HW_WPS: 86834bf887SAlex Bennée r = get_num_wrps(); 87834bf887SAlex Bennée break; 88808e7381SShannon Zhao case KVM_CAP_ARM_PMU_V3: 89808e7381SShannon Zhao r = kvm_arm_support_pmu_v3(); 90808e7381SShannon Zhao break; 91be26b3a7SDongjiu Geng case KVM_CAP_ARM_INJECT_SERROR_ESR: 92be26b3a7SDongjiu Geng r = cpus_have_const_cap(ARM64_HAS_RAS_EXTN); 93be26b3a7SDongjiu Geng break; 94834bf887SAlex Bennée case KVM_CAP_SET_GUEST_DEBUG: 95f577f6c2SShannon Zhao case KVM_CAP_VCPU_ATTRIBUTES: 96834bf887SAlex Bennée r = 1; 97834bf887SAlex Bennée break; 98233a7cb2SSuzuki K Poulose case KVM_CAP_ARM_VM_IPA_SIZE: 99233a7cb2SSuzuki K Poulose r = kvm_ipa_limit; 100233a7cb2SSuzuki K Poulose break; 101555f3d03SDave Martin case KVM_CAP_ARM_SVE: 102555f3d03SDave Martin r = system_supports_sve(); 103555f3d03SDave Martin break; 104f4672752SMarc Zyngier default: 105f4672752SMarc Zyngier r = 0; 106f4672752SMarc Zyngier } 107f4672752SMarc Zyngier 108f4672752SMarc Zyngier return r; 109f4672752SMarc Zyngier } 110f4672752SMarc Zyngier 1119033bba4SDave Martin unsigned int kvm_sve_max_vl; 1129033bba4SDave Martin 113a3be836dSDave Martin int kvm_arm_init_sve(void) 1149033bba4SDave Martin { 1159033bba4SDave Martin if (system_supports_sve()) { 1169033bba4SDave Martin kvm_sve_max_vl = sve_max_virtualisable_vl; 1179033bba4SDave Martin 1189033bba4SDave Martin /* 1199033bba4SDave Martin * The get_sve_reg()/set_sve_reg() ioctl interface will need 1209033bba4SDave Martin * to be extended with multiple register slice support in 1219033bba4SDave Martin * order to support vector lengths greater than 1229033bba4SDave Martin * SVE_VL_ARCH_MAX: 1239033bba4SDave Martin */ 1249033bba4SDave Martin if (WARN_ON(kvm_sve_max_vl > SVE_VL_ARCH_MAX)) 1259033bba4SDave Martin kvm_sve_max_vl = SVE_VL_ARCH_MAX; 1269033bba4SDave Martin 1279033bba4SDave Martin /* 1289033bba4SDave Martin * Don't even try to make use of vector lengths that 1299033bba4SDave Martin * aren't available on all CPUs, for now: 1309033bba4SDave Martin */ 1319033bba4SDave Martin if (kvm_sve_max_vl < sve_max_vl) 1329033bba4SDave Martin pr_warn("KVM: SVE vector length for guests limited to %u bytes\n", 1339033bba4SDave Martin kvm_sve_max_vl); 1349033bba4SDave Martin } 1359033bba4SDave Martin 1369033bba4SDave Martin return 0; 1379033bba4SDave Martin } 1389033bba4SDave Martin 1399a3cdf26SDave Martin static int kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu) 1409a3cdf26SDave Martin { 1419a3cdf26SDave Martin if (!system_supports_sve()) 1429a3cdf26SDave Martin return -EINVAL; 1439a3cdf26SDave Martin 1449a3cdf26SDave Martin /* Verify that KVM startup enforced this when SVE was detected: */ 1459a3cdf26SDave Martin if (WARN_ON(!has_vhe())) 1469a3cdf26SDave Martin return -EINVAL; 1479a3cdf26SDave Martin 1489a3cdf26SDave Martin vcpu->arch.sve_max_vl = kvm_sve_max_vl; 1499a3cdf26SDave Martin 1509a3cdf26SDave Martin /* 1519a3cdf26SDave Martin * Userspace can still customize the vector lengths by writing 1529a3cdf26SDave Martin * KVM_REG_ARM64_SVE_VLS. Allocation is deferred until 1539a3cdf26SDave Martin * kvm_arm_vcpu_finalize(), which freezes the configuration. 1549a3cdf26SDave Martin */ 1559a3cdf26SDave Martin vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE; 1569a3cdf26SDave Martin 1579a3cdf26SDave Martin return 0; 1589a3cdf26SDave Martin } 1599a3cdf26SDave Martin 1609033bba4SDave Martin /* 1619033bba4SDave Martin * Finalize vcpu's maximum SVE vector length, allocating 1629033bba4SDave Martin * vcpu->arch.sve_state as necessary. 1639033bba4SDave Martin */ 1649033bba4SDave Martin static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu) 1659033bba4SDave Martin { 1669033bba4SDave Martin void *buf; 1679033bba4SDave Martin unsigned int vl; 1689033bba4SDave Martin 1699033bba4SDave Martin vl = vcpu->arch.sve_max_vl; 1709033bba4SDave Martin 1719033bba4SDave Martin /* 1729033bba4SDave Martin * Resposibility for these properties is shared between 1739033bba4SDave Martin * kvm_arm_init_arch_resources(), kvm_vcpu_enable_sve() and 1749033bba4SDave Martin * set_sve_vls(). Double-check here just to be sure: 1759033bba4SDave Martin */ 1769033bba4SDave Martin if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl || 1779033bba4SDave Martin vl > SVE_VL_ARCH_MAX)) 1789033bba4SDave Martin return -EIO; 1799033bba4SDave Martin 1809033bba4SDave Martin buf = kzalloc(SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl)), GFP_KERNEL); 1819033bba4SDave Martin if (!buf) 1829033bba4SDave Martin return -ENOMEM; 1839033bba4SDave Martin 1849033bba4SDave Martin vcpu->arch.sve_state = buf; 1859033bba4SDave Martin vcpu->arch.flags |= KVM_ARM64_VCPU_SVE_FINALIZED; 1869033bba4SDave Martin return 0; 1879033bba4SDave Martin } 1889033bba4SDave Martin 1899033bba4SDave Martin int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int what) 1909033bba4SDave Martin { 1919033bba4SDave Martin switch (what) { 1929033bba4SDave Martin case KVM_ARM_VCPU_SVE: 1939033bba4SDave Martin if (!vcpu_has_sve(vcpu)) 1949033bba4SDave Martin return -EINVAL; 1959033bba4SDave Martin 1969033bba4SDave Martin if (kvm_arm_vcpu_sve_finalized(vcpu)) 1979033bba4SDave Martin return -EPERM; 1989033bba4SDave Martin 1999033bba4SDave Martin return kvm_vcpu_finalize_sve(vcpu); 2009033bba4SDave Martin } 2019033bba4SDave Martin 2029033bba4SDave Martin return -EINVAL; 2039033bba4SDave Martin } 2049033bba4SDave Martin 2059033bba4SDave Martin bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu) 2069033bba4SDave Martin { 2079033bba4SDave Martin if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu)) 2089033bba4SDave Martin return false; 2099033bba4SDave Martin 2109033bba4SDave Martin return true; 2119033bba4SDave Martin } 2129033bba4SDave Martin 2139033bba4SDave Martin void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 2149033bba4SDave Martin { 2159033bba4SDave Martin kfree(vcpu->arch.sve_state); 2169033bba4SDave Martin } 2179033bba4SDave Martin 2189a3cdf26SDave Martin static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) 2199a3cdf26SDave Martin { 2209a3cdf26SDave Martin if (vcpu_has_sve(vcpu)) 2219a3cdf26SDave Martin memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu)); 2229a3cdf26SDave Martin } 2239a3cdf26SDave Martin 224f4672752SMarc Zyngier /** 225f4672752SMarc Zyngier * kvm_reset_vcpu - sets core registers and sys_regs to reset value 226f4672752SMarc Zyngier * @vcpu: The VCPU pointer 227f4672752SMarc Zyngier * 228f4672752SMarc Zyngier * This function finds the right table above and sets the registers on 229edce2292SAndrea Gelmini * the virtual CPU struct to their architecturally defined reset 2309a3cdf26SDave Martin * values, except for registers whose reset is deferred until 2319a3cdf26SDave Martin * kvm_arm_vcpu_finalize(). 232e761a927SChristoffer Dall * 233e761a927SChristoffer Dall * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT 234e761a927SChristoffer Dall * ioctl or as part of handling a request issued by another VCPU in the PSCI 235e761a927SChristoffer Dall * handling code. In the first case, the VCPU will not be loaded, and in the 236e761a927SChristoffer Dall * second case the VCPU will be loaded. Because this function operates purely 237e761a927SChristoffer Dall * on the memory-backed valus of system registers, we want to do a full put if 238e761a927SChristoffer Dall * we were loaded (handling a request) and load the values back at the end of 239e761a927SChristoffer Dall * the function. Otherwise we leave the state alone. In both cases, we 240e761a927SChristoffer Dall * disable preemption around the vcpu reset as we would otherwise race with 241e761a927SChristoffer Dall * preempt notifiers which also call put/load. 242f4672752SMarc Zyngier */ 243f4672752SMarc Zyngier int kvm_reset_vcpu(struct kvm_vcpu *vcpu) 244f4672752SMarc Zyngier { 245f4672752SMarc Zyngier const struct kvm_regs *cpu_reset; 246e761a927SChristoffer Dall int ret = -EINVAL; 247e761a927SChristoffer Dall bool loaded; 248e761a927SChristoffer Dall 249e761a927SChristoffer Dall preempt_disable(); 250e761a927SChristoffer Dall loaded = (vcpu->cpu != -1); 251e761a927SChristoffer Dall if (loaded) 252e761a927SChristoffer Dall kvm_arch_vcpu_put(vcpu); 253f4672752SMarc Zyngier 2549a3cdf26SDave Martin if (!kvm_arm_vcpu_sve_finalized(vcpu)) { 2559a3cdf26SDave Martin if (test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) { 2569a3cdf26SDave Martin ret = kvm_vcpu_enable_sve(vcpu); 2579a3cdf26SDave Martin if (ret) 2589a3cdf26SDave Martin goto out; 2599a3cdf26SDave Martin } 2609a3cdf26SDave Martin } else { 2619a3cdf26SDave Martin kvm_vcpu_reset_sve(vcpu); 2629a3cdf26SDave Martin } 2639a3cdf26SDave Martin 264f4672752SMarc Zyngier switch (vcpu->arch.target) { 265f4672752SMarc Zyngier default: 2660d854a60SMarc Zyngier if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) { 2670d854a60SMarc Zyngier if (!cpu_has_32bit_el1()) 268e761a927SChristoffer Dall goto out; 2690d854a60SMarc Zyngier cpu_reset = &default_regs_reset32; 2700d854a60SMarc Zyngier } else { 271f4672752SMarc Zyngier cpu_reset = &default_regs_reset; 2720d854a60SMarc Zyngier } 2730d854a60SMarc Zyngier 274f4672752SMarc Zyngier break; 275f4672752SMarc Zyngier } 276f4672752SMarc Zyngier 277f4672752SMarc Zyngier /* Reset core registers */ 278f4672752SMarc Zyngier memcpy(vcpu_gp_regs(vcpu), cpu_reset, sizeof(*cpu_reset)); 279f4672752SMarc Zyngier 280f4672752SMarc Zyngier /* Reset system registers */ 281f4672752SMarc Zyngier kvm_reset_sys_regs(vcpu); 282f4672752SMarc Zyngier 283358b28f0SMarc Zyngier /* 284358b28f0SMarc Zyngier * Additional reset state handling that PSCI may have imposed on us. 285358b28f0SMarc Zyngier * Must be done after all the sys_reg reset. 286358b28f0SMarc Zyngier */ 287358b28f0SMarc Zyngier if (vcpu->arch.reset_state.reset) { 288358b28f0SMarc Zyngier unsigned long target_pc = vcpu->arch.reset_state.pc; 289358b28f0SMarc Zyngier 290358b28f0SMarc Zyngier /* Gracefully handle Thumb2 entry point */ 291358b28f0SMarc Zyngier if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) { 292358b28f0SMarc Zyngier target_pc &= ~1UL; 293358b28f0SMarc Zyngier vcpu_set_thumb(vcpu); 294358b28f0SMarc Zyngier } 295358b28f0SMarc Zyngier 296358b28f0SMarc Zyngier /* Propagate caller endianness */ 297358b28f0SMarc Zyngier if (vcpu->arch.reset_state.be) 298358b28f0SMarc Zyngier kvm_vcpu_set_be(vcpu); 299358b28f0SMarc Zyngier 300358b28f0SMarc Zyngier *vcpu_pc(vcpu) = target_pc; 301358b28f0SMarc Zyngier vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0); 302358b28f0SMarc Zyngier 303358b28f0SMarc Zyngier vcpu->arch.reset_state.reset = false; 304358b28f0SMarc Zyngier } 305358b28f0SMarc Zyngier 3062aa36e98SShannon Zhao /* Reset PMU */ 3072aa36e98SShannon Zhao kvm_pmu_vcpu_reset(vcpu); 3082aa36e98SShannon Zhao 3095d81f7dcSMarc Zyngier /* Default workaround setup is enabled (if supported) */ 3105d81f7dcSMarc Zyngier if (kvm_arm_have_ssbd() == KVM_SSBD_KERNEL) 3115d81f7dcSMarc Zyngier vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG; 3125d81f7dcSMarc Zyngier 313003300deSMarc Zyngier /* Reset timer */ 314e761a927SChristoffer Dall ret = kvm_timer_vcpu_reset(vcpu); 315e761a927SChristoffer Dall out: 316e761a927SChristoffer Dall if (loaded) 317e761a927SChristoffer Dall kvm_arch_vcpu_load(vcpu, smp_processor_id()); 318e761a927SChristoffer Dall preempt_enable(); 319e761a927SChristoffer Dall return ret; 320f4672752SMarc Zyngier } 3215b6c6742SSuzuki K Poulose 3220f62f0e9SSuzuki K Poulose void kvm_set_ipa_limit(void) 3230f62f0e9SSuzuki K Poulose { 3240f62f0e9SSuzuki K Poulose unsigned int ipa_max, pa_max, va_max, parange; 3250f62f0e9SSuzuki K Poulose 3260f62f0e9SSuzuki K Poulose parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 0x7; 3270f62f0e9SSuzuki K Poulose pa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3280f62f0e9SSuzuki K Poulose 3290f62f0e9SSuzuki K Poulose /* Clamp the IPA limit to the PA size supported by the kernel */ 3300f62f0e9SSuzuki K Poulose ipa_max = (pa_max > PHYS_MASK_SHIFT) ? PHYS_MASK_SHIFT : pa_max; 3310f62f0e9SSuzuki K Poulose /* 3320f62f0e9SSuzuki K Poulose * Since our stage2 table is dependent on the stage1 page table code, 3330f62f0e9SSuzuki K Poulose * we must always honor the following condition: 3340f62f0e9SSuzuki K Poulose * 3350f62f0e9SSuzuki K Poulose * Number of levels in Stage1 >= Number of levels in Stage2. 3360f62f0e9SSuzuki K Poulose * 3370f62f0e9SSuzuki K Poulose * So clamp the ipa limit further down to limit the number of levels. 3380f62f0e9SSuzuki K Poulose * Since we can concatenate upto 16 tables at entry level, we could 3390f62f0e9SSuzuki K Poulose * go upto 4bits above the maximum VA addressible with the current 3400f62f0e9SSuzuki K Poulose * number of levels. 3410f62f0e9SSuzuki K Poulose */ 3420f62f0e9SSuzuki K Poulose va_max = PGDIR_SHIFT + PAGE_SHIFT - 3; 3430f62f0e9SSuzuki K Poulose va_max += 4; 3440f62f0e9SSuzuki K Poulose 3450f62f0e9SSuzuki K Poulose if (va_max < ipa_max) 3460f62f0e9SSuzuki K Poulose ipa_max = va_max; 3470f62f0e9SSuzuki K Poulose 3480f62f0e9SSuzuki K Poulose /* 3490f62f0e9SSuzuki K Poulose * If the final limit is lower than the real physical address 3500f62f0e9SSuzuki K Poulose * limit of the CPUs, report the reason. 3510f62f0e9SSuzuki K Poulose */ 3520f62f0e9SSuzuki K Poulose if (ipa_max < pa_max) 3530f62f0e9SSuzuki K Poulose pr_info("kvm: Limiting the IPA size due to kernel %s Address limit\n", 3540f62f0e9SSuzuki K Poulose (va_max < pa_max) ? "Virtual" : "Physical"); 3550f62f0e9SSuzuki K Poulose 3560f62f0e9SSuzuki K Poulose WARN(ipa_max < KVM_PHYS_SHIFT, 3570f62f0e9SSuzuki K Poulose "KVM IPA limit (%d bit) is smaller than default size\n", ipa_max); 3580f62f0e9SSuzuki K Poulose kvm_ipa_limit = ipa_max; 3590f62f0e9SSuzuki K Poulose kvm_info("IPA Size Limit: %dbits\n", kvm_ipa_limit); 3600f62f0e9SSuzuki K Poulose } 3610f62f0e9SSuzuki K Poulose 3627665f3a8SSuzuki K Poulose /* 3637665f3a8SSuzuki K Poulose * Configure the VTCR_EL2 for this VM. The VTCR value is common 3647665f3a8SSuzuki K Poulose * across all the physical CPUs on the system. We use system wide 3657665f3a8SSuzuki K Poulose * sanitised values to fill in different fields, except for Hardware 3667665f3a8SSuzuki K Poulose * Management of Access Flags. HA Flag is set unconditionally on 3677665f3a8SSuzuki K Poulose * all CPUs, as it is safe to run with or without the feature and 3687665f3a8SSuzuki K Poulose * the bit is RES0 on CPUs that don't support it. 3697665f3a8SSuzuki K Poulose */ 370bca607ebSMarc Zyngier int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type) 3715b6c6742SSuzuki K Poulose { 3727665f3a8SSuzuki K Poulose u64 vtcr = VTCR_EL2_FLAGS; 3737665f3a8SSuzuki K Poulose u32 parange, phys_shift; 37458b3efc8SSuzuki K Poulose u8 lvls; 3757665f3a8SSuzuki K Poulose 376233a7cb2SSuzuki K Poulose if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK) 3775b6c6742SSuzuki K Poulose return -EINVAL; 3787665f3a8SSuzuki K Poulose 379233a7cb2SSuzuki K Poulose phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type); 380233a7cb2SSuzuki K Poulose if (phys_shift) { 381233a7cb2SSuzuki K Poulose if (phys_shift > kvm_ipa_limit || 382233a7cb2SSuzuki K Poulose phys_shift < 32) 383233a7cb2SSuzuki K Poulose return -EINVAL; 384233a7cb2SSuzuki K Poulose } else { 385233a7cb2SSuzuki K Poulose phys_shift = KVM_PHYS_SHIFT; 386233a7cb2SSuzuki K Poulose } 387233a7cb2SSuzuki K Poulose 3887665f3a8SSuzuki K Poulose parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 7; 3897665f3a8SSuzuki K Poulose if (parange > ID_AA64MMFR0_PARANGE_MAX) 3907665f3a8SSuzuki K Poulose parange = ID_AA64MMFR0_PARANGE_MAX; 3917665f3a8SSuzuki K Poulose vtcr |= parange << VTCR_EL2_PS_SHIFT; 3927665f3a8SSuzuki K Poulose 3937665f3a8SSuzuki K Poulose vtcr |= VTCR_EL2_T0SZ(phys_shift); 39458b3efc8SSuzuki K Poulose /* 39558b3efc8SSuzuki K Poulose * Use a minimum 2 level page table to prevent splitting 39658b3efc8SSuzuki K Poulose * host PMD huge pages at stage2. 39758b3efc8SSuzuki K Poulose */ 39858b3efc8SSuzuki K Poulose lvls = stage2_pgtable_levels(phys_shift); 39958b3efc8SSuzuki K Poulose if (lvls < 2) 40058b3efc8SSuzuki K Poulose lvls = 2; 40158b3efc8SSuzuki K Poulose vtcr |= VTCR_EL2_LVLS_TO_SL0(lvls); 4027665f3a8SSuzuki K Poulose 4037665f3a8SSuzuki K Poulose /* 4047665f3a8SSuzuki K Poulose * Enable the Hardware Access Flag management, unconditionally 4057665f3a8SSuzuki K Poulose * on all CPUs. The features is RES0 on CPUs without the support 4067665f3a8SSuzuki K Poulose * and must be ignored by the CPUs. 4077665f3a8SSuzuki K Poulose */ 4087665f3a8SSuzuki K Poulose vtcr |= VTCR_EL2_HA; 4097665f3a8SSuzuki K Poulose 4107665f3a8SSuzuki K Poulose /* Set the vmid bits */ 4117665f3a8SSuzuki K Poulose vtcr |= (kvm_get_vmid_bits() == 16) ? 4127665f3a8SSuzuki K Poulose VTCR_EL2_VS_16BIT : 4137665f3a8SSuzuki K Poulose VTCR_EL2_VS_8BIT; 4147665f3a8SSuzuki K Poulose kvm->arch.vtcr = vtcr; 4155b6c6742SSuzuki K Poulose return 0; 4165b6c6742SSuzuki K Poulose } 417