1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2f4672752SMarc Zyngier /* 3f4672752SMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 4f4672752SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 5f4672752SMarc Zyngier * 6f4672752SMarc Zyngier * Derived from arch/arm/kvm/reset.c 7f4672752SMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8f4672752SMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9f4672752SMarc Zyngier */ 10f4672752SMarc Zyngier 11f4672752SMarc Zyngier #include <linux/errno.h> 129a3cdf26SDave Martin #include <linux/kernel.h> 13f4672752SMarc Zyngier #include <linux/kvm_host.h> 14f4672752SMarc Zyngier #include <linux/kvm.h> 15834bf887SAlex Bennée #include <linux/hw_breakpoint.h> 169033bba4SDave Martin #include <linux/slab.h> 179a3cdf26SDave Martin #include <linux/string.h> 189033bba4SDave Martin #include <linux/types.h> 19f4672752SMarc Zyngier 20003300deSMarc Zyngier #include <kvm/arm_arch_timer.h> 21003300deSMarc Zyngier 227665f3a8SSuzuki K Poulose #include <asm/cpufeature.h> 23f4672752SMarc Zyngier #include <asm/cputype.h> 249033bba4SDave Martin #include <asm/fpsimd.h> 25f4672752SMarc Zyngier #include <asm/ptrace.h> 26f4672752SMarc Zyngier #include <asm/kvm_arm.h> 2767f69197SAKASHI Takahiro #include <asm/kvm_asm.h> 28358b28f0SMarc Zyngier #include <asm/kvm_emulate.h> 2967f69197SAKASHI Takahiro #include <asm/kvm_mmu.h> 309a3cdf26SDave Martin #include <asm/virt.h> 31f4672752SMarc Zyngier 320f62f0e9SSuzuki K Poulose /* Maximum phys_shift supported for any VM on this host */ 330f62f0e9SSuzuki K Poulose static u32 kvm_ipa_limit; 340f62f0e9SSuzuki K Poulose 35f4672752SMarc Zyngier /* 36f4672752SMarc Zyngier * ARMv8 Reset Values 37f4672752SMarc Zyngier */ 38349c330cSMarc Zyngier #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ 39349c330cSMarc Zyngier PSR_F_BIT | PSR_D_BIT) 40f4672752SMarc Zyngier 41349c330cSMarc Zyngier #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ 42349c330cSMarc Zyngier PSR_AA32_I_BIT | PSR_AA32_F_BIT) 430d854a60SMarc Zyngier 449033bba4SDave Martin unsigned int kvm_sve_max_vl; 459033bba4SDave Martin 46a3be836dSDave Martin int kvm_arm_init_sve(void) 479033bba4SDave Martin { 489033bba4SDave Martin if (system_supports_sve()) { 499033bba4SDave Martin kvm_sve_max_vl = sve_max_virtualisable_vl; 509033bba4SDave Martin 519033bba4SDave Martin /* 529033bba4SDave Martin * The get_sve_reg()/set_sve_reg() ioctl interface will need 539033bba4SDave Martin * to be extended with multiple register slice support in 549033bba4SDave Martin * order to support vector lengths greater than 559033bba4SDave Martin * SVE_VL_ARCH_MAX: 569033bba4SDave Martin */ 579033bba4SDave Martin if (WARN_ON(kvm_sve_max_vl > SVE_VL_ARCH_MAX)) 589033bba4SDave Martin kvm_sve_max_vl = SVE_VL_ARCH_MAX; 599033bba4SDave Martin 609033bba4SDave Martin /* 619033bba4SDave Martin * Don't even try to make use of vector lengths that 629033bba4SDave Martin * aren't available on all CPUs, for now: 639033bba4SDave Martin */ 649033bba4SDave Martin if (kvm_sve_max_vl < sve_max_vl) 659033bba4SDave Martin pr_warn("KVM: SVE vector length for guests limited to %u bytes\n", 669033bba4SDave Martin kvm_sve_max_vl); 679033bba4SDave Martin } 689033bba4SDave Martin 699033bba4SDave Martin return 0; 709033bba4SDave Martin } 719033bba4SDave Martin 729a3cdf26SDave Martin static int kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu) 739a3cdf26SDave Martin { 749a3cdf26SDave Martin if (!system_supports_sve()) 759a3cdf26SDave Martin return -EINVAL; 769a3cdf26SDave Martin 779a3cdf26SDave Martin vcpu->arch.sve_max_vl = kvm_sve_max_vl; 789a3cdf26SDave Martin 799a3cdf26SDave Martin /* 809a3cdf26SDave Martin * Userspace can still customize the vector lengths by writing 819a3cdf26SDave Martin * KVM_REG_ARM64_SVE_VLS. Allocation is deferred until 829a3cdf26SDave Martin * kvm_arm_vcpu_finalize(), which freezes the configuration. 839a3cdf26SDave Martin */ 849a3cdf26SDave Martin vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE; 859a3cdf26SDave Martin 869a3cdf26SDave Martin return 0; 879a3cdf26SDave Martin } 889a3cdf26SDave Martin 899033bba4SDave Martin /* 909033bba4SDave Martin * Finalize vcpu's maximum SVE vector length, allocating 919033bba4SDave Martin * vcpu->arch.sve_state as necessary. 929033bba4SDave Martin */ 939033bba4SDave Martin static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu) 949033bba4SDave Martin { 959033bba4SDave Martin void *buf; 969033bba4SDave Martin unsigned int vl; 979033bba4SDave Martin 989033bba4SDave Martin vl = vcpu->arch.sve_max_vl; 999033bba4SDave Martin 1009033bba4SDave Martin /* 101656012c7SFuad Tabba * Responsibility for these properties is shared between 1029033bba4SDave Martin * kvm_arm_init_arch_resources(), kvm_vcpu_enable_sve() and 1039033bba4SDave Martin * set_sve_vls(). Double-check here just to be sure: 1049033bba4SDave Martin */ 1059033bba4SDave Martin if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl || 1069033bba4SDave Martin vl > SVE_VL_ARCH_MAX)) 1079033bba4SDave Martin return -EIO; 1089033bba4SDave Martin 1099033bba4SDave Martin buf = kzalloc(SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl)), GFP_KERNEL); 1109033bba4SDave Martin if (!buf) 1119033bba4SDave Martin return -ENOMEM; 1129033bba4SDave Martin 1139033bba4SDave Martin vcpu->arch.sve_state = buf; 1149033bba4SDave Martin vcpu->arch.flags |= KVM_ARM64_VCPU_SVE_FINALIZED; 1159033bba4SDave Martin return 0; 1169033bba4SDave Martin } 1179033bba4SDave Martin 11892e68b2bSDave Martin int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature) 1199033bba4SDave Martin { 12092e68b2bSDave Martin switch (feature) { 1219033bba4SDave Martin case KVM_ARM_VCPU_SVE: 1229033bba4SDave Martin if (!vcpu_has_sve(vcpu)) 1239033bba4SDave Martin return -EINVAL; 1249033bba4SDave Martin 1259033bba4SDave Martin if (kvm_arm_vcpu_sve_finalized(vcpu)) 1269033bba4SDave Martin return -EPERM; 1279033bba4SDave Martin 1289033bba4SDave Martin return kvm_vcpu_finalize_sve(vcpu); 1299033bba4SDave Martin } 1309033bba4SDave Martin 1319033bba4SDave Martin return -EINVAL; 1329033bba4SDave Martin } 1339033bba4SDave Martin 1349033bba4SDave Martin bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu) 1359033bba4SDave Martin { 1369033bba4SDave Martin if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu)) 1379033bba4SDave Martin return false; 1389033bba4SDave Martin 1399033bba4SDave Martin return true; 1409033bba4SDave Martin } 1419033bba4SDave Martin 14219bcc89eSSean Christopherson void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) 14319bcc89eSSean Christopherson { 1449033bba4SDave Martin kfree(vcpu->arch.sve_state); 1459033bba4SDave Martin } 1469033bba4SDave Martin 1479a3cdf26SDave Martin static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) 1489a3cdf26SDave Martin { 1499a3cdf26SDave Martin if (vcpu_has_sve(vcpu)) 1509a3cdf26SDave Martin memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu)); 1519a3cdf26SDave Martin } 1529a3cdf26SDave Martin 153a22fa321SAmit Daniel Kachhap static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu) 154a22fa321SAmit Daniel Kachhap { 155a22fa321SAmit Daniel Kachhap /* 156a22fa321SAmit Daniel Kachhap * For now make sure that both address/generic pointer authentication 157aff7cce0SMarc Zyngier * features are requested by the userspace together and the system 158aff7cce0SMarc Zyngier * supports these capabilities. 159a22fa321SAmit Daniel Kachhap */ 160a22fa321SAmit Daniel Kachhap if (!test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) || 161aff7cce0SMarc Zyngier !test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features) || 162aff7cce0SMarc Zyngier !system_has_full_ptr_auth()) 163a22fa321SAmit Daniel Kachhap return -EINVAL; 164a22fa321SAmit Daniel Kachhap 165a22fa321SAmit Daniel Kachhap vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_PTRAUTH; 166a22fa321SAmit Daniel Kachhap return 0; 167a22fa321SAmit Daniel Kachhap } 168a22fa321SAmit Daniel Kachhap 169*66e94d5cSMarc Zyngier static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) 170*66e94d5cSMarc Zyngier { 171*66e94d5cSMarc Zyngier struct kvm_vcpu *tmp; 172*66e94d5cSMarc Zyngier bool is32bit; 173*66e94d5cSMarc Zyngier int i; 174*66e94d5cSMarc Zyngier 175*66e94d5cSMarc Zyngier is32bit = vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT); 176*66e94d5cSMarc Zyngier if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit) 177*66e94d5cSMarc Zyngier return false; 178*66e94d5cSMarc Zyngier 179*66e94d5cSMarc Zyngier /* Check that the vcpus are either all 32bit or all 64bit */ 180*66e94d5cSMarc Zyngier kvm_for_each_vcpu(i, tmp, vcpu->kvm) { 181*66e94d5cSMarc Zyngier if (vcpu_has_feature(tmp, KVM_ARM_VCPU_EL1_32BIT) != is32bit) 182*66e94d5cSMarc Zyngier return false; 183*66e94d5cSMarc Zyngier } 184*66e94d5cSMarc Zyngier 185*66e94d5cSMarc Zyngier return true; 186*66e94d5cSMarc Zyngier } 187*66e94d5cSMarc Zyngier 188f4672752SMarc Zyngier /** 189f4672752SMarc Zyngier * kvm_reset_vcpu - sets core registers and sys_regs to reset value 190f4672752SMarc Zyngier * @vcpu: The VCPU pointer 191f4672752SMarc Zyngier * 192f4672752SMarc Zyngier * This function finds the right table above and sets the registers on 193edce2292SAndrea Gelmini * the virtual CPU struct to their architecturally defined reset 1949a3cdf26SDave Martin * values, except for registers whose reset is deferred until 1959a3cdf26SDave Martin * kvm_arm_vcpu_finalize(). 196e761a927SChristoffer Dall * 197e761a927SChristoffer Dall * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT 198e761a927SChristoffer Dall * ioctl or as part of handling a request issued by another VCPU in the PSCI 199e761a927SChristoffer Dall * handling code. In the first case, the VCPU will not be loaded, and in the 200e761a927SChristoffer Dall * second case the VCPU will be loaded. Because this function operates purely 201656012c7SFuad Tabba * on the memory-backed values of system registers, we want to do a full put if 202e761a927SChristoffer Dall * we were loaded (handling a request) and load the values back at the end of 203e761a927SChristoffer Dall * the function. Otherwise we leave the state alone. In both cases, we 204e761a927SChristoffer Dall * disable preemption around the vcpu reset as we would otherwise race with 205e761a927SChristoffer Dall * preempt notifiers which also call put/load. 206f4672752SMarc Zyngier */ 207f4672752SMarc Zyngier int kvm_reset_vcpu(struct kvm_vcpu *vcpu) 208f4672752SMarc Zyngier { 20966b7e05dSSteven Price int ret; 210e761a927SChristoffer Dall bool loaded; 211349c330cSMarc Zyngier u32 pstate; 212e761a927SChristoffer Dall 213ebff0b0eSMarc Zyngier /* Reset PMU outside of the non-preemptible section */ 214ebff0b0eSMarc Zyngier kvm_pmu_vcpu_reset(vcpu); 215ebff0b0eSMarc Zyngier 216e761a927SChristoffer Dall preempt_disable(); 217e761a927SChristoffer Dall loaded = (vcpu->cpu != -1); 218e761a927SChristoffer Dall if (loaded) 219e761a927SChristoffer Dall kvm_arch_vcpu_put(vcpu); 220f4672752SMarc Zyngier 2219a3cdf26SDave Martin if (!kvm_arm_vcpu_sve_finalized(vcpu)) { 2229a3cdf26SDave Martin if (test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) { 2239a3cdf26SDave Martin ret = kvm_vcpu_enable_sve(vcpu); 2249a3cdf26SDave Martin if (ret) 2259a3cdf26SDave Martin goto out; 2269a3cdf26SDave Martin } 2279a3cdf26SDave Martin } else { 2289a3cdf26SDave Martin kvm_vcpu_reset_sve(vcpu); 2299a3cdf26SDave Martin } 2309a3cdf26SDave Martin 231a22fa321SAmit Daniel Kachhap if (test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) || 232a22fa321SAmit Daniel Kachhap test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features)) { 23366b7e05dSSteven Price if (kvm_vcpu_enable_ptrauth(vcpu)) { 23466b7e05dSSteven Price ret = -EINVAL; 235a22fa321SAmit Daniel Kachhap goto out; 236a22fa321SAmit Daniel Kachhap } 23766b7e05dSSteven Price } 238a22fa321SAmit Daniel Kachhap 239*66e94d5cSMarc Zyngier if (!vcpu_allowed_register_width(vcpu)) { 24066b7e05dSSteven Price ret = -EINVAL; 241e761a927SChristoffer Dall goto out; 24266b7e05dSSteven Price } 243*66e94d5cSMarc Zyngier 244*66e94d5cSMarc Zyngier switch (vcpu->arch.target) { 245*66e94d5cSMarc Zyngier default: 246*66e94d5cSMarc Zyngier if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) { 247349c330cSMarc Zyngier pstate = VCPU_RESET_PSTATE_SVC; 2480d854a60SMarc Zyngier } else { 249349c330cSMarc Zyngier pstate = VCPU_RESET_PSTATE_EL1; 2500d854a60SMarc Zyngier } 2510d854a60SMarc Zyngier 25277da4303SMarc Zyngier if (kvm_vcpu_has_pmu(vcpu) && !kvm_arm_support_pmu_v3()) { 25377da4303SMarc Zyngier ret = -EINVAL; 25477da4303SMarc Zyngier goto out; 25577da4303SMarc Zyngier } 256f4672752SMarc Zyngier break; 257f4672752SMarc Zyngier } 258f4672752SMarc Zyngier 259f4672752SMarc Zyngier /* Reset core registers */ 260349c330cSMarc Zyngier memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu))); 26185d70374SMarc Zyngier memset(&vcpu->arch.ctxt.fp_regs, 0, sizeof(vcpu->arch.ctxt.fp_regs)); 26285d70374SMarc Zyngier vcpu->arch.ctxt.spsr_abt = 0; 26385d70374SMarc Zyngier vcpu->arch.ctxt.spsr_und = 0; 26485d70374SMarc Zyngier vcpu->arch.ctxt.spsr_irq = 0; 26585d70374SMarc Zyngier vcpu->arch.ctxt.spsr_fiq = 0; 266e47c2055SMarc Zyngier vcpu_gp_regs(vcpu)->pstate = pstate; 267f4672752SMarc Zyngier 268f4672752SMarc Zyngier /* Reset system registers */ 269f4672752SMarc Zyngier kvm_reset_sys_regs(vcpu); 270f4672752SMarc Zyngier 271358b28f0SMarc Zyngier /* 272358b28f0SMarc Zyngier * Additional reset state handling that PSCI may have imposed on us. 273358b28f0SMarc Zyngier * Must be done after all the sys_reg reset. 274358b28f0SMarc Zyngier */ 275358b28f0SMarc Zyngier if (vcpu->arch.reset_state.reset) { 276358b28f0SMarc Zyngier unsigned long target_pc = vcpu->arch.reset_state.pc; 277358b28f0SMarc Zyngier 278358b28f0SMarc Zyngier /* Gracefully handle Thumb2 entry point */ 279358b28f0SMarc Zyngier if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) { 280358b28f0SMarc Zyngier target_pc &= ~1UL; 281358b28f0SMarc Zyngier vcpu_set_thumb(vcpu); 282358b28f0SMarc Zyngier } 283358b28f0SMarc Zyngier 284358b28f0SMarc Zyngier /* Propagate caller endianness */ 285358b28f0SMarc Zyngier if (vcpu->arch.reset_state.be) 286358b28f0SMarc Zyngier kvm_vcpu_set_be(vcpu); 287358b28f0SMarc Zyngier 288358b28f0SMarc Zyngier *vcpu_pc(vcpu) = target_pc; 289358b28f0SMarc Zyngier vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0); 290358b28f0SMarc Zyngier 291358b28f0SMarc Zyngier vcpu->arch.reset_state.reset = false; 292358b28f0SMarc Zyngier } 293358b28f0SMarc Zyngier 294003300deSMarc Zyngier /* Reset timer */ 295e761a927SChristoffer Dall ret = kvm_timer_vcpu_reset(vcpu); 296e761a927SChristoffer Dall out: 297e761a927SChristoffer Dall if (loaded) 298e761a927SChristoffer Dall kvm_arch_vcpu_load(vcpu, smp_processor_id()); 299e761a927SChristoffer Dall preempt_enable(); 300e761a927SChristoffer Dall return ret; 301f4672752SMarc Zyngier } 3025b6c6742SSuzuki K Poulose 303c73433fcSAnshuman Khandual u32 get_kvm_ipa_limit(void) 304c73433fcSAnshuman Khandual { 305c73433fcSAnshuman Khandual return kvm_ipa_limit; 306c73433fcSAnshuman Khandual } 307c73433fcSAnshuman Khandual 308b130a8f7SMarc Zyngier int kvm_set_ipa_limit(void) 3090f62f0e9SSuzuki K Poulose { 310c9b69a0cSWill Deacon unsigned int parange, tgran_2; 311f73531f0SAnshuman Khandual u64 mmfr0; 3120f62f0e9SSuzuki K Poulose 313f73531f0SAnshuman Khandual mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 314f73531f0SAnshuman Khandual parange = cpuid_feature_extract_unsigned_field(mmfr0, 315f73531f0SAnshuman Khandual ID_AA64MMFR0_PARANGE_SHIFT); 316b130a8f7SMarc Zyngier 317b130a8f7SMarc Zyngier /* 318b130a8f7SMarc Zyngier * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at 319b130a8f7SMarc Zyngier * Stage-2. If not, things will stop very quickly. 320b130a8f7SMarc Zyngier */ 321b130a8f7SMarc Zyngier switch (PAGE_SIZE) { 322b130a8f7SMarc Zyngier default: 323b130a8f7SMarc Zyngier case SZ_4K: 324b130a8f7SMarc Zyngier tgran_2 = ID_AA64MMFR0_TGRAN4_2_SHIFT; 325b130a8f7SMarc Zyngier break; 326b130a8f7SMarc Zyngier case SZ_16K: 327b130a8f7SMarc Zyngier tgran_2 = ID_AA64MMFR0_TGRAN16_2_SHIFT; 328b130a8f7SMarc Zyngier break; 329b130a8f7SMarc Zyngier case SZ_64K: 330b130a8f7SMarc Zyngier tgran_2 = ID_AA64MMFR0_TGRAN64_2_SHIFT; 331b130a8f7SMarc Zyngier break; 332b130a8f7SMarc Zyngier } 333b130a8f7SMarc Zyngier 334b130a8f7SMarc Zyngier switch (cpuid_feature_extract_unsigned_field(mmfr0, tgran_2)) { 33526f55386SJames Morse case ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE: 336b130a8f7SMarc Zyngier kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n"); 337b130a8f7SMarc Zyngier return -EINVAL; 33826f55386SJames Morse case ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT: 339b130a8f7SMarc Zyngier kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n"); 340b130a8f7SMarc Zyngier break; 34126f55386SJames Morse case ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX: 342b130a8f7SMarc Zyngier kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n"); 343b130a8f7SMarc Zyngier break; 34426f55386SJames Morse default: 34526f55386SJames Morse kvm_err("Unsupported value for TGRAN_2, giving up\n"); 34626f55386SJames Morse return -EINVAL; 347b130a8f7SMarc Zyngier } 348b130a8f7SMarc Zyngier 349c9b69a0cSWill Deacon kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange); 3507d717558SMarc Zyngier kvm_info("IPA Size Limit: %d bits%s\n", kvm_ipa_limit, 3517d717558SMarc Zyngier ((kvm_ipa_limit < KVM_PHYS_SHIFT) ? 3527d717558SMarc Zyngier " (Reduced IPA size, limited VM/VMM compatibility)" : "")); 353b130a8f7SMarc Zyngier 354b130a8f7SMarc Zyngier return 0; 3550f62f0e9SSuzuki K Poulose } 3560f62f0e9SSuzuki K Poulose 357bca607ebSMarc Zyngier int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type) 3585b6c6742SSuzuki K Poulose { 359bcb25a2bSQuentin Perret u64 mmfr0, mmfr1; 360bcb25a2bSQuentin Perret u32 phys_shift; 3617665f3a8SSuzuki K Poulose 362233a7cb2SSuzuki K Poulose if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK) 3635b6c6742SSuzuki K Poulose return -EINVAL; 3647665f3a8SSuzuki K Poulose 365233a7cb2SSuzuki K Poulose phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type); 366233a7cb2SSuzuki K Poulose if (phys_shift) { 367233a7cb2SSuzuki K Poulose if (phys_shift > kvm_ipa_limit || 368233a7cb2SSuzuki K Poulose phys_shift < 32) 369233a7cb2SSuzuki K Poulose return -EINVAL; 370233a7cb2SSuzuki K Poulose } else { 371233a7cb2SSuzuki K Poulose phys_shift = KVM_PHYS_SHIFT; 3727d717558SMarc Zyngier if (phys_shift > kvm_ipa_limit) { 3737d717558SMarc Zyngier pr_warn_once("%s using unsupported default IPA limit, upgrade your VMM\n", 3747d717558SMarc Zyngier current->comm); 3757d717558SMarc Zyngier return -EINVAL; 3767d717558SMarc Zyngier } 377233a7cb2SSuzuki K Poulose } 378233a7cb2SSuzuki K Poulose 379f73531f0SAnshuman Khandual mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 380bcb25a2bSQuentin Perret mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 381bcb25a2bSQuentin Perret kvm->arch.vtcr = kvm_get_vtcr(mmfr0, mmfr1, phys_shift); 3827665f3a8SSuzuki K Poulose 3835b6c6742SSuzuki K Poulose return 0; 3845b6c6742SSuzuki K Poulose } 385