1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2f4672752SMarc Zyngier /* 3f4672752SMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 4f4672752SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 5f4672752SMarc Zyngier * 6f4672752SMarc Zyngier * Derived from arch/arm/kvm/reset.c 7f4672752SMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8f4672752SMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9f4672752SMarc Zyngier */ 10f4672752SMarc Zyngier 11f4672752SMarc Zyngier #include <linux/errno.h> 129a3cdf26SDave Martin #include <linux/kernel.h> 13f4672752SMarc Zyngier #include <linux/kvm_host.h> 14f4672752SMarc Zyngier #include <linux/kvm.h> 15834bf887SAlex Bennée #include <linux/hw_breakpoint.h> 169033bba4SDave Martin #include <linux/slab.h> 179a3cdf26SDave Martin #include <linux/string.h> 189033bba4SDave Martin #include <linux/types.h> 19f4672752SMarc Zyngier 20003300deSMarc Zyngier #include <kvm/arm_arch_timer.h> 21003300deSMarc Zyngier 227665f3a8SSuzuki K Poulose #include <asm/cpufeature.h> 23f4672752SMarc Zyngier #include <asm/cputype.h> 249033bba4SDave Martin #include <asm/fpsimd.h> 25f4672752SMarc Zyngier #include <asm/ptrace.h> 26f4672752SMarc Zyngier #include <asm/kvm_arm.h> 2767f69197SAKASHI Takahiro #include <asm/kvm_asm.h> 28358b28f0SMarc Zyngier #include <asm/kvm_emulate.h> 2967f69197SAKASHI Takahiro #include <asm/kvm_mmu.h> 309a3cdf26SDave Martin #include <asm/virt.h> 31f4672752SMarc Zyngier 320f62f0e9SSuzuki K Poulose /* Maximum phys_shift supported for any VM on this host */ 330f62f0e9SSuzuki K Poulose static u32 kvm_ipa_limit; 340f62f0e9SSuzuki K Poulose 35f4672752SMarc Zyngier /* 36f4672752SMarc Zyngier * ARMv8 Reset Values 37f4672752SMarc Zyngier */ 38349c330cSMarc Zyngier #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ 39349c330cSMarc Zyngier PSR_F_BIT | PSR_D_BIT) 40f4672752SMarc Zyngier 41349c330cSMarc Zyngier #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ 42349c330cSMarc Zyngier PSR_AA32_I_BIT | PSR_AA32_F_BIT) 430d854a60SMarc Zyngier 449033bba4SDave Martin unsigned int kvm_sve_max_vl; 459033bba4SDave Martin 46a3be836dSDave Martin int kvm_arm_init_sve(void) 479033bba4SDave Martin { 489033bba4SDave Martin if (system_supports_sve()) { 49b5bc00ffSMark Brown kvm_sve_max_vl = sve_max_virtualisable_vl(); 509033bba4SDave Martin 519033bba4SDave Martin /* 529033bba4SDave Martin * The get_sve_reg()/set_sve_reg() ioctl interface will need 539033bba4SDave Martin * to be extended with multiple register slice support in 549033bba4SDave Martin * order to support vector lengths greater than 5530c43e73SMark Brown * VL_ARCH_MAX: 569033bba4SDave Martin */ 5730c43e73SMark Brown if (WARN_ON(kvm_sve_max_vl > VL_ARCH_MAX)) 5830c43e73SMark Brown kvm_sve_max_vl = VL_ARCH_MAX; 599033bba4SDave Martin 609033bba4SDave Martin /* 619033bba4SDave Martin * Don't even try to make use of vector lengths that 629033bba4SDave Martin * aren't available on all CPUs, for now: 639033bba4SDave Martin */ 64b5bc00ffSMark Brown if (kvm_sve_max_vl < sve_max_vl()) 659033bba4SDave Martin pr_warn("KVM: SVE vector length for guests limited to %u bytes\n", 669033bba4SDave Martin kvm_sve_max_vl); 679033bba4SDave Martin } 689033bba4SDave Martin 699033bba4SDave Martin return 0; 709033bba4SDave Martin } 719033bba4SDave Martin 729a3cdf26SDave Martin static int kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu) 739a3cdf26SDave Martin { 749a3cdf26SDave Martin if (!system_supports_sve()) 759a3cdf26SDave Martin return -EINVAL; 769a3cdf26SDave Martin 779a3cdf26SDave Martin vcpu->arch.sve_max_vl = kvm_sve_max_vl; 789a3cdf26SDave Martin 799a3cdf26SDave Martin /* 809a3cdf26SDave Martin * Userspace can still customize the vector lengths by writing 819a3cdf26SDave Martin * KVM_REG_ARM64_SVE_VLS. Allocation is deferred until 829a3cdf26SDave Martin * kvm_arm_vcpu_finalize(), which freezes the configuration. 839a3cdf26SDave Martin */ 849a3cdf26SDave Martin vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE; 859a3cdf26SDave Martin 869a3cdf26SDave Martin return 0; 879a3cdf26SDave Martin } 889a3cdf26SDave Martin 899033bba4SDave Martin /* 909033bba4SDave Martin * Finalize vcpu's maximum SVE vector length, allocating 919033bba4SDave Martin * vcpu->arch.sve_state as necessary. 929033bba4SDave Martin */ 939033bba4SDave Martin static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu) 949033bba4SDave Martin { 959033bba4SDave Martin void *buf; 969033bba4SDave Martin unsigned int vl; 97bff01a61SMarc Zyngier size_t reg_sz; 98bff01a61SMarc Zyngier int ret; 999033bba4SDave Martin 1009033bba4SDave Martin vl = vcpu->arch.sve_max_vl; 1019033bba4SDave Martin 1029033bba4SDave Martin /* 103656012c7SFuad Tabba * Responsibility for these properties is shared between 104e938eddbSZenghui Yu * kvm_arm_init_sve(), kvm_vcpu_enable_sve() and 1059033bba4SDave Martin * set_sve_vls(). Double-check here just to be sure: 1069033bba4SDave Martin */ 107b5bc00ffSMark Brown if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl() || 10830c43e73SMark Brown vl > VL_ARCH_MAX)) 1099033bba4SDave Martin return -EIO; 1109033bba4SDave Martin 111bff01a61SMarc Zyngier reg_sz = vcpu_sve_state_size(vcpu); 112bff01a61SMarc Zyngier buf = kzalloc(reg_sz, GFP_KERNEL_ACCOUNT); 1139033bba4SDave Martin if (!buf) 1149033bba4SDave Martin return -ENOMEM; 1159033bba4SDave Martin 1163f868e14SQuentin Perret ret = kvm_share_hyp(buf, buf + reg_sz); 117bff01a61SMarc Zyngier if (ret) { 118bff01a61SMarc Zyngier kfree(buf); 119bff01a61SMarc Zyngier return ret; 120bff01a61SMarc Zyngier } 121bff01a61SMarc Zyngier 1229033bba4SDave Martin vcpu->arch.sve_state = buf; 1239033bba4SDave Martin vcpu->arch.flags |= KVM_ARM64_VCPU_SVE_FINALIZED; 1249033bba4SDave Martin return 0; 1259033bba4SDave Martin } 1269033bba4SDave Martin 12792e68b2bSDave Martin int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature) 1289033bba4SDave Martin { 12992e68b2bSDave Martin switch (feature) { 1309033bba4SDave Martin case KVM_ARM_VCPU_SVE: 1319033bba4SDave Martin if (!vcpu_has_sve(vcpu)) 1329033bba4SDave Martin return -EINVAL; 1339033bba4SDave Martin 1349033bba4SDave Martin if (kvm_arm_vcpu_sve_finalized(vcpu)) 1359033bba4SDave Martin return -EPERM; 1369033bba4SDave Martin 1379033bba4SDave Martin return kvm_vcpu_finalize_sve(vcpu); 1389033bba4SDave Martin } 1399033bba4SDave Martin 1409033bba4SDave Martin return -EINVAL; 1419033bba4SDave Martin } 1429033bba4SDave Martin 1439033bba4SDave Martin bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu) 1449033bba4SDave Martin { 1459033bba4SDave Martin if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu)) 1469033bba4SDave Martin return false; 1479033bba4SDave Martin 1489033bba4SDave Martin return true; 1499033bba4SDave Martin } 1509033bba4SDave Martin 15119bcc89eSSean Christopherson void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) 15219bcc89eSSean Christopherson { 15352b28657SQuentin Perret void *sve_state = vcpu->arch.sve_state; 15452b28657SQuentin Perret 15552b28657SQuentin Perret kvm_vcpu_unshare_task_fp(vcpu); 15652b28657SQuentin Perret kvm_unshare_hyp(vcpu, vcpu + 1); 15752b28657SQuentin Perret if (sve_state) 15852b28657SQuentin Perret kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu)); 15952b28657SQuentin Perret kfree(sve_state); 1609033bba4SDave Martin } 1619033bba4SDave Martin 1629a3cdf26SDave Martin static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) 1639a3cdf26SDave Martin { 1649a3cdf26SDave Martin if (vcpu_has_sve(vcpu)) 1659a3cdf26SDave Martin memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu)); 1669a3cdf26SDave Martin } 1679a3cdf26SDave Martin 168a22fa321SAmit Daniel Kachhap static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu) 169a22fa321SAmit Daniel Kachhap { 170a22fa321SAmit Daniel Kachhap /* 171a22fa321SAmit Daniel Kachhap * For now make sure that both address/generic pointer authentication 172aff7cce0SMarc Zyngier * features are requested by the userspace together and the system 173aff7cce0SMarc Zyngier * supports these capabilities. 174a22fa321SAmit Daniel Kachhap */ 175a22fa321SAmit Daniel Kachhap if (!test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) || 176aff7cce0SMarc Zyngier !test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features) || 177aff7cce0SMarc Zyngier !system_has_full_ptr_auth()) 178a22fa321SAmit Daniel Kachhap return -EINVAL; 179a22fa321SAmit Daniel Kachhap 180a22fa321SAmit Daniel Kachhap vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_PTRAUTH; 181a22fa321SAmit Daniel Kachhap return 0; 182a22fa321SAmit Daniel Kachhap } 183a22fa321SAmit Daniel Kachhap 184*26bf74bdSReiji Watanabe /** 185*26bf74bdSReiji Watanabe * kvm_set_vm_width() - set the register width for the guest 186*26bf74bdSReiji Watanabe * @vcpu: Pointer to the vcpu being configured 187*26bf74bdSReiji Watanabe * 188*26bf74bdSReiji Watanabe * Set both KVM_ARCH_FLAG_EL1_32BIT and KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED 189*26bf74bdSReiji Watanabe * in the VM flags based on the vcpu's requested register width, the HW 190*26bf74bdSReiji Watanabe * capabilities and other options (such as MTE). 191*26bf74bdSReiji Watanabe * When REG_WIDTH_CONFIGURED is already set, the vcpu settings must be 192*26bf74bdSReiji Watanabe * consistent with the value of the FLAG_EL1_32BIT bit in the flags. 193*26bf74bdSReiji Watanabe * 194*26bf74bdSReiji Watanabe * Return: 0 on success, negative error code on failure. 195*26bf74bdSReiji Watanabe */ 196*26bf74bdSReiji Watanabe static int kvm_set_vm_width(struct kvm_vcpu *vcpu) 19766e94d5cSMarc Zyngier { 198*26bf74bdSReiji Watanabe struct kvm *kvm = vcpu->kvm; 19966e94d5cSMarc Zyngier bool is32bit; 20066e94d5cSMarc Zyngier 20166e94d5cSMarc Zyngier is32bit = vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT); 20266e94d5cSMarc Zyngier 203*26bf74bdSReiji Watanabe lockdep_assert_held(&kvm->lock); 204673638f4SSteven Price 205*26bf74bdSReiji Watanabe if (test_bit(KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED, &kvm->arch.flags)) { 206*26bf74bdSReiji Watanabe /* 207*26bf74bdSReiji Watanabe * The guest's register width is already configured. 208*26bf74bdSReiji Watanabe * Make sure that the vcpu is consistent with it. 209*26bf74bdSReiji Watanabe */ 210*26bf74bdSReiji Watanabe if (is32bit == test_bit(KVM_ARCH_FLAG_EL1_32BIT, &kvm->arch.flags)) 211*26bf74bdSReiji Watanabe return 0; 212*26bf74bdSReiji Watanabe 213*26bf74bdSReiji Watanabe return -EINVAL; 21466e94d5cSMarc Zyngier } 21566e94d5cSMarc Zyngier 216*26bf74bdSReiji Watanabe if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit) 217*26bf74bdSReiji Watanabe return -EINVAL; 218*26bf74bdSReiji Watanabe 219*26bf74bdSReiji Watanabe /* MTE is incompatible with AArch32 */ 220*26bf74bdSReiji Watanabe if (kvm_has_mte(kvm) && is32bit) 221*26bf74bdSReiji Watanabe return -EINVAL; 222*26bf74bdSReiji Watanabe 223*26bf74bdSReiji Watanabe if (is32bit) 224*26bf74bdSReiji Watanabe set_bit(KVM_ARCH_FLAG_EL1_32BIT, &kvm->arch.flags); 225*26bf74bdSReiji Watanabe 226*26bf74bdSReiji Watanabe set_bit(KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED, &kvm->arch.flags); 227*26bf74bdSReiji Watanabe 228*26bf74bdSReiji Watanabe return 0; 22966e94d5cSMarc Zyngier } 23066e94d5cSMarc Zyngier 231f4672752SMarc Zyngier /** 232f4672752SMarc Zyngier * kvm_reset_vcpu - sets core registers and sys_regs to reset value 233f4672752SMarc Zyngier * @vcpu: The VCPU pointer 234f4672752SMarc Zyngier * 235a080e323SFuad Tabba * This function sets the registers on the virtual CPU struct to their 236a080e323SFuad Tabba * architecturally defined reset values, except for registers whose reset is 237a080e323SFuad Tabba * deferred until kvm_arm_vcpu_finalize(). 238e761a927SChristoffer Dall * 239e761a927SChristoffer Dall * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT 240e761a927SChristoffer Dall * ioctl or as part of handling a request issued by another VCPU in the PSCI 241e761a927SChristoffer Dall * handling code. In the first case, the VCPU will not be loaded, and in the 242e761a927SChristoffer Dall * second case the VCPU will be loaded. Because this function operates purely 243656012c7SFuad Tabba * on the memory-backed values of system registers, we want to do a full put if 244e761a927SChristoffer Dall * we were loaded (handling a request) and load the values back at the end of 245e761a927SChristoffer Dall * the function. Otherwise we leave the state alone. In both cases, we 246e761a927SChristoffer Dall * disable preemption around the vcpu reset as we would otherwise race with 247e761a927SChristoffer Dall * preempt notifiers which also call put/load. 248f4672752SMarc Zyngier */ 249f4672752SMarc Zyngier int kvm_reset_vcpu(struct kvm_vcpu *vcpu) 250f4672752SMarc Zyngier { 2516654f9dfSOliver Upton struct vcpu_reset_state reset_state; 25266b7e05dSSteven Price int ret; 253e761a927SChristoffer Dall bool loaded; 254349c330cSMarc Zyngier u32 pstate; 255e761a927SChristoffer Dall 2566654f9dfSOliver Upton mutex_lock(&vcpu->kvm->lock); 257*26bf74bdSReiji Watanabe ret = kvm_set_vm_width(vcpu); 258*26bf74bdSReiji Watanabe if (!ret) { 2596654f9dfSOliver Upton reset_state = vcpu->arch.reset_state; 2606654f9dfSOliver Upton WRITE_ONCE(vcpu->arch.reset_state.reset, false); 261*26bf74bdSReiji Watanabe } 2626654f9dfSOliver Upton mutex_unlock(&vcpu->kvm->lock); 2636654f9dfSOliver Upton 264*26bf74bdSReiji Watanabe if (ret) 265*26bf74bdSReiji Watanabe return ret; 266*26bf74bdSReiji Watanabe 267ebff0b0eSMarc Zyngier /* Reset PMU outside of the non-preemptible section */ 268ebff0b0eSMarc Zyngier kvm_pmu_vcpu_reset(vcpu); 269ebff0b0eSMarc Zyngier 270e761a927SChristoffer Dall preempt_disable(); 271e761a927SChristoffer Dall loaded = (vcpu->cpu != -1); 272e761a927SChristoffer Dall if (loaded) 273e761a927SChristoffer Dall kvm_arch_vcpu_put(vcpu); 274f4672752SMarc Zyngier 2759a3cdf26SDave Martin if (!kvm_arm_vcpu_sve_finalized(vcpu)) { 2769a3cdf26SDave Martin if (test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) { 2779a3cdf26SDave Martin ret = kvm_vcpu_enable_sve(vcpu); 2789a3cdf26SDave Martin if (ret) 2799a3cdf26SDave Martin goto out; 2809a3cdf26SDave Martin } 2819a3cdf26SDave Martin } else { 2829a3cdf26SDave Martin kvm_vcpu_reset_sve(vcpu); 2839a3cdf26SDave Martin } 2849a3cdf26SDave Martin 285a22fa321SAmit Daniel Kachhap if (test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) || 286a22fa321SAmit Daniel Kachhap test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features)) { 28766b7e05dSSteven Price if (kvm_vcpu_enable_ptrauth(vcpu)) { 28866b7e05dSSteven Price ret = -EINVAL; 289a22fa321SAmit Daniel Kachhap goto out; 290a22fa321SAmit Daniel Kachhap } 29166b7e05dSSteven Price } 292a22fa321SAmit Daniel Kachhap 29366e94d5cSMarc Zyngier switch (vcpu->arch.target) { 29466e94d5cSMarc Zyngier default: 295*26bf74bdSReiji Watanabe if (vcpu_el1_is_32bit(vcpu)) { 296349c330cSMarc Zyngier pstate = VCPU_RESET_PSTATE_SVC; 2970d854a60SMarc Zyngier } else { 298349c330cSMarc Zyngier pstate = VCPU_RESET_PSTATE_EL1; 2990d854a60SMarc Zyngier } 3000d854a60SMarc Zyngier 30177da4303SMarc Zyngier if (kvm_vcpu_has_pmu(vcpu) && !kvm_arm_support_pmu_v3()) { 30277da4303SMarc Zyngier ret = -EINVAL; 30377da4303SMarc Zyngier goto out; 30477da4303SMarc Zyngier } 305f4672752SMarc Zyngier break; 306f4672752SMarc Zyngier } 307f4672752SMarc Zyngier 308f4672752SMarc Zyngier /* Reset core registers */ 309349c330cSMarc Zyngier memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu))); 31085d70374SMarc Zyngier memset(&vcpu->arch.ctxt.fp_regs, 0, sizeof(vcpu->arch.ctxt.fp_regs)); 31185d70374SMarc Zyngier vcpu->arch.ctxt.spsr_abt = 0; 31285d70374SMarc Zyngier vcpu->arch.ctxt.spsr_und = 0; 31385d70374SMarc Zyngier vcpu->arch.ctxt.spsr_irq = 0; 31485d70374SMarc Zyngier vcpu->arch.ctxt.spsr_fiq = 0; 315e47c2055SMarc Zyngier vcpu_gp_regs(vcpu)->pstate = pstate; 316f4672752SMarc Zyngier 317f4672752SMarc Zyngier /* Reset system registers */ 318f4672752SMarc Zyngier kvm_reset_sys_regs(vcpu); 319f4672752SMarc Zyngier 320358b28f0SMarc Zyngier /* 321358b28f0SMarc Zyngier * Additional reset state handling that PSCI may have imposed on us. 322358b28f0SMarc Zyngier * Must be done after all the sys_reg reset. 323358b28f0SMarc Zyngier */ 3246654f9dfSOliver Upton if (reset_state.reset) { 3256654f9dfSOliver Upton unsigned long target_pc = reset_state.pc; 326358b28f0SMarc Zyngier 327358b28f0SMarc Zyngier /* Gracefully handle Thumb2 entry point */ 328358b28f0SMarc Zyngier if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) { 329358b28f0SMarc Zyngier target_pc &= ~1UL; 330358b28f0SMarc Zyngier vcpu_set_thumb(vcpu); 331358b28f0SMarc Zyngier } 332358b28f0SMarc Zyngier 333358b28f0SMarc Zyngier /* Propagate caller endianness */ 3346654f9dfSOliver Upton if (reset_state.be) 335358b28f0SMarc Zyngier kvm_vcpu_set_be(vcpu); 336358b28f0SMarc Zyngier 337358b28f0SMarc Zyngier *vcpu_pc(vcpu) = target_pc; 3386654f9dfSOliver Upton vcpu_set_reg(vcpu, 0, reset_state.r0); 339358b28f0SMarc Zyngier } 340358b28f0SMarc Zyngier 341003300deSMarc Zyngier /* Reset timer */ 342e761a927SChristoffer Dall ret = kvm_timer_vcpu_reset(vcpu); 343e761a927SChristoffer Dall out: 344e761a927SChristoffer Dall if (loaded) 345e761a927SChristoffer Dall kvm_arch_vcpu_load(vcpu, smp_processor_id()); 346e761a927SChristoffer Dall preempt_enable(); 347e761a927SChristoffer Dall return ret; 348f4672752SMarc Zyngier } 3495b6c6742SSuzuki K Poulose 350c73433fcSAnshuman Khandual u32 get_kvm_ipa_limit(void) 351c73433fcSAnshuman Khandual { 352c73433fcSAnshuman Khandual return kvm_ipa_limit; 353c73433fcSAnshuman Khandual } 354c73433fcSAnshuman Khandual 355b130a8f7SMarc Zyngier int kvm_set_ipa_limit(void) 3560f62f0e9SSuzuki K Poulose { 357b31578f6SAnshuman Khandual unsigned int parange; 358f73531f0SAnshuman Khandual u64 mmfr0; 3590f62f0e9SSuzuki K Poulose 360f73531f0SAnshuman Khandual mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 361f73531f0SAnshuman Khandual parange = cpuid_feature_extract_unsigned_field(mmfr0, 362f73531f0SAnshuman Khandual ID_AA64MMFR0_PARANGE_SHIFT); 3635e5df957SAnshuman Khandual /* 3645e5df957SAnshuman Khandual * IPA size beyond 48 bits could not be supported 3655e5df957SAnshuman Khandual * on either 4K or 16K page size. Hence let's cap 3665e5df957SAnshuman Khandual * it to 48 bits, in case it's reported as larger 3675e5df957SAnshuman Khandual * on the system. 3685e5df957SAnshuman Khandual */ 3695e5df957SAnshuman Khandual if (PAGE_SIZE != SZ_64K) 3705e5df957SAnshuman Khandual parange = min(parange, (unsigned int)ID_AA64MMFR0_PARANGE_48); 371b130a8f7SMarc Zyngier 372b130a8f7SMarc Zyngier /* 373b130a8f7SMarc Zyngier * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at 374b130a8f7SMarc Zyngier * Stage-2. If not, things will stop very quickly. 375b130a8f7SMarc Zyngier */ 376b31578f6SAnshuman Khandual switch (cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_TGRAN_2_SHIFT)) { 37726f55386SJames Morse case ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE: 378b130a8f7SMarc Zyngier kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n"); 379b130a8f7SMarc Zyngier return -EINVAL; 38026f55386SJames Morse case ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT: 381b130a8f7SMarc Zyngier kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n"); 382b130a8f7SMarc Zyngier break; 38326f55386SJames Morse case ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX: 384b130a8f7SMarc Zyngier kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n"); 385b130a8f7SMarc Zyngier break; 38626f55386SJames Morse default: 38726f55386SJames Morse kvm_err("Unsupported value for TGRAN_2, giving up\n"); 38826f55386SJames Morse return -EINVAL; 389b130a8f7SMarc Zyngier } 390b130a8f7SMarc Zyngier 391c9b69a0cSWill Deacon kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange); 3927d717558SMarc Zyngier kvm_info("IPA Size Limit: %d bits%s\n", kvm_ipa_limit, 3937d717558SMarc Zyngier ((kvm_ipa_limit < KVM_PHYS_SHIFT) ? 3947d717558SMarc Zyngier " (Reduced IPA size, limited VM/VMM compatibility)" : "")); 395b130a8f7SMarc Zyngier 396b130a8f7SMarc Zyngier return 0; 3970f62f0e9SSuzuki K Poulose } 3980f62f0e9SSuzuki K Poulose 399bca607ebSMarc Zyngier int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type) 4005b6c6742SSuzuki K Poulose { 401bcb25a2bSQuentin Perret u64 mmfr0, mmfr1; 402bcb25a2bSQuentin Perret u32 phys_shift; 4037665f3a8SSuzuki K Poulose 404233a7cb2SSuzuki K Poulose if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK) 4055b6c6742SSuzuki K Poulose return -EINVAL; 4067665f3a8SSuzuki K Poulose 407233a7cb2SSuzuki K Poulose phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type); 408233a7cb2SSuzuki K Poulose if (phys_shift) { 409233a7cb2SSuzuki K Poulose if (phys_shift > kvm_ipa_limit || 4109788c140SAnshuman Khandual phys_shift < ARM64_MIN_PARANGE_BITS) 411233a7cb2SSuzuki K Poulose return -EINVAL; 412233a7cb2SSuzuki K Poulose } else { 413233a7cb2SSuzuki K Poulose phys_shift = KVM_PHYS_SHIFT; 4147d717558SMarc Zyngier if (phys_shift > kvm_ipa_limit) { 4157d717558SMarc Zyngier pr_warn_once("%s using unsupported default IPA limit, upgrade your VMM\n", 4167d717558SMarc Zyngier current->comm); 4177d717558SMarc Zyngier return -EINVAL; 4187d717558SMarc Zyngier } 419233a7cb2SSuzuki K Poulose } 420233a7cb2SSuzuki K Poulose 421f73531f0SAnshuman Khandual mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 422bcb25a2bSQuentin Perret mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 423bcb25a2bSQuentin Perret kvm->arch.vtcr = kvm_get_vtcr(mmfr0, mmfr1, phys_shift); 4247665f3a8SSuzuki K Poulose 4255b6c6742SSuzuki K Poulose return 0; 4265b6c6742SSuzuki K Poulose } 427