1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 9 #include <linux/arm-smccc.h> 10 #include <linux/kvm_host.h> 11 #include <linux/types.h> 12 #include <linux/jump_label.h> 13 #include <linux/percpu.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 #include <asm/thread_info.h> 29 #include <asm/vectors.h> 30 31 /* VHE specific context */ 32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 35 36 static void __activate_traps(struct kvm_vcpu *vcpu) 37 { 38 u64 val; 39 40 ___activate_traps(vcpu); 41 42 val = read_sysreg(cpacr_el1); 43 val |= CPACR_EL1_TTA; 44 val &= ~(CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN | 45 CPACR_EL1_SMEN_EL0EN | CPACR_EL1_SMEN_EL1EN); 46 47 /* 48 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to 49 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, 50 * except for some missing controls, such as TAM. 51 * In this case, CPTR_EL2.TAM has the same position with or without 52 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM 53 * shift value for trapping the AMU accesses. 54 */ 55 56 val |= CPTR_EL2_TAM; 57 58 if (guest_owns_fp_regs(vcpu)) { 59 if (vcpu_has_sve(vcpu)) 60 val |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN; 61 } else { 62 val &= ~(CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN); 63 __activate_traps_fpsimd32(vcpu); 64 } 65 66 if (cpus_have_final_cap(ARM64_SME)) 67 write_sysreg(read_sysreg(sctlr_el2) & ~SCTLR_ELx_ENTP2, 68 sctlr_el2); 69 70 write_sysreg(val, cpacr_el1); 71 72 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); 73 } 74 NOKPROBE_SYMBOL(__activate_traps); 75 76 static void __deactivate_traps(struct kvm_vcpu *vcpu) 77 { 78 const char *host_vectors = vectors; 79 80 ___deactivate_traps(vcpu); 81 82 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); 83 84 /* 85 * ARM errata 1165522 and 1530923 require the actual execution of the 86 * above before we can switch to the EL2/EL0 translation regime used by 87 * the host. 88 */ 89 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 90 91 if (cpus_have_final_cap(ARM64_SME)) 92 write_sysreg(read_sysreg(sctlr_el2) | SCTLR_ELx_ENTP2, 93 sctlr_el2); 94 95 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); 96 97 if (!arm64_kernel_unmapped_at_el0()) 98 host_vectors = __this_cpu_read(this_cpu_vector); 99 write_sysreg(host_vectors, vbar_el1); 100 } 101 NOKPROBE_SYMBOL(__deactivate_traps); 102 103 void activate_traps_vhe_load(struct kvm_vcpu *vcpu) 104 { 105 __activate_traps_common(vcpu); 106 } 107 108 void deactivate_traps_vhe_put(struct kvm_vcpu *vcpu) 109 { 110 __deactivate_traps_common(vcpu); 111 } 112 113 static const exit_handler_fn hyp_exit_handlers[] = { 114 [0 ... ESR_ELx_EC_MAX] = NULL, 115 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 116 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 117 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 118 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 119 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 120 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 121 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth, 122 }; 123 124 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 125 { 126 return hyp_exit_handlers; 127 } 128 129 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code) 130 { 131 } 132 133 /* Switch to the guest for VHE systems running in EL2 */ 134 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) 135 { 136 struct kvm_cpu_context *host_ctxt; 137 struct kvm_cpu_context *guest_ctxt; 138 u64 exit_code; 139 140 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 141 host_ctxt->__hyp_running_vcpu = vcpu; 142 guest_ctxt = &vcpu->arch.ctxt; 143 144 sysreg_save_host_state_vhe(host_ctxt); 145 146 /* 147 * ARM erratum 1165522 requires us to configure both stage 1 and 148 * stage 2 translation for the guest context before we clear 149 * HCR_EL2.TGE. 150 * 151 * We have already configured the guest's stage 1 translation in 152 * kvm_vcpu_load_sysregs_vhe above. We must now call 153 * __load_stage2 before __activate_traps, because 154 * __load_stage2 configures stage 2 translation, and 155 * __activate_traps clear HCR_EL2.TGE (among other things). 156 */ 157 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch); 158 __activate_traps(vcpu); 159 160 __kvm_adjust_pc(vcpu); 161 162 sysreg_restore_guest_state_vhe(guest_ctxt); 163 __debug_switch_to_guest(vcpu); 164 165 do { 166 /* Jump in the fire! */ 167 exit_code = __guest_enter(vcpu); 168 169 /* And we're baaack! */ 170 } while (fixup_guest_exit(vcpu, &exit_code)); 171 172 sysreg_save_guest_state_vhe(guest_ctxt); 173 174 __deactivate_traps(vcpu); 175 176 sysreg_restore_host_state_vhe(host_ctxt); 177 178 if (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED) 179 __fpsimd_save_fpexc32(vcpu); 180 181 __debug_switch_to_host(vcpu); 182 183 return exit_code; 184 } 185 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); 186 187 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 188 { 189 int ret; 190 191 local_daif_mask(); 192 193 /* 194 * Having IRQs masked via PMR when entering the guest means the GIC 195 * will not signal the CPU of interrupts of lower priority, and the 196 * only way to get out will be via guest exceptions. 197 * Naturally, we want to avoid this. 198 * 199 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a 200 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. 201 */ 202 pmr_sync(); 203 204 ret = __kvm_vcpu_run_vhe(vcpu); 205 206 /* 207 * local_daif_restore() takes care to properly restore PSTATE.DAIF 208 * and the GIC PMR if the host is using IRQ priorities. 209 */ 210 local_daif_restore(DAIF_PROCCTX_NOIRQ); 211 212 /* 213 * When we exit from the guest we change a number of CPU configuration 214 * parameters, such as traps. Make sure these changes take effect 215 * before running the host or additional guests. 216 */ 217 isb(); 218 219 return ret; 220 } 221 222 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par) 223 { 224 struct kvm_cpu_context *host_ctxt; 225 struct kvm_vcpu *vcpu; 226 227 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 228 vcpu = host_ctxt->__hyp_running_vcpu; 229 230 __deactivate_traps(vcpu); 231 sysreg_restore_host_state_vhe(host_ctxt); 232 233 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n", 234 spsr, elr, 235 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), 236 read_sysreg(hpfar_el2), par, vcpu); 237 } 238 NOKPROBE_SYMBOL(__hyp_call_panic); 239 240 void __noreturn hyp_panic(void) 241 { 242 u64 spsr = read_sysreg_el2(SYS_SPSR); 243 u64 elr = read_sysreg_el2(SYS_ELR); 244 u64 par = read_sysreg_par(); 245 246 __hyp_call_panic(spsr, elr, par); 247 unreachable(); 248 } 249 250 asmlinkage void kvm_unexpected_el2_exception(void) 251 { 252 __kvm_unexpected_el2_exception(); 253 } 254