1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/adjust_pc.h> 8 #include <hyp/switch.h> 9 10 #include <linux/arm-smccc.h> 11 #include <linux/kvm_host.h> 12 #include <linux/types.h> 13 #include <linux/jump_label.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 #include <asm/thread_info.h> 29 30 const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n"; 31 32 /* VHE specific context */ 33 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 34 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 35 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 36 37 static void __activate_traps(struct kvm_vcpu *vcpu) 38 { 39 u64 val; 40 41 ___activate_traps(vcpu); 42 43 val = read_sysreg(cpacr_el1); 44 val |= CPACR_EL1_TTA; 45 val &= ~CPACR_EL1_ZEN; 46 47 /* 48 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to 49 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, 50 * except for some missing controls, such as TAM. 51 * In this case, CPTR_EL2.TAM has the same position with or without 52 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM 53 * shift value for trapping the AMU accesses. 54 */ 55 56 val |= CPTR_EL2_TAM; 57 58 if (update_fp_enabled(vcpu)) { 59 if (vcpu_has_sve(vcpu)) 60 val |= CPACR_EL1_ZEN; 61 } else { 62 val &= ~CPACR_EL1_FPEN; 63 __activate_traps_fpsimd32(vcpu); 64 } 65 66 write_sysreg(val, cpacr_el1); 67 68 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); 69 } 70 NOKPROBE_SYMBOL(__activate_traps); 71 72 static void __deactivate_traps(struct kvm_vcpu *vcpu) 73 { 74 extern char vectors[]; /* kernel exception vectors */ 75 76 ___deactivate_traps(vcpu); 77 78 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); 79 80 /* 81 * ARM errata 1165522 and 1530923 require the actual execution of the 82 * above before we can switch to the EL2/EL0 translation regime used by 83 * the host. 84 */ 85 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 86 87 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); 88 write_sysreg(vectors, vbar_el1); 89 } 90 NOKPROBE_SYMBOL(__deactivate_traps); 91 92 void activate_traps_vhe_load(struct kvm_vcpu *vcpu) 93 { 94 __activate_traps_common(vcpu); 95 } 96 97 void deactivate_traps_vhe_put(void) 98 { 99 u64 mdcr_el2 = read_sysreg(mdcr_el2); 100 101 mdcr_el2 &= MDCR_EL2_HPMN_MASK | 102 MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT | 103 MDCR_EL2_TPMS; 104 105 write_sysreg(mdcr_el2, mdcr_el2); 106 107 __deactivate_traps_common(); 108 } 109 110 /* Switch to the guest for VHE systems running in EL2 */ 111 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) 112 { 113 struct kvm_cpu_context *host_ctxt; 114 struct kvm_cpu_context *guest_ctxt; 115 u64 exit_code; 116 117 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 118 host_ctxt->__hyp_running_vcpu = vcpu; 119 guest_ctxt = &vcpu->arch.ctxt; 120 121 sysreg_save_host_state_vhe(host_ctxt); 122 123 /* 124 * ARM erratum 1165522 requires us to configure both stage 1 and 125 * stage 2 translation for the guest context before we clear 126 * HCR_EL2.TGE. 127 * 128 * We have already configured the guest's stage 1 translation in 129 * kvm_vcpu_load_sysregs_vhe above. We must now call 130 * __load_guest_stage2 before __activate_traps, because 131 * __load_guest_stage2 configures stage 2 translation, and 132 * __activate_traps clear HCR_EL2.TGE (among other things). 133 */ 134 __load_guest_stage2(vcpu->arch.hw_mmu); 135 __activate_traps(vcpu); 136 137 __adjust_pc(vcpu); 138 139 sysreg_restore_guest_state_vhe(guest_ctxt); 140 __debug_switch_to_guest(vcpu); 141 142 do { 143 /* Jump in the fire! */ 144 exit_code = __guest_enter(vcpu); 145 146 /* And we're baaack! */ 147 } while (fixup_guest_exit(vcpu, &exit_code)); 148 149 sysreg_save_guest_state_vhe(guest_ctxt); 150 151 __deactivate_traps(vcpu); 152 153 sysreg_restore_host_state_vhe(host_ctxt); 154 155 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) 156 __fpsimd_save_fpexc32(vcpu); 157 158 __debug_switch_to_host(vcpu); 159 160 return exit_code; 161 } 162 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); 163 164 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 165 { 166 int ret; 167 168 local_daif_mask(); 169 170 /* 171 * Having IRQs masked via PMR when entering the guest means the GIC 172 * will not signal the CPU of interrupts of lower priority, and the 173 * only way to get out will be via guest exceptions. 174 * Naturally, we want to avoid this. 175 * 176 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a 177 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. 178 */ 179 pmr_sync(); 180 181 ret = __kvm_vcpu_run_vhe(vcpu); 182 183 /* 184 * local_daif_restore() takes care to properly restore PSTATE.DAIF 185 * and the GIC PMR if the host is using IRQ priorities. 186 */ 187 local_daif_restore(DAIF_PROCCTX_NOIRQ); 188 189 /* 190 * When we exit from the guest we change a number of CPU configuration 191 * parameters, such as traps. Make sure these changes take effect 192 * before running the host or additional guests. 193 */ 194 isb(); 195 196 return ret; 197 } 198 199 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par) 200 { 201 struct kvm_cpu_context *host_ctxt; 202 struct kvm_vcpu *vcpu; 203 204 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 205 vcpu = host_ctxt->__hyp_running_vcpu; 206 207 __deactivate_traps(vcpu); 208 sysreg_restore_host_state_vhe(host_ctxt); 209 210 panic(__hyp_panic_string, 211 spsr, elr, 212 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), 213 read_sysreg(hpfar_el2), par, vcpu); 214 } 215 NOKPROBE_SYMBOL(__hyp_call_panic); 216 217 void __noreturn hyp_panic(void) 218 { 219 u64 spsr = read_sysreg_el2(SYS_SPSR); 220 u64 elr = read_sysreg_el2(SYS_ELR); 221 u64 par = read_sysreg_par(); 222 223 __hyp_call_panic(spsr, elr, par); 224 unreachable(); 225 } 226 227 asmlinkage void kvm_unexpected_el2_exception(void) 228 { 229 return __kvm_unexpected_el2_exception(); 230 } 231