1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/adjust_pc.h> 8 #include <hyp/switch.h> 9 10 #include <linux/arm-smccc.h> 11 #include <linux/kvm_host.h> 12 #include <linux/types.h> 13 #include <linux/jump_label.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 #include <asm/thread_info.h> 29 30 /* VHE specific context */ 31 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 32 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 33 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 34 35 static void __activate_traps(struct kvm_vcpu *vcpu) 36 { 37 u64 val; 38 39 ___activate_traps(vcpu); 40 41 val = read_sysreg(cpacr_el1); 42 val |= CPACR_EL1_TTA; 43 val &= ~CPACR_EL1_ZEN; 44 45 /* 46 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to 47 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, 48 * except for some missing controls, such as TAM. 49 * In this case, CPTR_EL2.TAM has the same position with or without 50 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM 51 * shift value for trapping the AMU accesses. 52 */ 53 54 val |= CPTR_EL2_TAM; 55 56 if (update_fp_enabled(vcpu)) { 57 if (vcpu_has_sve(vcpu)) 58 val |= CPACR_EL1_ZEN; 59 } else { 60 val &= ~CPACR_EL1_FPEN; 61 __activate_traps_fpsimd32(vcpu); 62 } 63 64 write_sysreg(val, cpacr_el1); 65 66 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); 67 } 68 NOKPROBE_SYMBOL(__activate_traps); 69 70 static void __deactivate_traps(struct kvm_vcpu *vcpu) 71 { 72 extern char vectors[]; /* kernel exception vectors */ 73 74 ___deactivate_traps(vcpu); 75 76 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); 77 78 /* 79 * ARM errata 1165522 and 1530923 require the actual execution of the 80 * above before we can switch to the EL2/EL0 translation regime used by 81 * the host. 82 */ 83 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 84 85 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); 86 write_sysreg(vectors, vbar_el1); 87 } 88 NOKPROBE_SYMBOL(__deactivate_traps); 89 90 void activate_traps_vhe_load(struct kvm_vcpu *vcpu) 91 { 92 __activate_traps_common(vcpu); 93 } 94 95 void deactivate_traps_vhe_put(void) 96 { 97 u64 mdcr_el2 = read_sysreg(mdcr_el2); 98 99 mdcr_el2 &= MDCR_EL2_HPMN_MASK | 100 MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT | 101 MDCR_EL2_TPMS; 102 103 write_sysreg(mdcr_el2, mdcr_el2); 104 105 __deactivate_traps_common(); 106 } 107 108 /* Switch to the guest for VHE systems running in EL2 */ 109 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) 110 { 111 struct kvm_cpu_context *host_ctxt; 112 struct kvm_cpu_context *guest_ctxt; 113 u64 exit_code; 114 115 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 116 host_ctxt->__hyp_running_vcpu = vcpu; 117 guest_ctxt = &vcpu->arch.ctxt; 118 119 sysreg_save_host_state_vhe(host_ctxt); 120 121 /* 122 * ARM erratum 1165522 requires us to configure both stage 1 and 123 * stage 2 translation for the guest context before we clear 124 * HCR_EL2.TGE. 125 * 126 * We have already configured the guest's stage 1 translation in 127 * kvm_vcpu_load_sysregs_vhe above. We must now call 128 * __load_guest_stage2 before __activate_traps, because 129 * __load_guest_stage2 configures stage 2 translation, and 130 * __activate_traps clear HCR_EL2.TGE (among other things). 131 */ 132 __load_guest_stage2(vcpu->arch.hw_mmu); 133 __activate_traps(vcpu); 134 135 __adjust_pc(vcpu); 136 137 sysreg_restore_guest_state_vhe(guest_ctxt); 138 __debug_switch_to_guest(vcpu); 139 140 do { 141 /* Jump in the fire! */ 142 exit_code = __guest_enter(vcpu); 143 144 /* And we're baaack! */ 145 } while (fixup_guest_exit(vcpu, &exit_code)); 146 147 sysreg_save_guest_state_vhe(guest_ctxt); 148 149 __deactivate_traps(vcpu); 150 151 sysreg_restore_host_state_vhe(host_ctxt); 152 153 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) 154 __fpsimd_save_fpexc32(vcpu); 155 156 __debug_switch_to_host(vcpu); 157 158 return exit_code; 159 } 160 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); 161 162 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 163 { 164 int ret; 165 166 local_daif_mask(); 167 168 /* 169 * Having IRQs masked via PMR when entering the guest means the GIC 170 * will not signal the CPU of interrupts of lower priority, and the 171 * only way to get out will be via guest exceptions. 172 * Naturally, we want to avoid this. 173 * 174 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a 175 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. 176 */ 177 pmr_sync(); 178 179 ret = __kvm_vcpu_run_vhe(vcpu); 180 181 /* 182 * local_daif_restore() takes care to properly restore PSTATE.DAIF 183 * and the GIC PMR if the host is using IRQ priorities. 184 */ 185 local_daif_restore(DAIF_PROCCTX_NOIRQ); 186 187 /* 188 * When we exit from the guest we change a number of CPU configuration 189 * parameters, such as traps. Make sure these changes take effect 190 * before running the host or additional guests. 191 */ 192 isb(); 193 194 return ret; 195 } 196 197 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par) 198 { 199 struct kvm_cpu_context *host_ctxt; 200 struct kvm_vcpu *vcpu; 201 202 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 203 vcpu = host_ctxt->__hyp_running_vcpu; 204 205 __deactivate_traps(vcpu); 206 sysreg_restore_host_state_vhe(host_ctxt); 207 208 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n", 209 spsr, elr, 210 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), 211 read_sysreg(hpfar_el2), par, vcpu); 212 } 213 NOKPROBE_SYMBOL(__hyp_call_panic); 214 215 void __noreturn hyp_panic(void) 216 { 217 u64 spsr = read_sysreg_el2(SYS_SPSR); 218 u64 elr = read_sysreg_el2(SYS_ELR); 219 u64 par = read_sysreg_par(); 220 221 __hyp_call_panic(spsr, elr, par); 222 unreachable(); 223 } 224 225 asmlinkage void kvm_unexpected_el2_exception(void) 226 { 227 return __kvm_unexpected_el2_exception(); 228 } 229