1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 9 #include <linux/arm-smccc.h> 10 #include <linux/kvm_host.h> 11 #include <linux/types.h> 12 #include <linux/jump_label.h> 13 #include <uapi/linux/psci.h> 14 15 #include <kvm/arm_psci.h> 16 17 #include <asm/barrier.h> 18 #include <asm/cpufeature.h> 19 #include <asm/kprobes.h> 20 #include <asm/kvm_asm.h> 21 #include <asm/kvm_emulate.h> 22 #include <asm/kvm_hyp.h> 23 #include <asm/kvm_mmu.h> 24 #include <asm/fpsimd.h> 25 #include <asm/debug-monitors.h> 26 #include <asm/processor.h> 27 28 /* VHE specific context */ 29 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 30 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 31 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 32 33 static void __activate_traps(struct kvm_vcpu *vcpu) 34 { 35 u64 val; 36 37 ___activate_traps(vcpu); 38 39 val = read_sysreg(cpacr_el1); 40 val |= CPACR_EL1_TTA; 41 val &= ~CPACR_EL1_ZEN; 42 43 /* 44 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to 45 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, 46 * except for some missing controls, such as TAM. 47 * In this case, CPTR_EL2.TAM has the same position with or without 48 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM 49 * shift value for trapping the AMU accesses. 50 */ 51 52 val |= CPTR_EL2_TAM; 53 54 if (update_fp_enabled(vcpu)) { 55 if (vcpu_has_sve(vcpu)) 56 val |= CPACR_EL1_ZEN; 57 } else { 58 val &= ~CPACR_EL1_FPEN; 59 __activate_traps_fpsimd32(vcpu); 60 } 61 62 write_sysreg(val, cpacr_el1); 63 64 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); 65 } 66 NOKPROBE_SYMBOL(__activate_traps); 67 68 static void __deactivate_traps(struct kvm_vcpu *vcpu) 69 { 70 extern char vectors[]; /* kernel exception vectors */ 71 72 ___deactivate_traps(vcpu); 73 74 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); 75 76 /* 77 * ARM errata 1165522 and 1530923 require the actual execution of the 78 * above before we can switch to the EL2/EL0 translation regime used by 79 * the host. 80 */ 81 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 82 83 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); 84 write_sysreg(vectors, vbar_el1); 85 } 86 NOKPROBE_SYMBOL(__deactivate_traps); 87 88 void activate_traps_vhe_load(struct kvm_vcpu *vcpu) 89 { 90 __activate_traps_common(vcpu); 91 } 92 93 void deactivate_traps_vhe_put(struct kvm_vcpu *vcpu) 94 { 95 __deactivate_traps_common(vcpu); 96 } 97 98 static const exit_handler_fn hyp_exit_handlers[] = { 99 [0 ... ESR_ELx_EC_MAX] = NULL, 100 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 101 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 102 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 103 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 104 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 105 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 106 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth, 107 }; 108 109 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 110 { 111 return hyp_exit_handlers; 112 } 113 114 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code) 115 { 116 } 117 118 /* Switch to the guest for VHE systems running in EL2 */ 119 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) 120 { 121 struct kvm_cpu_context *host_ctxt; 122 struct kvm_cpu_context *guest_ctxt; 123 u64 exit_code; 124 125 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 126 host_ctxt->__hyp_running_vcpu = vcpu; 127 guest_ctxt = &vcpu->arch.ctxt; 128 129 sysreg_save_host_state_vhe(host_ctxt); 130 131 /* 132 * ARM erratum 1165522 requires us to configure both stage 1 and 133 * stage 2 translation for the guest context before we clear 134 * HCR_EL2.TGE. 135 * 136 * We have already configured the guest's stage 1 translation in 137 * kvm_vcpu_load_sysregs_vhe above. We must now call 138 * __load_stage2 before __activate_traps, because 139 * __load_stage2 configures stage 2 translation, and 140 * __activate_traps clear HCR_EL2.TGE (among other things). 141 */ 142 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch); 143 __activate_traps(vcpu); 144 145 __kvm_adjust_pc(vcpu); 146 147 sysreg_restore_guest_state_vhe(guest_ctxt); 148 __debug_switch_to_guest(vcpu); 149 150 do { 151 /* Jump in the fire! */ 152 exit_code = __guest_enter(vcpu); 153 154 /* And we're baaack! */ 155 } while (fixup_guest_exit(vcpu, &exit_code)); 156 157 sysreg_save_guest_state_vhe(guest_ctxt); 158 159 __deactivate_traps(vcpu); 160 161 sysreg_restore_host_state_vhe(host_ctxt); 162 163 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) 164 __fpsimd_save_fpexc32(vcpu); 165 166 __debug_switch_to_host(vcpu); 167 168 return exit_code; 169 } 170 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); 171 172 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 173 { 174 int ret; 175 176 local_daif_mask(); 177 178 /* 179 * Having IRQs masked via PMR when entering the guest means the GIC 180 * will not signal the CPU of interrupts of lower priority, and the 181 * only way to get out will be via guest exceptions. 182 * Naturally, we want to avoid this. 183 * 184 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a 185 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. 186 */ 187 pmr_sync(); 188 189 ret = __kvm_vcpu_run_vhe(vcpu); 190 191 /* 192 * local_daif_restore() takes care to properly restore PSTATE.DAIF 193 * and the GIC PMR if the host is using IRQ priorities. 194 */ 195 local_daif_restore(DAIF_PROCCTX_NOIRQ); 196 197 /* 198 * When we exit from the guest we change a number of CPU configuration 199 * parameters, such as traps. Make sure these changes take effect 200 * before running the host or additional guests. 201 */ 202 isb(); 203 204 return ret; 205 } 206 207 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par) 208 { 209 struct kvm_cpu_context *host_ctxt; 210 struct kvm_vcpu *vcpu; 211 212 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 213 vcpu = host_ctxt->__hyp_running_vcpu; 214 215 __deactivate_traps(vcpu); 216 sysreg_restore_host_state_vhe(host_ctxt); 217 218 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n", 219 spsr, elr, 220 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), 221 read_sysreg(hpfar_el2), par, vcpu); 222 } 223 NOKPROBE_SYMBOL(__hyp_call_panic); 224 225 void __noreturn hyp_panic(void) 226 { 227 u64 spsr = read_sysreg_el2(SYS_SPSR); 228 u64 elr = read_sysreg_el2(SYS_ELR); 229 u64 par = read_sysreg_par(); 230 231 __hyp_call_panic(spsr, elr, par); 232 unreachable(); 233 } 234 235 asmlinkage void kvm_unexpected_el2_exception(void) 236 { 237 return __kvm_unexpected_el2_exception(); 238 } 239