1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012-2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/adjust_pc.h> 8 9 #include <linux/compiler.h> 10 #include <linux/irqchip/arm-gic-v3.h> 11 #include <linux/kvm_host.h> 12 13 #include <asm/kvm_emulate.h> 14 #include <asm/kvm_hyp.h> 15 #include <asm/kvm_mmu.h> 16 17 #define vtr_to_max_lr_idx(v) ((v) & 0xf) 18 #define vtr_to_nr_pre_bits(v) ((((u32)(v) >> 26) & 7) + 1) 19 #define vtr_to_nr_apr_regs(v) (1 << (vtr_to_nr_pre_bits(v) - 5)) 20 21 static u64 __gic_v3_get_lr(unsigned int lr) 22 { 23 switch (lr & 0xf) { 24 case 0: 25 return read_gicreg(ICH_LR0_EL2); 26 case 1: 27 return read_gicreg(ICH_LR1_EL2); 28 case 2: 29 return read_gicreg(ICH_LR2_EL2); 30 case 3: 31 return read_gicreg(ICH_LR3_EL2); 32 case 4: 33 return read_gicreg(ICH_LR4_EL2); 34 case 5: 35 return read_gicreg(ICH_LR5_EL2); 36 case 6: 37 return read_gicreg(ICH_LR6_EL2); 38 case 7: 39 return read_gicreg(ICH_LR7_EL2); 40 case 8: 41 return read_gicreg(ICH_LR8_EL2); 42 case 9: 43 return read_gicreg(ICH_LR9_EL2); 44 case 10: 45 return read_gicreg(ICH_LR10_EL2); 46 case 11: 47 return read_gicreg(ICH_LR11_EL2); 48 case 12: 49 return read_gicreg(ICH_LR12_EL2); 50 case 13: 51 return read_gicreg(ICH_LR13_EL2); 52 case 14: 53 return read_gicreg(ICH_LR14_EL2); 54 case 15: 55 return read_gicreg(ICH_LR15_EL2); 56 } 57 58 unreachable(); 59 } 60 61 static void __gic_v3_set_lr(u64 val, int lr) 62 { 63 switch (lr & 0xf) { 64 case 0: 65 write_gicreg(val, ICH_LR0_EL2); 66 break; 67 case 1: 68 write_gicreg(val, ICH_LR1_EL2); 69 break; 70 case 2: 71 write_gicreg(val, ICH_LR2_EL2); 72 break; 73 case 3: 74 write_gicreg(val, ICH_LR3_EL2); 75 break; 76 case 4: 77 write_gicreg(val, ICH_LR4_EL2); 78 break; 79 case 5: 80 write_gicreg(val, ICH_LR5_EL2); 81 break; 82 case 6: 83 write_gicreg(val, ICH_LR6_EL2); 84 break; 85 case 7: 86 write_gicreg(val, ICH_LR7_EL2); 87 break; 88 case 8: 89 write_gicreg(val, ICH_LR8_EL2); 90 break; 91 case 9: 92 write_gicreg(val, ICH_LR9_EL2); 93 break; 94 case 10: 95 write_gicreg(val, ICH_LR10_EL2); 96 break; 97 case 11: 98 write_gicreg(val, ICH_LR11_EL2); 99 break; 100 case 12: 101 write_gicreg(val, ICH_LR12_EL2); 102 break; 103 case 13: 104 write_gicreg(val, ICH_LR13_EL2); 105 break; 106 case 14: 107 write_gicreg(val, ICH_LR14_EL2); 108 break; 109 case 15: 110 write_gicreg(val, ICH_LR15_EL2); 111 break; 112 } 113 } 114 115 static void __vgic_v3_write_ap0rn(u32 val, int n) 116 { 117 switch (n) { 118 case 0: 119 write_gicreg(val, ICH_AP0R0_EL2); 120 break; 121 case 1: 122 write_gicreg(val, ICH_AP0R1_EL2); 123 break; 124 case 2: 125 write_gicreg(val, ICH_AP0R2_EL2); 126 break; 127 case 3: 128 write_gicreg(val, ICH_AP0R3_EL2); 129 break; 130 } 131 } 132 133 static void __vgic_v3_write_ap1rn(u32 val, int n) 134 { 135 switch (n) { 136 case 0: 137 write_gicreg(val, ICH_AP1R0_EL2); 138 break; 139 case 1: 140 write_gicreg(val, ICH_AP1R1_EL2); 141 break; 142 case 2: 143 write_gicreg(val, ICH_AP1R2_EL2); 144 break; 145 case 3: 146 write_gicreg(val, ICH_AP1R3_EL2); 147 break; 148 } 149 } 150 151 static u32 __vgic_v3_read_ap0rn(int n) 152 { 153 u32 val; 154 155 switch (n) { 156 case 0: 157 val = read_gicreg(ICH_AP0R0_EL2); 158 break; 159 case 1: 160 val = read_gicreg(ICH_AP0R1_EL2); 161 break; 162 case 2: 163 val = read_gicreg(ICH_AP0R2_EL2); 164 break; 165 case 3: 166 val = read_gicreg(ICH_AP0R3_EL2); 167 break; 168 default: 169 unreachable(); 170 } 171 172 return val; 173 } 174 175 static u32 __vgic_v3_read_ap1rn(int n) 176 { 177 u32 val; 178 179 switch (n) { 180 case 0: 181 val = read_gicreg(ICH_AP1R0_EL2); 182 break; 183 case 1: 184 val = read_gicreg(ICH_AP1R1_EL2); 185 break; 186 case 2: 187 val = read_gicreg(ICH_AP1R2_EL2); 188 break; 189 case 3: 190 val = read_gicreg(ICH_AP1R3_EL2); 191 break; 192 default: 193 unreachable(); 194 } 195 196 return val; 197 } 198 199 void __vgic_v3_save_state(struct vgic_v3_cpu_if *cpu_if) 200 { 201 u64 used_lrs = cpu_if->used_lrs; 202 203 /* 204 * Make sure stores to the GIC via the memory mapped interface 205 * are now visible to the system register interface when reading the 206 * LRs, and when reading back the VMCR on non-VHE systems. 207 */ 208 if (used_lrs || !has_vhe()) { 209 if (!cpu_if->vgic_sre) { 210 dsb(sy); 211 isb(); 212 } 213 } 214 215 if (used_lrs || cpu_if->its_vpe.its_vm) { 216 int i; 217 u32 elrsr; 218 219 elrsr = read_gicreg(ICH_ELRSR_EL2); 220 221 write_gicreg(cpu_if->vgic_hcr & ~ICH_HCR_EN, ICH_HCR_EL2); 222 223 for (i = 0; i < used_lrs; i++) { 224 if (elrsr & (1 << i)) 225 cpu_if->vgic_lr[i] &= ~ICH_LR_STATE; 226 else 227 cpu_if->vgic_lr[i] = __gic_v3_get_lr(i); 228 229 __gic_v3_set_lr(0, i); 230 } 231 } 232 } 233 234 void __vgic_v3_restore_state(struct vgic_v3_cpu_if *cpu_if) 235 { 236 u64 used_lrs = cpu_if->used_lrs; 237 int i; 238 239 if (used_lrs || cpu_if->its_vpe.its_vm) { 240 write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2); 241 242 for (i = 0; i < used_lrs; i++) 243 __gic_v3_set_lr(cpu_if->vgic_lr[i], i); 244 } 245 246 /* 247 * Ensure that writes to the LRs, and on non-VHE systems ensure that 248 * the write to the VMCR in __vgic_v3_activate_traps(), will have 249 * reached the (re)distributors. This ensure the guest will read the 250 * correct values from the memory-mapped interface. 251 */ 252 if (used_lrs || !has_vhe()) { 253 if (!cpu_if->vgic_sre) { 254 isb(); 255 dsb(sy); 256 } 257 } 258 } 259 260 void __vgic_v3_activate_traps(struct vgic_v3_cpu_if *cpu_if) 261 { 262 /* 263 * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a 264 * Group0 interrupt (as generated in GICv2 mode) to be 265 * delivered as a FIQ to the guest, with potentially fatal 266 * consequences. So we must make sure that ICC_SRE_EL1 has 267 * been actually programmed with the value we want before 268 * starting to mess with the rest of the GIC, and VMCR_EL2 in 269 * particular. This logic must be called before 270 * __vgic_v3_restore_state(). 271 */ 272 if (!cpu_if->vgic_sre) { 273 write_gicreg(0, ICC_SRE_EL1); 274 isb(); 275 write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2); 276 277 278 if (has_vhe()) { 279 /* 280 * Ensure that the write to the VMCR will have reached 281 * the (re)distributors. This ensure the guest will 282 * read the correct values from the memory-mapped 283 * interface. 284 */ 285 isb(); 286 dsb(sy); 287 } 288 } 289 290 /* 291 * Prevent the guest from touching the GIC system registers if 292 * SRE isn't enabled for GICv3 emulation. 293 */ 294 write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE, 295 ICC_SRE_EL2); 296 297 /* 298 * If we need to trap system registers, we must write 299 * ICH_HCR_EL2 anyway, even if no interrupts are being 300 * injected, 301 */ 302 if (static_branch_unlikely(&vgic_v3_cpuif_trap) || 303 cpu_if->its_vpe.its_vm) 304 write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2); 305 } 306 307 void __vgic_v3_deactivate_traps(struct vgic_v3_cpu_if *cpu_if) 308 { 309 u64 val; 310 311 if (!cpu_if->vgic_sre) { 312 cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2); 313 } 314 315 val = read_gicreg(ICC_SRE_EL2); 316 write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); 317 318 if (!cpu_if->vgic_sre) { 319 /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */ 320 isb(); 321 write_gicreg(1, ICC_SRE_EL1); 322 } 323 324 /* 325 * If we were trapping system registers, we enabled the VGIC even if 326 * no interrupts were being injected, and we disable it again here. 327 */ 328 if (static_branch_unlikely(&vgic_v3_cpuif_trap) || 329 cpu_if->its_vpe.its_vm) 330 write_gicreg(0, ICH_HCR_EL2); 331 } 332 333 void __vgic_v3_save_aprs(struct vgic_v3_cpu_if *cpu_if) 334 { 335 u64 val; 336 u32 nr_pre_bits; 337 338 val = read_gicreg(ICH_VTR_EL2); 339 nr_pre_bits = vtr_to_nr_pre_bits(val); 340 341 switch (nr_pre_bits) { 342 case 7: 343 cpu_if->vgic_ap0r[3] = __vgic_v3_read_ap0rn(3); 344 cpu_if->vgic_ap0r[2] = __vgic_v3_read_ap0rn(2); 345 fallthrough; 346 case 6: 347 cpu_if->vgic_ap0r[1] = __vgic_v3_read_ap0rn(1); 348 fallthrough; 349 default: 350 cpu_if->vgic_ap0r[0] = __vgic_v3_read_ap0rn(0); 351 } 352 353 switch (nr_pre_bits) { 354 case 7: 355 cpu_if->vgic_ap1r[3] = __vgic_v3_read_ap1rn(3); 356 cpu_if->vgic_ap1r[2] = __vgic_v3_read_ap1rn(2); 357 fallthrough; 358 case 6: 359 cpu_if->vgic_ap1r[1] = __vgic_v3_read_ap1rn(1); 360 fallthrough; 361 default: 362 cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0); 363 } 364 } 365 366 void __vgic_v3_restore_aprs(struct vgic_v3_cpu_if *cpu_if) 367 { 368 u64 val; 369 u32 nr_pre_bits; 370 371 val = read_gicreg(ICH_VTR_EL2); 372 nr_pre_bits = vtr_to_nr_pre_bits(val); 373 374 switch (nr_pre_bits) { 375 case 7: 376 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[3], 3); 377 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[2], 2); 378 fallthrough; 379 case 6: 380 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[1], 1); 381 fallthrough; 382 default: 383 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[0], 0); 384 } 385 386 switch (nr_pre_bits) { 387 case 7: 388 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[3], 3); 389 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[2], 2); 390 fallthrough; 391 case 6: 392 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[1], 1); 393 fallthrough; 394 default: 395 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[0], 0); 396 } 397 } 398 399 void __vgic_v3_init_lrs(void) 400 { 401 int max_lr_idx = vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2)); 402 int i; 403 404 for (i = 0; i <= max_lr_idx; i++) 405 __gic_v3_set_lr(0, i); 406 } 407 408 /* 409 * Return the GIC CPU configuration: 410 * - [31:0] ICH_VTR_EL2 411 * - [62:32] RES0 412 * - [63] MMIO (GICv2) capable 413 */ 414 u64 __vgic_v3_get_gic_config(void) 415 { 416 u64 val, sre = read_gicreg(ICC_SRE_EL1); 417 unsigned long flags = 0; 418 419 /* 420 * To check whether we have a MMIO-based (GICv2 compatible) 421 * CPU interface, we need to disable the system register 422 * view. To do that safely, we have to prevent any interrupt 423 * from firing (which would be deadly). 424 * 425 * Note that this only makes sense on VHE, as interrupts are 426 * already masked for nVHE as part of the exception entry to 427 * EL2. 428 */ 429 if (has_vhe()) 430 flags = local_daif_save(); 431 432 write_gicreg(0, ICC_SRE_EL1); 433 isb(); 434 435 val = read_gicreg(ICC_SRE_EL1); 436 437 write_gicreg(sre, ICC_SRE_EL1); 438 isb(); 439 440 if (has_vhe()) 441 local_daif_restore(flags); 442 443 val = (val & ICC_SRE_EL1_SRE) ? 0 : (1ULL << 63); 444 val |= read_gicreg(ICH_VTR_EL2); 445 446 return val; 447 } 448 449 u64 __vgic_v3_read_vmcr(void) 450 { 451 return read_gicreg(ICH_VMCR_EL2); 452 } 453 454 void __vgic_v3_write_vmcr(u32 vmcr) 455 { 456 write_gicreg(vmcr, ICH_VMCR_EL2); 457 } 458 459 static int __vgic_v3_bpr_min(void) 460 { 461 /* See Pseudocode for VPriorityGroup */ 462 return 8 - vtr_to_nr_pre_bits(read_gicreg(ICH_VTR_EL2)); 463 } 464 465 static int __vgic_v3_get_group(struct kvm_vcpu *vcpu) 466 { 467 u32 esr = kvm_vcpu_get_esr(vcpu); 468 u8 crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 469 470 return crm != 8; 471 } 472 473 #define GICv3_IDLE_PRIORITY 0xff 474 475 static int __vgic_v3_highest_priority_lr(struct kvm_vcpu *vcpu, u32 vmcr, 476 u64 *lr_val) 477 { 478 unsigned int used_lrs = vcpu->arch.vgic_cpu.vgic_v3.used_lrs; 479 u8 priority = GICv3_IDLE_PRIORITY; 480 int i, lr = -1; 481 482 for (i = 0; i < used_lrs; i++) { 483 u64 val = __gic_v3_get_lr(i); 484 u8 lr_prio = (val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT; 485 486 /* Not pending in the state? */ 487 if ((val & ICH_LR_STATE) != ICH_LR_PENDING_BIT) 488 continue; 489 490 /* Group-0 interrupt, but Group-0 disabled? */ 491 if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK)) 492 continue; 493 494 /* Group-1 interrupt, but Group-1 disabled? */ 495 if ((val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG1_MASK)) 496 continue; 497 498 /* Not the highest priority? */ 499 if (lr_prio >= priority) 500 continue; 501 502 /* This is a candidate */ 503 priority = lr_prio; 504 *lr_val = val; 505 lr = i; 506 } 507 508 if (lr == -1) 509 *lr_val = ICC_IAR1_EL1_SPURIOUS; 510 511 return lr; 512 } 513 514 static int __vgic_v3_find_active_lr(struct kvm_vcpu *vcpu, int intid, 515 u64 *lr_val) 516 { 517 unsigned int used_lrs = vcpu->arch.vgic_cpu.vgic_v3.used_lrs; 518 int i; 519 520 for (i = 0; i < used_lrs; i++) { 521 u64 val = __gic_v3_get_lr(i); 522 523 if ((val & ICH_LR_VIRTUAL_ID_MASK) == intid && 524 (val & ICH_LR_ACTIVE_BIT)) { 525 *lr_val = val; 526 return i; 527 } 528 } 529 530 *lr_val = ICC_IAR1_EL1_SPURIOUS; 531 return -1; 532 } 533 534 static int __vgic_v3_get_highest_active_priority(void) 535 { 536 u8 nr_apr_regs = vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2)); 537 u32 hap = 0; 538 int i; 539 540 for (i = 0; i < nr_apr_regs; i++) { 541 u32 val; 542 543 /* 544 * The ICH_AP0Rn_EL2 and ICH_AP1Rn_EL2 registers 545 * contain the active priority levels for this VCPU 546 * for the maximum number of supported priority 547 * levels, and we return the full priority level only 548 * if the BPR is programmed to its minimum, otherwise 549 * we return a combination of the priority level and 550 * subpriority, as determined by the setting of the 551 * BPR, but without the full subpriority. 552 */ 553 val = __vgic_v3_read_ap0rn(i); 554 val |= __vgic_v3_read_ap1rn(i); 555 if (!val) { 556 hap += 32; 557 continue; 558 } 559 560 return (hap + __ffs(val)) << __vgic_v3_bpr_min(); 561 } 562 563 return GICv3_IDLE_PRIORITY; 564 } 565 566 static unsigned int __vgic_v3_get_bpr0(u32 vmcr) 567 { 568 return (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT; 569 } 570 571 static unsigned int __vgic_v3_get_bpr1(u32 vmcr) 572 { 573 unsigned int bpr; 574 575 if (vmcr & ICH_VMCR_CBPR_MASK) { 576 bpr = __vgic_v3_get_bpr0(vmcr); 577 if (bpr < 7) 578 bpr++; 579 } else { 580 bpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT; 581 } 582 583 return bpr; 584 } 585 586 /* 587 * Convert a priority to a preemption level, taking the relevant BPR 588 * into account by zeroing the sub-priority bits. 589 */ 590 static u8 __vgic_v3_pri_to_pre(u8 pri, u32 vmcr, int grp) 591 { 592 unsigned int bpr; 593 594 if (!grp) 595 bpr = __vgic_v3_get_bpr0(vmcr) + 1; 596 else 597 bpr = __vgic_v3_get_bpr1(vmcr); 598 599 return pri & (GENMASK(7, 0) << bpr); 600 } 601 602 /* 603 * The priority value is independent of any of the BPR values, so we 604 * normalize it using the minimal BPR value. This guarantees that no 605 * matter what the guest does with its BPR, we can always set/get the 606 * same value of a priority. 607 */ 608 static void __vgic_v3_set_active_priority(u8 pri, u32 vmcr, int grp) 609 { 610 u8 pre, ap; 611 u32 val; 612 int apr; 613 614 pre = __vgic_v3_pri_to_pre(pri, vmcr, grp); 615 ap = pre >> __vgic_v3_bpr_min(); 616 apr = ap / 32; 617 618 if (!grp) { 619 val = __vgic_v3_read_ap0rn(apr); 620 __vgic_v3_write_ap0rn(val | BIT(ap % 32), apr); 621 } else { 622 val = __vgic_v3_read_ap1rn(apr); 623 __vgic_v3_write_ap1rn(val | BIT(ap % 32), apr); 624 } 625 } 626 627 static int __vgic_v3_clear_highest_active_priority(void) 628 { 629 u8 nr_apr_regs = vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2)); 630 u32 hap = 0; 631 int i; 632 633 for (i = 0; i < nr_apr_regs; i++) { 634 u32 ap0, ap1; 635 int c0, c1; 636 637 ap0 = __vgic_v3_read_ap0rn(i); 638 ap1 = __vgic_v3_read_ap1rn(i); 639 if (!ap0 && !ap1) { 640 hap += 32; 641 continue; 642 } 643 644 c0 = ap0 ? __ffs(ap0) : 32; 645 c1 = ap1 ? __ffs(ap1) : 32; 646 647 /* Always clear the LSB, which is the highest priority */ 648 if (c0 < c1) { 649 ap0 &= ~BIT(c0); 650 __vgic_v3_write_ap0rn(ap0, i); 651 hap += c0; 652 } else { 653 ap1 &= ~BIT(c1); 654 __vgic_v3_write_ap1rn(ap1, i); 655 hap += c1; 656 } 657 658 /* Rescale to 8 bits of priority */ 659 return hap << __vgic_v3_bpr_min(); 660 } 661 662 return GICv3_IDLE_PRIORITY; 663 } 664 665 static void __vgic_v3_read_iar(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 666 { 667 u64 lr_val; 668 u8 lr_prio, pmr; 669 int lr, grp; 670 671 grp = __vgic_v3_get_group(vcpu); 672 673 lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val); 674 if (lr < 0) 675 goto spurious; 676 677 if (grp != !!(lr_val & ICH_LR_GROUP)) 678 goto spurious; 679 680 pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; 681 lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT; 682 if (pmr <= lr_prio) 683 goto spurious; 684 685 if (__vgic_v3_get_highest_active_priority() <= __vgic_v3_pri_to_pre(lr_prio, vmcr, grp)) 686 goto spurious; 687 688 lr_val &= ~ICH_LR_STATE; 689 /* No active state for LPIs */ 690 if ((lr_val & ICH_LR_VIRTUAL_ID_MASK) <= VGIC_MAX_SPI) 691 lr_val |= ICH_LR_ACTIVE_BIT; 692 __gic_v3_set_lr(lr_val, lr); 693 __vgic_v3_set_active_priority(lr_prio, vmcr, grp); 694 vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK); 695 return; 696 697 spurious: 698 vcpu_set_reg(vcpu, rt, ICC_IAR1_EL1_SPURIOUS); 699 } 700 701 static void __vgic_v3_clear_active_lr(int lr, u64 lr_val) 702 { 703 lr_val &= ~ICH_LR_ACTIVE_BIT; 704 if (lr_val & ICH_LR_HW) { 705 u32 pid; 706 707 pid = (lr_val & ICH_LR_PHYS_ID_MASK) >> ICH_LR_PHYS_ID_SHIFT; 708 gic_write_dir(pid); 709 } 710 711 __gic_v3_set_lr(lr_val, lr); 712 } 713 714 static void __vgic_v3_bump_eoicount(void) 715 { 716 u32 hcr; 717 718 hcr = read_gicreg(ICH_HCR_EL2); 719 hcr += 1 << ICH_HCR_EOIcount_SHIFT; 720 write_gicreg(hcr, ICH_HCR_EL2); 721 } 722 723 static void __vgic_v3_write_dir(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 724 { 725 u32 vid = vcpu_get_reg(vcpu, rt); 726 u64 lr_val; 727 int lr; 728 729 /* EOImode == 0, nothing to be done here */ 730 if (!(vmcr & ICH_VMCR_EOIM_MASK)) 731 return; 732 733 /* No deactivate to be performed on an LPI */ 734 if (vid >= VGIC_MIN_LPI) 735 return; 736 737 lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val); 738 if (lr == -1) { 739 __vgic_v3_bump_eoicount(); 740 return; 741 } 742 743 __vgic_v3_clear_active_lr(lr, lr_val); 744 } 745 746 static void __vgic_v3_write_eoir(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 747 { 748 u32 vid = vcpu_get_reg(vcpu, rt); 749 u64 lr_val; 750 u8 lr_prio, act_prio; 751 int lr, grp; 752 753 grp = __vgic_v3_get_group(vcpu); 754 755 /* Drop priority in any case */ 756 act_prio = __vgic_v3_clear_highest_active_priority(); 757 758 /* If EOIing an LPI, no deactivate to be performed */ 759 if (vid >= VGIC_MIN_LPI) 760 return; 761 762 /* EOImode == 1, nothing to be done here */ 763 if (vmcr & ICH_VMCR_EOIM_MASK) 764 return; 765 766 lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val); 767 if (lr == -1) { 768 __vgic_v3_bump_eoicount(); 769 return; 770 } 771 772 lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT; 773 774 /* If priorities or group do not match, the guest has fscked-up. */ 775 if (grp != !!(lr_val & ICH_LR_GROUP) || 776 __vgic_v3_pri_to_pre(lr_prio, vmcr, grp) != act_prio) 777 return; 778 779 /* Let's now perform the deactivation */ 780 __vgic_v3_clear_active_lr(lr, lr_val); 781 } 782 783 static void __vgic_v3_read_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 784 { 785 vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG0_MASK)); 786 } 787 788 static void __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 789 { 790 vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK)); 791 } 792 793 static void __vgic_v3_write_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 794 { 795 u64 val = vcpu_get_reg(vcpu, rt); 796 797 if (val & 1) 798 vmcr |= ICH_VMCR_ENG0_MASK; 799 else 800 vmcr &= ~ICH_VMCR_ENG0_MASK; 801 802 __vgic_v3_write_vmcr(vmcr); 803 } 804 805 static void __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 806 { 807 u64 val = vcpu_get_reg(vcpu, rt); 808 809 if (val & 1) 810 vmcr |= ICH_VMCR_ENG1_MASK; 811 else 812 vmcr &= ~ICH_VMCR_ENG1_MASK; 813 814 __vgic_v3_write_vmcr(vmcr); 815 } 816 817 static void __vgic_v3_read_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 818 { 819 vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr0(vmcr)); 820 } 821 822 static void __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 823 { 824 vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr)); 825 } 826 827 static void __vgic_v3_write_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 828 { 829 u64 val = vcpu_get_reg(vcpu, rt); 830 u8 bpr_min = __vgic_v3_bpr_min() - 1; 831 832 /* Enforce BPR limiting */ 833 if (val < bpr_min) 834 val = bpr_min; 835 836 val <<= ICH_VMCR_BPR0_SHIFT; 837 val &= ICH_VMCR_BPR0_MASK; 838 vmcr &= ~ICH_VMCR_BPR0_MASK; 839 vmcr |= val; 840 841 __vgic_v3_write_vmcr(vmcr); 842 } 843 844 static void __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 845 { 846 u64 val = vcpu_get_reg(vcpu, rt); 847 u8 bpr_min = __vgic_v3_bpr_min(); 848 849 if (vmcr & ICH_VMCR_CBPR_MASK) 850 return; 851 852 /* Enforce BPR limiting */ 853 if (val < bpr_min) 854 val = bpr_min; 855 856 val <<= ICH_VMCR_BPR1_SHIFT; 857 val &= ICH_VMCR_BPR1_MASK; 858 vmcr &= ~ICH_VMCR_BPR1_MASK; 859 vmcr |= val; 860 861 __vgic_v3_write_vmcr(vmcr); 862 } 863 864 static void __vgic_v3_read_apxrn(struct kvm_vcpu *vcpu, int rt, int n) 865 { 866 u32 val; 867 868 if (!__vgic_v3_get_group(vcpu)) 869 val = __vgic_v3_read_ap0rn(n); 870 else 871 val = __vgic_v3_read_ap1rn(n); 872 873 vcpu_set_reg(vcpu, rt, val); 874 } 875 876 static void __vgic_v3_write_apxrn(struct kvm_vcpu *vcpu, int rt, int n) 877 { 878 u32 val = vcpu_get_reg(vcpu, rt); 879 880 if (!__vgic_v3_get_group(vcpu)) 881 __vgic_v3_write_ap0rn(val, n); 882 else 883 __vgic_v3_write_ap1rn(val, n); 884 } 885 886 static void __vgic_v3_read_apxr0(struct kvm_vcpu *vcpu, 887 u32 vmcr, int rt) 888 { 889 __vgic_v3_read_apxrn(vcpu, rt, 0); 890 } 891 892 static void __vgic_v3_read_apxr1(struct kvm_vcpu *vcpu, 893 u32 vmcr, int rt) 894 { 895 __vgic_v3_read_apxrn(vcpu, rt, 1); 896 } 897 898 static void __vgic_v3_read_apxr2(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 899 { 900 __vgic_v3_read_apxrn(vcpu, rt, 2); 901 } 902 903 static void __vgic_v3_read_apxr3(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 904 { 905 __vgic_v3_read_apxrn(vcpu, rt, 3); 906 } 907 908 static void __vgic_v3_write_apxr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 909 { 910 __vgic_v3_write_apxrn(vcpu, rt, 0); 911 } 912 913 static void __vgic_v3_write_apxr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 914 { 915 __vgic_v3_write_apxrn(vcpu, rt, 1); 916 } 917 918 static void __vgic_v3_write_apxr2(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 919 { 920 __vgic_v3_write_apxrn(vcpu, rt, 2); 921 } 922 923 static void __vgic_v3_write_apxr3(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 924 { 925 __vgic_v3_write_apxrn(vcpu, rt, 3); 926 } 927 928 static void __vgic_v3_read_hppir(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 929 { 930 u64 lr_val; 931 int lr, lr_grp, grp; 932 933 grp = __vgic_v3_get_group(vcpu); 934 935 lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val); 936 if (lr == -1) 937 goto spurious; 938 939 lr_grp = !!(lr_val & ICH_LR_GROUP); 940 if (lr_grp != grp) 941 lr_val = ICC_IAR1_EL1_SPURIOUS; 942 943 spurious: 944 vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK); 945 } 946 947 static void __vgic_v3_read_pmr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 948 { 949 vmcr &= ICH_VMCR_PMR_MASK; 950 vmcr >>= ICH_VMCR_PMR_SHIFT; 951 vcpu_set_reg(vcpu, rt, vmcr); 952 } 953 954 static void __vgic_v3_write_pmr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 955 { 956 u32 val = vcpu_get_reg(vcpu, rt); 957 958 val <<= ICH_VMCR_PMR_SHIFT; 959 val &= ICH_VMCR_PMR_MASK; 960 vmcr &= ~ICH_VMCR_PMR_MASK; 961 vmcr |= val; 962 963 write_gicreg(vmcr, ICH_VMCR_EL2); 964 } 965 966 static void __vgic_v3_read_rpr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 967 { 968 u32 val = __vgic_v3_get_highest_active_priority(); 969 vcpu_set_reg(vcpu, rt, val); 970 } 971 972 static void __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 973 { 974 u32 vtr, val; 975 976 vtr = read_gicreg(ICH_VTR_EL2); 977 /* PRIbits */ 978 val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT; 979 /* IDbits */ 980 val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT; 981 /* SEIS */ 982 val |= ((vtr >> 22) & 1) << ICC_CTLR_EL1_SEIS_SHIFT; 983 /* A3V */ 984 val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT; 985 /* EOImode */ 986 val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT; 987 /* CBPR */ 988 val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; 989 990 vcpu_set_reg(vcpu, rt, val); 991 } 992 993 static void __vgic_v3_write_ctlr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 994 { 995 u32 val = vcpu_get_reg(vcpu, rt); 996 997 if (val & ICC_CTLR_EL1_CBPR_MASK) 998 vmcr |= ICH_VMCR_CBPR_MASK; 999 else 1000 vmcr &= ~ICH_VMCR_CBPR_MASK; 1001 1002 if (val & ICC_CTLR_EL1_EOImode_MASK) 1003 vmcr |= ICH_VMCR_EOIM_MASK; 1004 else 1005 vmcr &= ~ICH_VMCR_EOIM_MASK; 1006 1007 write_gicreg(vmcr, ICH_VMCR_EL2); 1008 } 1009 1010 int __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu) 1011 { 1012 int rt; 1013 u32 esr; 1014 u32 vmcr; 1015 void (*fn)(struct kvm_vcpu *, u32, int); 1016 bool is_read; 1017 u32 sysreg; 1018 1019 esr = kvm_vcpu_get_esr(vcpu); 1020 if (vcpu_mode_is_32bit(vcpu)) { 1021 if (!kvm_condition_valid(vcpu)) { 1022 __kvm_skip_instr(vcpu); 1023 return 1; 1024 } 1025 1026 sysreg = esr_cp15_to_sysreg(esr); 1027 } else { 1028 sysreg = esr_sys64_to_sysreg(esr); 1029 } 1030 1031 is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ; 1032 1033 switch (sysreg) { 1034 case SYS_ICC_IAR0_EL1: 1035 case SYS_ICC_IAR1_EL1: 1036 if (unlikely(!is_read)) 1037 return 0; 1038 fn = __vgic_v3_read_iar; 1039 break; 1040 case SYS_ICC_EOIR0_EL1: 1041 case SYS_ICC_EOIR1_EL1: 1042 if (unlikely(is_read)) 1043 return 0; 1044 fn = __vgic_v3_write_eoir; 1045 break; 1046 case SYS_ICC_IGRPEN1_EL1: 1047 if (is_read) 1048 fn = __vgic_v3_read_igrpen1; 1049 else 1050 fn = __vgic_v3_write_igrpen1; 1051 break; 1052 case SYS_ICC_BPR1_EL1: 1053 if (is_read) 1054 fn = __vgic_v3_read_bpr1; 1055 else 1056 fn = __vgic_v3_write_bpr1; 1057 break; 1058 case SYS_ICC_AP0Rn_EL1(0): 1059 case SYS_ICC_AP1Rn_EL1(0): 1060 if (is_read) 1061 fn = __vgic_v3_read_apxr0; 1062 else 1063 fn = __vgic_v3_write_apxr0; 1064 break; 1065 case SYS_ICC_AP0Rn_EL1(1): 1066 case SYS_ICC_AP1Rn_EL1(1): 1067 if (is_read) 1068 fn = __vgic_v3_read_apxr1; 1069 else 1070 fn = __vgic_v3_write_apxr1; 1071 break; 1072 case SYS_ICC_AP0Rn_EL1(2): 1073 case SYS_ICC_AP1Rn_EL1(2): 1074 if (is_read) 1075 fn = __vgic_v3_read_apxr2; 1076 else 1077 fn = __vgic_v3_write_apxr2; 1078 break; 1079 case SYS_ICC_AP0Rn_EL1(3): 1080 case SYS_ICC_AP1Rn_EL1(3): 1081 if (is_read) 1082 fn = __vgic_v3_read_apxr3; 1083 else 1084 fn = __vgic_v3_write_apxr3; 1085 break; 1086 case SYS_ICC_HPPIR0_EL1: 1087 case SYS_ICC_HPPIR1_EL1: 1088 if (unlikely(!is_read)) 1089 return 0; 1090 fn = __vgic_v3_read_hppir; 1091 break; 1092 case SYS_ICC_IGRPEN0_EL1: 1093 if (is_read) 1094 fn = __vgic_v3_read_igrpen0; 1095 else 1096 fn = __vgic_v3_write_igrpen0; 1097 break; 1098 case SYS_ICC_BPR0_EL1: 1099 if (is_read) 1100 fn = __vgic_v3_read_bpr0; 1101 else 1102 fn = __vgic_v3_write_bpr0; 1103 break; 1104 case SYS_ICC_DIR_EL1: 1105 if (unlikely(is_read)) 1106 return 0; 1107 fn = __vgic_v3_write_dir; 1108 break; 1109 case SYS_ICC_RPR_EL1: 1110 if (unlikely(!is_read)) 1111 return 0; 1112 fn = __vgic_v3_read_rpr; 1113 break; 1114 case SYS_ICC_CTLR_EL1: 1115 if (is_read) 1116 fn = __vgic_v3_read_ctlr; 1117 else 1118 fn = __vgic_v3_write_ctlr; 1119 break; 1120 case SYS_ICC_PMR_EL1: 1121 if (is_read) 1122 fn = __vgic_v3_read_pmr; 1123 else 1124 fn = __vgic_v3_write_pmr; 1125 break; 1126 default: 1127 return 0; 1128 } 1129 1130 vmcr = __vgic_v3_read_vmcr(); 1131 rt = kvm_vcpu_sys_get_rt(vcpu); 1132 fn(vcpu, vmcr, rt); 1133 1134 __kvm_skip_instr(vcpu); 1135 1136 return 1; 1137 } 1138