1 /* 2 * Copyright (C) 2012-2015 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <linux/compiler.h> 19 #include <linux/irqchip/arm-gic-v3.h> 20 #include <linux/kvm_host.h> 21 22 #include <asm/kvm_hyp.h> 23 24 #define vtr_to_max_lr_idx(v) ((v) & 0xf) 25 #define vtr_to_nr_pri_bits(v) (((u32)(v) >> 29) + 1) 26 27 #define read_gicreg(r) \ 28 ({ \ 29 u64 reg; \ 30 asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg)); \ 31 reg; \ 32 }) 33 34 #define write_gicreg(v,r) \ 35 do { \ 36 u64 __val = (v); \ 37 asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\ 38 } while (0) 39 40 static u64 __hyp_text __gic_v3_get_lr(unsigned int lr) 41 { 42 switch (lr & 0xf) { 43 case 0: 44 return read_gicreg(ICH_LR0_EL2); 45 case 1: 46 return read_gicreg(ICH_LR1_EL2); 47 case 2: 48 return read_gicreg(ICH_LR2_EL2); 49 case 3: 50 return read_gicreg(ICH_LR3_EL2); 51 case 4: 52 return read_gicreg(ICH_LR4_EL2); 53 case 5: 54 return read_gicreg(ICH_LR5_EL2); 55 case 6: 56 return read_gicreg(ICH_LR6_EL2); 57 case 7: 58 return read_gicreg(ICH_LR7_EL2); 59 case 8: 60 return read_gicreg(ICH_LR8_EL2); 61 case 9: 62 return read_gicreg(ICH_LR9_EL2); 63 case 10: 64 return read_gicreg(ICH_LR10_EL2); 65 case 11: 66 return read_gicreg(ICH_LR11_EL2); 67 case 12: 68 return read_gicreg(ICH_LR12_EL2); 69 case 13: 70 return read_gicreg(ICH_LR13_EL2); 71 case 14: 72 return read_gicreg(ICH_LR14_EL2); 73 case 15: 74 return read_gicreg(ICH_LR15_EL2); 75 } 76 77 unreachable(); 78 } 79 80 static void __hyp_text __gic_v3_set_lr(u64 val, int lr) 81 { 82 switch (lr & 0xf) { 83 case 0: 84 write_gicreg(val, ICH_LR0_EL2); 85 break; 86 case 1: 87 write_gicreg(val, ICH_LR1_EL2); 88 break; 89 case 2: 90 write_gicreg(val, ICH_LR2_EL2); 91 break; 92 case 3: 93 write_gicreg(val, ICH_LR3_EL2); 94 break; 95 case 4: 96 write_gicreg(val, ICH_LR4_EL2); 97 break; 98 case 5: 99 write_gicreg(val, ICH_LR5_EL2); 100 break; 101 case 6: 102 write_gicreg(val, ICH_LR6_EL2); 103 break; 104 case 7: 105 write_gicreg(val, ICH_LR7_EL2); 106 break; 107 case 8: 108 write_gicreg(val, ICH_LR8_EL2); 109 break; 110 case 9: 111 write_gicreg(val, ICH_LR9_EL2); 112 break; 113 case 10: 114 write_gicreg(val, ICH_LR10_EL2); 115 break; 116 case 11: 117 write_gicreg(val, ICH_LR11_EL2); 118 break; 119 case 12: 120 write_gicreg(val, ICH_LR12_EL2); 121 break; 122 case 13: 123 write_gicreg(val, ICH_LR13_EL2); 124 break; 125 case 14: 126 write_gicreg(val, ICH_LR14_EL2); 127 break; 128 case 15: 129 write_gicreg(val, ICH_LR15_EL2); 130 break; 131 } 132 } 133 134 static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu, int nr_lr) 135 { 136 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; 137 int i; 138 bool expect_mi; 139 140 expect_mi = !!(cpu_if->vgic_hcr & ICH_HCR_UIE); 141 142 for (i = 0; i < nr_lr; i++) { 143 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i))) 144 continue; 145 146 expect_mi |= (!(cpu_if->vgic_lr[i] & ICH_LR_HW) && 147 (cpu_if->vgic_lr[i] & ICH_LR_EOI)); 148 } 149 150 if (expect_mi) { 151 cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2); 152 153 if (cpu_if->vgic_misr & ICH_MISR_EOI) 154 cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2); 155 else 156 cpu_if->vgic_eisr = 0; 157 } else { 158 cpu_if->vgic_misr = 0; 159 cpu_if->vgic_eisr = 0; 160 } 161 } 162 163 void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu) 164 { 165 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; 166 u64 val; 167 168 /* 169 * Make sure stores to the GIC via the memory mapped interface 170 * are now visible to the system register interface. 171 */ 172 dsb(st); 173 174 cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2); 175 176 if (vcpu->arch.vgic_cpu.live_lrs) { 177 int i; 178 u32 max_lr_idx, nr_pri_bits; 179 180 cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2); 181 182 write_gicreg(0, ICH_HCR_EL2); 183 val = read_gicreg(ICH_VTR_EL2); 184 max_lr_idx = vtr_to_max_lr_idx(val); 185 nr_pri_bits = vtr_to_nr_pri_bits(val); 186 187 save_maint_int_state(vcpu, max_lr_idx + 1); 188 189 for (i = 0; i <= max_lr_idx; i++) { 190 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i))) 191 continue; 192 193 if (cpu_if->vgic_elrsr & (1 << i)) { 194 cpu_if->vgic_lr[i] &= ~ICH_LR_STATE; 195 continue; 196 } 197 198 cpu_if->vgic_lr[i] = __gic_v3_get_lr(i); 199 __gic_v3_set_lr(0, i); 200 } 201 202 switch (nr_pri_bits) { 203 case 7: 204 cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2); 205 cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2); 206 case 6: 207 cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2); 208 default: 209 cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2); 210 } 211 212 switch (nr_pri_bits) { 213 case 7: 214 cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2); 215 cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2); 216 case 6: 217 cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2); 218 default: 219 cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2); 220 } 221 222 vcpu->arch.vgic_cpu.live_lrs = 0; 223 } else { 224 cpu_if->vgic_misr = 0; 225 cpu_if->vgic_eisr = 0; 226 cpu_if->vgic_elrsr = 0xffff; 227 cpu_if->vgic_ap0r[0] = 0; 228 cpu_if->vgic_ap0r[1] = 0; 229 cpu_if->vgic_ap0r[2] = 0; 230 cpu_if->vgic_ap0r[3] = 0; 231 cpu_if->vgic_ap1r[0] = 0; 232 cpu_if->vgic_ap1r[1] = 0; 233 cpu_if->vgic_ap1r[2] = 0; 234 cpu_if->vgic_ap1r[3] = 0; 235 } 236 237 val = read_gicreg(ICC_SRE_EL2); 238 write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); 239 isb(); /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */ 240 write_gicreg(1, ICC_SRE_EL1); 241 } 242 243 void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu) 244 { 245 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; 246 u64 val; 247 u32 max_lr_idx, nr_pri_bits; 248 u16 live_lrs = 0; 249 int i; 250 251 /* 252 * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a 253 * Group0 interrupt (as generated in GICv2 mode) to be 254 * delivered as a FIQ to the guest, with potentially fatal 255 * consequences. So we must make sure that ICC_SRE_EL1 has 256 * been actually programmed with the value we want before 257 * starting to mess with the rest of the GIC. 258 */ 259 write_gicreg(cpu_if->vgic_sre, ICC_SRE_EL1); 260 isb(); 261 262 val = read_gicreg(ICH_VTR_EL2); 263 max_lr_idx = vtr_to_max_lr_idx(val); 264 nr_pri_bits = vtr_to_nr_pri_bits(val); 265 266 for (i = 0; i <= max_lr_idx; i++) { 267 if (cpu_if->vgic_lr[i] & ICH_LR_STATE) 268 live_lrs |= (1 << i); 269 } 270 271 write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2); 272 273 if (live_lrs) { 274 write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2); 275 276 switch (nr_pri_bits) { 277 case 7: 278 write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2); 279 write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2); 280 case 6: 281 write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2); 282 default: 283 write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2); 284 } 285 286 switch (nr_pri_bits) { 287 case 7: 288 write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2); 289 write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2); 290 case 6: 291 write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2); 292 default: 293 write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2); 294 } 295 296 for (i = 0; i <= max_lr_idx; i++) { 297 if (!(live_lrs & (1 << i))) 298 continue; 299 300 __gic_v3_set_lr(cpu_if->vgic_lr[i], i); 301 } 302 } 303 304 /* 305 * Ensures that the above will have reached the 306 * (re)distributors. This ensure the guest will read the 307 * correct values from the memory-mapped interface. 308 */ 309 isb(); 310 dsb(sy); 311 vcpu->arch.vgic_cpu.live_lrs = live_lrs; 312 313 /* 314 * Prevent the guest from touching the GIC system registers if 315 * SRE isn't enabled for GICv3 emulation. 316 */ 317 if (!cpu_if->vgic_sre) { 318 write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE, 319 ICC_SRE_EL2); 320 } 321 } 322 323 void __hyp_text __vgic_v3_init_lrs(void) 324 { 325 int max_lr_idx = vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2)); 326 int i; 327 328 for (i = 0; i <= max_lr_idx; i++) 329 __gic_v3_set_lr(0, i); 330 } 331 332 static u64 __hyp_text __vgic_v3_read_ich_vtr_el2(void) 333 { 334 return read_gicreg(ICH_VTR_EL2); 335 } 336 337 __alias(__vgic_v3_read_ich_vtr_el2) u64 __vgic_v3_get_ich_vtr_el2(void); 338