1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 #include <hyp/sysreg-sr.h> 9 10 #include <linux/arm-smccc.h> 11 #include <linux/kvm_host.h> 12 #include <linux/types.h> 13 #include <linux/jump_label.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 #include <asm/thread_info.h> 29 30 #include <nvhe/fixed_config.h> 31 #include <nvhe/mem_protect.h> 32 33 /* Non-VHE specific context */ 34 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 35 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 36 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 37 38 static void __activate_traps(struct kvm_vcpu *vcpu) 39 { 40 u64 val; 41 42 ___activate_traps(vcpu); 43 __activate_traps_common(vcpu); 44 45 val = vcpu->arch.cptr_el2; 46 val |= CPTR_EL2_TTA | CPTR_EL2_TAM; 47 if (!update_fp_enabled(vcpu)) { 48 val |= CPTR_EL2_TFP | CPTR_EL2_TZ; 49 __activate_traps_fpsimd32(vcpu); 50 } 51 52 write_sysreg(val, cptr_el2); 53 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); 54 55 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 56 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; 57 58 isb(); 59 /* 60 * At this stage, and thanks to the above isb(), S2 is 61 * configured and enabled. We can now restore the guest's S1 62 * configuration: SCTLR, and only then TCR. 63 */ 64 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR); 65 isb(); 66 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); 67 } 68 } 69 70 static void __deactivate_traps(struct kvm_vcpu *vcpu) 71 { 72 extern char __kvm_hyp_host_vector[]; 73 u64 cptr; 74 75 ___deactivate_traps(vcpu); 76 77 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 78 u64 val; 79 80 /* 81 * Set the TCR and SCTLR registers in the exact opposite 82 * sequence as __activate_traps (first prevent walks, 83 * then force the MMU on). A generous sprinkling of isb() 84 * ensure that things happen in this exact order. 85 */ 86 val = read_sysreg_el1(SYS_TCR); 87 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR); 88 isb(); 89 val = read_sysreg_el1(SYS_SCTLR); 90 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR); 91 isb(); 92 } 93 94 __deactivate_traps_common(vcpu); 95 96 write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2); 97 98 cptr = CPTR_EL2_DEFAULT; 99 if (vcpu_has_sve(vcpu) && (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)) 100 cptr |= CPTR_EL2_TZ; 101 102 write_sysreg(cptr, cptr_el2); 103 write_sysreg(__kvm_hyp_host_vector, vbar_el2); 104 } 105 106 /* Save VGICv3 state on non-VHE systems */ 107 static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu) 108 { 109 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 110 __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3); 111 __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 112 } 113 } 114 115 /* Restore VGICv3 state on non_VEH systems */ 116 static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu) 117 { 118 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 119 __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 120 __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3); 121 } 122 } 123 124 /** 125 * Disable host events, enable guest events 126 */ 127 static bool __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt) 128 { 129 struct kvm_host_data *host; 130 struct kvm_pmu_events *pmu; 131 132 host = container_of(host_ctxt, struct kvm_host_data, host_ctxt); 133 pmu = &host->pmu_events; 134 135 if (pmu->events_host) 136 write_sysreg(pmu->events_host, pmcntenclr_el0); 137 138 if (pmu->events_guest) 139 write_sysreg(pmu->events_guest, pmcntenset_el0); 140 141 return (pmu->events_host || pmu->events_guest); 142 } 143 144 /** 145 * Disable guest events, enable host events 146 */ 147 static void __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt) 148 { 149 struct kvm_host_data *host; 150 struct kvm_pmu_events *pmu; 151 152 host = container_of(host_ctxt, struct kvm_host_data, host_ctxt); 153 pmu = &host->pmu_events; 154 155 if (pmu->events_guest) 156 write_sysreg(pmu->events_guest, pmcntenclr_el0); 157 158 if (pmu->events_host) 159 write_sysreg(pmu->events_host, pmcntenset_el0); 160 } 161 162 /** 163 * Handler for protected VM MSR, MRS or System instruction execution in AArch64. 164 * 165 * Returns true if the hypervisor has handled the exit, and control should go 166 * back to the guest, or false if it hasn't. 167 */ 168 static bool kvm_handle_pvm_sys64(struct kvm_vcpu *vcpu, u64 *exit_code) 169 { 170 /* 171 * Make sure we handle the exit for workarounds and ptrauth 172 * before the pKVM handling, as the latter could decide to 173 * UNDEF. 174 */ 175 return (kvm_hyp_handle_sysreg(vcpu, exit_code) || 176 kvm_handle_pvm_sysreg(vcpu, exit_code)); 177 } 178 179 /** 180 * Handler for protected floating-point and Advanced SIMD accesses. 181 * 182 * Returns true if the hypervisor has handled the exit, and control should go 183 * back to the guest, or false if it hasn't. 184 */ 185 static bool kvm_handle_pvm_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code) 186 { 187 /* Linux guests assume support for floating-point and Advanced SIMD. */ 188 BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_FP), 189 PVM_ID_AA64PFR0_ALLOW)); 190 BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_ASIMD), 191 PVM_ID_AA64PFR0_ALLOW)); 192 193 return kvm_hyp_handle_fpsimd(vcpu, exit_code); 194 } 195 196 static const exit_handler_fn hyp_exit_handlers[] = { 197 [0 ... ESR_ELx_EC_MAX] = NULL, 198 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 199 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 200 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 201 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 202 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 203 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 204 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth, 205 }; 206 207 static const exit_handler_fn pvm_exit_handlers[] = { 208 [0 ... ESR_ELx_EC_MAX] = NULL, 209 [ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64, 210 [ESR_ELx_EC_SVE] = kvm_handle_pvm_restricted, 211 [ESR_ELx_EC_FP_ASIMD] = kvm_handle_pvm_fpsimd, 212 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 213 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 214 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth, 215 }; 216 217 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 218 { 219 if (unlikely(kvm_vm_is_protected(kern_hyp_va(vcpu->kvm)))) 220 return pvm_exit_handlers; 221 222 return hyp_exit_handlers; 223 } 224 225 /* 226 * Some guests (e.g., protected VMs) are not be allowed to run in AArch32. 227 * The ARMv8 architecture does not give the hypervisor a mechanism to prevent a 228 * guest from dropping to AArch32 EL0 if implemented by the CPU. If the 229 * hypervisor spots a guest in such a state ensure it is handled, and don't 230 * trust the host to spot or fix it. The check below is based on the one in 231 * kvm_arch_vcpu_ioctl_run(). 232 * 233 * Returns false if the guest ran in AArch32 when it shouldn't have, and 234 * thus should exit to the host, or true if a the guest run loop can continue. 235 */ 236 static bool handle_aarch32_guest(struct kvm_vcpu *vcpu, u64 *exit_code) 237 { 238 struct kvm *kvm = kern_hyp_va(vcpu->kvm); 239 240 if (kvm_vm_is_protected(kvm) && vcpu_mode_is_32bit(vcpu)) { 241 /* 242 * As we have caught the guest red-handed, decide that it isn't 243 * fit for purpose anymore by making the vcpu invalid. The VMM 244 * can try and fix it by re-initializing the vcpu with 245 * KVM_ARM_VCPU_INIT, however, this is likely not possible for 246 * protected VMs. 247 */ 248 vcpu->arch.target = -1; 249 *exit_code &= BIT(ARM_EXIT_WITH_SERROR_BIT); 250 *exit_code |= ARM_EXCEPTION_IL; 251 return false; 252 } 253 254 return true; 255 } 256 257 /* Switch to the guest for legacy non-VHE systems */ 258 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 259 { 260 struct kvm_cpu_context *host_ctxt; 261 struct kvm_cpu_context *guest_ctxt; 262 struct kvm_s2_mmu *mmu; 263 bool pmu_switch_needed; 264 u64 exit_code; 265 266 /* 267 * Having IRQs masked via PMR when entering the guest means the GIC 268 * will not signal the CPU of interrupts of lower priority, and the 269 * only way to get out will be via guest exceptions. 270 * Naturally, we want to avoid this. 271 */ 272 if (system_uses_irq_prio_masking()) { 273 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); 274 pmr_sync(); 275 } 276 277 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 278 host_ctxt->__hyp_running_vcpu = vcpu; 279 guest_ctxt = &vcpu->arch.ctxt; 280 281 pmu_switch_needed = __pmu_switch_to_guest(host_ctxt); 282 283 __sysreg_save_state_nvhe(host_ctxt); 284 /* 285 * We must flush and disable the SPE buffer for nVHE, as 286 * the translation regime(EL1&0) is going to be loaded with 287 * that of the guest. And we must do this before we change the 288 * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and 289 * before we load guest Stage1. 290 */ 291 __debug_save_host_buffers_nvhe(vcpu); 292 293 __kvm_adjust_pc(vcpu); 294 295 /* 296 * We must restore the 32-bit state before the sysregs, thanks 297 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72). 298 * 299 * Also, and in order to be able to deal with erratum #1319537 (A57) 300 * and #1319367 (A72), we must ensure that all VM-related sysreg are 301 * restored before we enable S2 translation. 302 */ 303 __sysreg32_restore_state(vcpu); 304 __sysreg_restore_state_nvhe(guest_ctxt); 305 306 mmu = kern_hyp_va(vcpu->arch.hw_mmu); 307 __load_stage2(mmu, kern_hyp_va(mmu->arch)); 308 __activate_traps(vcpu); 309 310 __hyp_vgic_restore_state(vcpu); 311 __timer_enable_traps(vcpu); 312 313 __debug_switch_to_guest(vcpu); 314 315 do { 316 /* Jump in the fire! */ 317 exit_code = __guest_enter(vcpu); 318 319 if (unlikely(!handle_aarch32_guest(vcpu, &exit_code))) 320 break; 321 322 /* And we're baaack! */ 323 } while (fixup_guest_exit(vcpu, &exit_code)); 324 325 __sysreg_save_state_nvhe(guest_ctxt); 326 __sysreg32_save_state(vcpu); 327 __timer_disable_traps(vcpu); 328 __hyp_vgic_save_state(vcpu); 329 330 __deactivate_traps(vcpu); 331 __load_host_stage2(); 332 333 __sysreg_restore_state_nvhe(host_ctxt); 334 335 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) 336 __fpsimd_save_fpexc32(vcpu); 337 338 __debug_switch_to_host(vcpu); 339 /* 340 * This must come after restoring the host sysregs, since a non-VHE 341 * system may enable SPE here and make use of the TTBRs. 342 */ 343 __debug_restore_host_buffers_nvhe(vcpu); 344 345 if (pmu_switch_needed) 346 __pmu_switch_to_host(host_ctxt); 347 348 /* Returning to host will clear PSR.I, remask PMR if needed */ 349 if (system_uses_irq_prio_masking()) 350 gic_write_pmr(GIC_PRIO_IRQOFF); 351 352 host_ctxt->__hyp_running_vcpu = NULL; 353 354 return exit_code; 355 } 356 357 void __noreturn hyp_panic(void) 358 { 359 u64 spsr = read_sysreg_el2(SYS_SPSR); 360 u64 elr = read_sysreg_el2(SYS_ELR); 361 u64 par = read_sysreg_par(); 362 struct kvm_cpu_context *host_ctxt; 363 struct kvm_vcpu *vcpu; 364 365 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 366 vcpu = host_ctxt->__hyp_running_vcpu; 367 368 if (vcpu) { 369 __timer_disable_traps(vcpu); 370 __deactivate_traps(vcpu); 371 __load_host_stage2(); 372 __sysreg_restore_state_nvhe(host_ctxt); 373 } 374 375 __hyp_do_panic(host_ctxt, spsr, elr, par); 376 unreachable(); 377 } 378 379 asmlinkage void kvm_unexpected_el2_exception(void) 380 { 381 return __kvm_unexpected_el2_exception(); 382 } 383