1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 #include <hyp/sysreg-sr.h> 9 10 #include <linux/arm-smccc.h> 11 #include <linux/kvm_host.h> 12 #include <linux/types.h> 13 #include <linux/jump_label.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 29 #include <nvhe/fixed_config.h> 30 #include <nvhe/mem_protect.h> 31 32 /* Non-VHE specific context */ 33 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 34 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 35 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 36 37 extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc); 38 39 static void __activate_traps(struct kvm_vcpu *vcpu) 40 { 41 u64 val; 42 43 ___activate_traps(vcpu); 44 __activate_traps_common(vcpu); 45 46 val = vcpu->arch.cptr_el2; 47 val |= CPTR_EL2_TTA | CPTR_EL2_TAM; 48 if (!guest_owns_fp_regs(vcpu)) { 49 val |= CPTR_EL2_TFP | CPTR_EL2_TZ; 50 __activate_traps_fpsimd32(vcpu); 51 } 52 if (cpus_have_final_cap(ARM64_SME)) 53 val |= CPTR_EL2_TSM; 54 55 write_sysreg(val, cptr_el2); 56 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); 57 58 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 59 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; 60 61 isb(); 62 /* 63 * At this stage, and thanks to the above isb(), S2 is 64 * configured and enabled. We can now restore the guest's S1 65 * configuration: SCTLR, and only then TCR. 66 */ 67 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR); 68 isb(); 69 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); 70 } 71 } 72 73 static void __deactivate_traps(struct kvm_vcpu *vcpu) 74 { 75 extern char __kvm_hyp_host_vector[]; 76 u64 cptr; 77 78 ___deactivate_traps(vcpu); 79 80 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 81 u64 val; 82 83 /* 84 * Set the TCR and SCTLR registers in the exact opposite 85 * sequence as __activate_traps (first prevent walks, 86 * then force the MMU on). A generous sprinkling of isb() 87 * ensure that things happen in this exact order. 88 */ 89 val = read_sysreg_el1(SYS_TCR); 90 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR); 91 isb(); 92 val = read_sysreg_el1(SYS_SCTLR); 93 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR); 94 isb(); 95 } 96 97 __deactivate_traps_common(vcpu); 98 99 write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2); 100 101 cptr = CPTR_EL2_DEFAULT; 102 if (vcpu_has_sve(vcpu) && (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED)) 103 cptr |= CPTR_EL2_TZ; 104 if (cpus_have_final_cap(ARM64_SME)) 105 cptr &= ~CPTR_EL2_TSM; 106 107 write_sysreg(cptr, cptr_el2); 108 write_sysreg(__kvm_hyp_host_vector, vbar_el2); 109 } 110 111 /* Save VGICv3 state on non-VHE systems */ 112 static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu) 113 { 114 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 115 __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3); 116 __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 117 } 118 } 119 120 /* Restore VGICv3 state on non-VHE systems */ 121 static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu) 122 { 123 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 124 __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 125 __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3); 126 } 127 } 128 129 /* 130 * Disable host events, enable guest events 131 */ 132 #ifdef CONFIG_HW_PERF_EVENTS 133 static bool __pmu_switch_to_guest(struct kvm_vcpu *vcpu) 134 { 135 struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; 136 137 if (pmu->events_host) 138 write_sysreg(pmu->events_host, pmcntenclr_el0); 139 140 if (pmu->events_guest) 141 write_sysreg(pmu->events_guest, pmcntenset_el0); 142 143 return (pmu->events_host || pmu->events_guest); 144 } 145 146 /* 147 * Disable guest events, enable host events 148 */ 149 static void __pmu_switch_to_host(struct kvm_vcpu *vcpu) 150 { 151 struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; 152 153 if (pmu->events_guest) 154 write_sysreg(pmu->events_guest, pmcntenclr_el0); 155 156 if (pmu->events_host) 157 write_sysreg(pmu->events_host, pmcntenset_el0); 158 } 159 #else 160 #define __pmu_switch_to_guest(v) ({ false; }) 161 #define __pmu_switch_to_host(v) do {} while (0) 162 #endif 163 164 /* 165 * Handler for protected VM MSR, MRS or System instruction execution in AArch64. 166 * 167 * Returns true if the hypervisor has handled the exit, and control should go 168 * back to the guest, or false if it hasn't. 169 */ 170 static bool kvm_handle_pvm_sys64(struct kvm_vcpu *vcpu, u64 *exit_code) 171 { 172 /* 173 * Make sure we handle the exit for workarounds and ptrauth 174 * before the pKVM handling, as the latter could decide to 175 * UNDEF. 176 */ 177 return (kvm_hyp_handle_sysreg(vcpu, exit_code) || 178 kvm_handle_pvm_sysreg(vcpu, exit_code)); 179 } 180 181 static const exit_handler_fn hyp_exit_handlers[] = { 182 [0 ... ESR_ELx_EC_MAX] = NULL, 183 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 184 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 185 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 186 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 187 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 188 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 189 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low, 190 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth, 191 }; 192 193 static const exit_handler_fn pvm_exit_handlers[] = { 194 [0 ... ESR_ELx_EC_MAX] = NULL, 195 [ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64, 196 [ESR_ELx_EC_SVE] = kvm_handle_pvm_restricted, 197 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 198 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 199 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 200 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low, 201 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth, 202 }; 203 204 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 205 { 206 if (unlikely(kvm_vm_is_protected(kern_hyp_va(vcpu->kvm)))) 207 return pvm_exit_handlers; 208 209 return hyp_exit_handlers; 210 } 211 212 /* 213 * Some guests (e.g., protected VMs) are not be allowed to run in AArch32. 214 * The ARMv8 architecture does not give the hypervisor a mechanism to prevent a 215 * guest from dropping to AArch32 EL0 if implemented by the CPU. If the 216 * hypervisor spots a guest in such a state ensure it is handled, and don't 217 * trust the host to spot or fix it. The check below is based on the one in 218 * kvm_arch_vcpu_ioctl_run(). 219 * 220 * Returns false if the guest ran in AArch32 when it shouldn't have, and 221 * thus should exit to the host, or true if a the guest run loop can continue. 222 */ 223 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code) 224 { 225 struct kvm *kvm = kern_hyp_va(vcpu->kvm); 226 227 if (kvm_vm_is_protected(kvm) && vcpu_mode_is_32bit(vcpu)) { 228 /* 229 * As we have caught the guest red-handed, decide that it isn't 230 * fit for purpose anymore by making the vcpu invalid. The VMM 231 * can try and fix it by re-initializing the vcpu with 232 * KVM_ARM_VCPU_INIT, however, this is likely not possible for 233 * protected VMs. 234 */ 235 vcpu->arch.target = -1; 236 *exit_code &= BIT(ARM_EXIT_WITH_SERROR_BIT); 237 *exit_code |= ARM_EXCEPTION_IL; 238 } 239 } 240 241 /* Switch to the guest for legacy non-VHE systems */ 242 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 243 { 244 struct kvm_cpu_context *host_ctxt; 245 struct kvm_cpu_context *guest_ctxt; 246 struct kvm_s2_mmu *mmu; 247 bool pmu_switch_needed; 248 u64 exit_code; 249 250 /* 251 * Having IRQs masked via PMR when entering the guest means the GIC 252 * will not signal the CPU of interrupts of lower priority, and the 253 * only way to get out will be via guest exceptions. 254 * Naturally, we want to avoid this. 255 */ 256 if (system_uses_irq_prio_masking()) { 257 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); 258 pmr_sync(); 259 } 260 261 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 262 host_ctxt->__hyp_running_vcpu = vcpu; 263 guest_ctxt = &vcpu->arch.ctxt; 264 265 pmu_switch_needed = __pmu_switch_to_guest(vcpu); 266 267 __sysreg_save_state_nvhe(host_ctxt); 268 /* 269 * We must flush and disable the SPE buffer for nVHE, as 270 * the translation regime(EL1&0) is going to be loaded with 271 * that of the guest. And we must do this before we change the 272 * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and 273 * before we load guest Stage1. 274 */ 275 __debug_save_host_buffers_nvhe(vcpu); 276 277 /* 278 * We're about to restore some new MMU state. Make sure 279 * ongoing page-table walks that have started before we 280 * trapped to EL2 have completed. This also synchronises the 281 * above disabling of SPE and TRBE. 282 * 283 * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", 284 * rule R_LFHQG and subsequent information statements. 285 */ 286 dsb(nsh); 287 288 __kvm_adjust_pc(vcpu); 289 290 /* 291 * We must restore the 32-bit state before the sysregs, thanks 292 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72). 293 * 294 * Also, and in order to be able to deal with erratum #1319537 (A57) 295 * and #1319367 (A72), we must ensure that all VM-related sysreg are 296 * restored before we enable S2 translation. 297 */ 298 __sysreg32_restore_state(vcpu); 299 __sysreg_restore_state_nvhe(guest_ctxt); 300 301 mmu = kern_hyp_va(vcpu->arch.hw_mmu); 302 __load_stage2(mmu, kern_hyp_va(mmu->arch)); 303 __activate_traps(vcpu); 304 305 __hyp_vgic_restore_state(vcpu); 306 __timer_enable_traps(vcpu); 307 308 __debug_switch_to_guest(vcpu); 309 310 do { 311 /* Jump in the fire! */ 312 exit_code = __guest_enter(vcpu); 313 314 /* And we're baaack! */ 315 } while (fixup_guest_exit(vcpu, &exit_code)); 316 317 __sysreg_save_state_nvhe(guest_ctxt); 318 __sysreg32_save_state(vcpu); 319 __timer_disable_traps(vcpu); 320 __hyp_vgic_save_state(vcpu); 321 322 /* 323 * Same thing as before the guest run: we're about to switch 324 * the MMU context, so let's make sure we don't have any 325 * ongoing EL1&0 translations. 326 */ 327 dsb(nsh); 328 329 __deactivate_traps(vcpu); 330 __load_host_stage2(); 331 332 __sysreg_restore_state_nvhe(host_ctxt); 333 334 if (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED) 335 __fpsimd_save_fpexc32(vcpu); 336 337 __debug_switch_to_host(vcpu); 338 /* 339 * This must come after restoring the host sysregs, since a non-VHE 340 * system may enable SPE here and make use of the TTBRs. 341 */ 342 __debug_restore_host_buffers_nvhe(vcpu); 343 344 if (pmu_switch_needed) 345 __pmu_switch_to_host(vcpu); 346 347 /* Returning to host will clear PSR.I, remask PMR if needed */ 348 if (system_uses_irq_prio_masking()) 349 gic_write_pmr(GIC_PRIO_IRQOFF); 350 351 host_ctxt->__hyp_running_vcpu = NULL; 352 353 return exit_code; 354 } 355 356 asmlinkage void __noreturn hyp_panic(void) 357 { 358 u64 spsr = read_sysreg_el2(SYS_SPSR); 359 u64 elr = read_sysreg_el2(SYS_ELR); 360 u64 par = read_sysreg_par(); 361 struct kvm_cpu_context *host_ctxt; 362 struct kvm_vcpu *vcpu; 363 364 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 365 vcpu = host_ctxt->__hyp_running_vcpu; 366 367 if (vcpu) { 368 __timer_disable_traps(vcpu); 369 __deactivate_traps(vcpu); 370 __load_host_stage2(); 371 __sysreg_restore_state_nvhe(host_ctxt); 372 } 373 374 /* Prepare to dump kvm nvhe hyp stacktrace */ 375 kvm_nvhe_prepare_backtrace((unsigned long)__builtin_frame_address(0), 376 _THIS_IP_); 377 378 __hyp_do_panic(host_ctxt, spsr, elr, par); 379 unreachable(); 380 } 381 382 asmlinkage void __noreturn hyp_panic_bad_stack(void) 383 { 384 hyp_panic(); 385 } 386 387 asmlinkage void kvm_unexpected_el2_exception(void) 388 { 389 __kvm_unexpected_el2_exception(); 390 } 391