1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 #include <hyp/sysreg-sr.h> 9 10 #include <linux/arm-smccc.h> 11 #include <linux/kvm_host.h> 12 #include <linux/types.h> 13 #include <linux/jump_label.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 #include <asm/thread_info.h> 29 30 /* Non-VHE specific context */ 31 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 32 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 33 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 34 35 static void __activate_traps(struct kvm_vcpu *vcpu) 36 { 37 u64 val; 38 39 ___activate_traps(vcpu); 40 __activate_traps_common(vcpu); 41 42 val = CPTR_EL2_DEFAULT; 43 val |= CPTR_EL2_TTA | CPTR_EL2_TZ | CPTR_EL2_TAM; 44 if (!update_fp_enabled(vcpu)) { 45 val |= CPTR_EL2_TFP; 46 __activate_traps_fpsimd32(vcpu); 47 } 48 49 write_sysreg(val, cptr_el2); 50 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); 51 52 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 53 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; 54 55 isb(); 56 /* 57 * At this stage, and thanks to the above isb(), S2 is 58 * configured and enabled. We can now restore the guest's S1 59 * configuration: SCTLR, and only then TCR. 60 */ 61 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR); 62 isb(); 63 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); 64 } 65 } 66 67 static void __deactivate_traps(struct kvm_vcpu *vcpu) 68 { 69 extern char __kvm_hyp_host_vector[]; 70 u64 mdcr_el2; 71 72 ___deactivate_traps(vcpu); 73 74 mdcr_el2 = read_sysreg(mdcr_el2); 75 76 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 77 u64 val; 78 79 /* 80 * Set the TCR and SCTLR registers in the exact opposite 81 * sequence as __activate_traps (first prevent walks, 82 * then force the MMU on). A generous sprinkling of isb() 83 * ensure that things happen in this exact order. 84 */ 85 val = read_sysreg_el1(SYS_TCR); 86 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR); 87 isb(); 88 val = read_sysreg_el1(SYS_SCTLR); 89 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR); 90 isb(); 91 } 92 93 __deactivate_traps_common(); 94 95 mdcr_el2 &= MDCR_EL2_HPMN_MASK; 96 mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT; 97 98 write_sysreg(mdcr_el2, mdcr_el2); 99 write_sysreg(HCR_HOST_NVHE_FLAGS, hcr_el2); 100 write_sysreg(CPTR_EL2_DEFAULT, cptr_el2); 101 write_sysreg(__kvm_hyp_host_vector, vbar_el2); 102 } 103 104 static void __load_host_stage2(void) 105 { 106 write_sysreg(0, vttbr_el2); 107 } 108 109 /* Save VGICv3 state on non-VHE systems */ 110 static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu) 111 { 112 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 113 __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3); 114 __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 115 } 116 } 117 118 /* Restore VGICv3 state on non_VEH systems */ 119 static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu) 120 { 121 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 122 __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 123 __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3); 124 } 125 } 126 127 /** 128 * Disable host events, enable guest events 129 */ 130 static bool __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt) 131 { 132 struct kvm_host_data *host; 133 struct kvm_pmu_events *pmu; 134 135 host = container_of(host_ctxt, struct kvm_host_data, host_ctxt); 136 pmu = &host->pmu_events; 137 138 if (pmu->events_host) 139 write_sysreg(pmu->events_host, pmcntenclr_el0); 140 141 if (pmu->events_guest) 142 write_sysreg(pmu->events_guest, pmcntenset_el0); 143 144 return (pmu->events_host || pmu->events_guest); 145 } 146 147 /** 148 * Disable guest events, enable host events 149 */ 150 static void __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt) 151 { 152 struct kvm_host_data *host; 153 struct kvm_pmu_events *pmu; 154 155 host = container_of(host_ctxt, struct kvm_host_data, host_ctxt); 156 pmu = &host->pmu_events; 157 158 if (pmu->events_guest) 159 write_sysreg(pmu->events_guest, pmcntenclr_el0); 160 161 if (pmu->events_host) 162 write_sysreg(pmu->events_host, pmcntenset_el0); 163 } 164 165 /* Switch to the guest for legacy non-VHE systems */ 166 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 167 { 168 struct kvm_cpu_context *host_ctxt; 169 struct kvm_cpu_context *guest_ctxt; 170 bool pmu_switch_needed; 171 u64 exit_code; 172 173 /* 174 * Having IRQs masked via PMR when entering the guest means the GIC 175 * will not signal the CPU of interrupts of lower priority, and the 176 * only way to get out will be via guest exceptions. 177 * Naturally, we want to avoid this. 178 */ 179 if (system_uses_irq_prio_masking()) { 180 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); 181 pmr_sync(); 182 } 183 184 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 185 host_ctxt->__hyp_running_vcpu = vcpu; 186 guest_ctxt = &vcpu->arch.ctxt; 187 188 pmu_switch_needed = __pmu_switch_to_guest(host_ctxt); 189 190 __sysreg_save_state_nvhe(host_ctxt); 191 192 /* 193 * We must restore the 32-bit state before the sysregs, thanks 194 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72). 195 * 196 * Also, and in order to be able to deal with erratum #1319537 (A57) 197 * and #1319367 (A72), we must ensure that all VM-related sysreg are 198 * restored before we enable S2 translation. 199 */ 200 __sysreg32_restore_state(vcpu); 201 __sysreg_restore_state_nvhe(guest_ctxt); 202 203 __load_guest_stage2(kern_hyp_va(vcpu->arch.hw_mmu)); 204 __activate_traps(vcpu); 205 206 __hyp_vgic_restore_state(vcpu); 207 __timer_enable_traps(vcpu); 208 209 __debug_switch_to_guest(vcpu); 210 211 do { 212 /* Jump in the fire! */ 213 exit_code = __guest_enter(vcpu); 214 215 /* And we're baaack! */ 216 } while (fixup_guest_exit(vcpu, &exit_code)); 217 218 __sysreg_save_state_nvhe(guest_ctxt); 219 __sysreg32_save_state(vcpu); 220 __timer_disable_traps(vcpu); 221 __hyp_vgic_save_state(vcpu); 222 223 __deactivate_traps(vcpu); 224 __load_host_stage2(); 225 226 __sysreg_restore_state_nvhe(host_ctxt); 227 228 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) 229 __fpsimd_save_fpexc32(vcpu); 230 231 /* 232 * This must come after restoring the host sysregs, since a non-VHE 233 * system may enable SPE here and make use of the TTBRs. 234 */ 235 __debug_switch_to_host(vcpu); 236 237 if (pmu_switch_needed) 238 __pmu_switch_to_host(host_ctxt); 239 240 /* Returning to host will clear PSR.I, remask PMR if needed */ 241 if (system_uses_irq_prio_masking()) 242 gic_write_pmr(GIC_PRIO_IRQOFF); 243 244 host_ctxt->__hyp_running_vcpu = NULL; 245 246 return exit_code; 247 } 248 249 void __noreturn hyp_panic(void) 250 { 251 u64 spsr = read_sysreg_el2(SYS_SPSR); 252 u64 elr = read_sysreg_el2(SYS_ELR); 253 u64 par = read_sysreg_par(); 254 bool restore_host = true; 255 struct kvm_cpu_context *host_ctxt; 256 struct kvm_vcpu *vcpu; 257 258 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 259 vcpu = host_ctxt->__hyp_running_vcpu; 260 261 if (vcpu) { 262 __timer_disable_traps(vcpu); 263 __deactivate_traps(vcpu); 264 __load_host_stage2(); 265 __sysreg_restore_state_nvhe(host_ctxt); 266 } 267 268 __hyp_do_panic(restore_host, spsr, elr, par); 269 unreachable(); 270 } 271 272 asmlinkage void kvm_unexpected_el2_exception(void) 273 { 274 return __kvm_unexpected_el2_exception(); 275 } 276