1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 #include <hyp/sysreg-sr.h> 9 10 #include <linux/arm-smccc.h> 11 #include <linux/kvm_host.h> 12 #include <linux/types.h> 13 #include <linux/jump_label.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 29 #include <nvhe/fixed_config.h> 30 #include <nvhe/mem_protect.h> 31 32 /* Non-VHE specific context */ 33 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 34 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 35 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 36 37 static void __activate_traps(struct kvm_vcpu *vcpu) 38 { 39 u64 val; 40 41 ___activate_traps(vcpu); 42 __activate_traps_common(vcpu); 43 44 val = vcpu->arch.cptr_el2; 45 val |= CPTR_EL2_TTA | CPTR_EL2_TAM; 46 if (!update_fp_enabled(vcpu)) { 47 val |= CPTR_EL2_TFP | CPTR_EL2_TZ; 48 __activate_traps_fpsimd32(vcpu); 49 } 50 if (cpus_have_final_cap(ARM64_SME)) 51 val |= CPTR_EL2_TSM; 52 53 write_sysreg(val, cptr_el2); 54 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); 55 56 if (cpus_have_final_cap(ARM64_SME)) { 57 val = read_sysreg_s(SYS_HFGRTR_EL2); 58 val &= ~(HFGxTR_EL2_nTPIDR2_EL0_MASK | 59 HFGxTR_EL2_nSMPRI_EL1_MASK); 60 write_sysreg_s(val, SYS_HFGRTR_EL2); 61 62 val = read_sysreg_s(SYS_HFGWTR_EL2); 63 val &= ~(HFGxTR_EL2_nTPIDR2_EL0_MASK | 64 HFGxTR_EL2_nSMPRI_EL1_MASK); 65 write_sysreg_s(val, SYS_HFGWTR_EL2); 66 } 67 68 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 69 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; 70 71 isb(); 72 /* 73 * At this stage, and thanks to the above isb(), S2 is 74 * configured and enabled. We can now restore the guest's S1 75 * configuration: SCTLR, and only then TCR. 76 */ 77 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR); 78 isb(); 79 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); 80 } 81 } 82 83 static void __deactivate_traps(struct kvm_vcpu *vcpu) 84 { 85 extern char __kvm_hyp_host_vector[]; 86 u64 cptr; 87 88 ___deactivate_traps(vcpu); 89 90 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 91 u64 val; 92 93 /* 94 * Set the TCR and SCTLR registers in the exact opposite 95 * sequence as __activate_traps (first prevent walks, 96 * then force the MMU on). A generous sprinkling of isb() 97 * ensure that things happen in this exact order. 98 */ 99 val = read_sysreg_el1(SYS_TCR); 100 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR); 101 isb(); 102 val = read_sysreg_el1(SYS_SCTLR); 103 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR); 104 isb(); 105 } 106 107 __deactivate_traps_common(vcpu); 108 109 write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2); 110 111 if (cpus_have_final_cap(ARM64_SME)) { 112 u64 val; 113 114 val = read_sysreg_s(SYS_HFGRTR_EL2); 115 val |= HFGxTR_EL2_nTPIDR2_EL0_MASK | 116 HFGxTR_EL2_nSMPRI_EL1_MASK; 117 write_sysreg_s(val, SYS_HFGRTR_EL2); 118 119 val = read_sysreg_s(SYS_HFGWTR_EL2); 120 val |= HFGxTR_EL2_nTPIDR2_EL0_MASK | 121 HFGxTR_EL2_nSMPRI_EL1_MASK; 122 write_sysreg_s(val, SYS_HFGWTR_EL2); 123 } 124 125 cptr = CPTR_EL2_DEFAULT; 126 if (vcpu_has_sve(vcpu) && (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)) 127 cptr |= CPTR_EL2_TZ; 128 if (cpus_have_final_cap(ARM64_SME)) 129 cptr &= ~CPTR_EL2_TSM; 130 131 write_sysreg(cptr, cptr_el2); 132 write_sysreg(__kvm_hyp_host_vector, vbar_el2); 133 } 134 135 /* Save VGICv3 state on non-VHE systems */ 136 static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu) 137 { 138 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 139 __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3); 140 __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 141 } 142 } 143 144 /* Restore VGICv3 state on non_VEH systems */ 145 static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu) 146 { 147 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 148 __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 149 __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3); 150 } 151 } 152 153 /* 154 * Disable host events, enable guest events 155 */ 156 #ifdef CONFIG_HW_PERF_EVENTS 157 static bool __pmu_switch_to_guest(struct kvm_vcpu *vcpu) 158 { 159 struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; 160 161 if (pmu->events_host) 162 write_sysreg(pmu->events_host, pmcntenclr_el0); 163 164 if (pmu->events_guest) 165 write_sysreg(pmu->events_guest, pmcntenset_el0); 166 167 return (pmu->events_host || pmu->events_guest); 168 } 169 170 /* 171 * Disable guest events, enable host events 172 */ 173 static void __pmu_switch_to_host(struct kvm_vcpu *vcpu) 174 { 175 struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; 176 177 if (pmu->events_guest) 178 write_sysreg(pmu->events_guest, pmcntenclr_el0); 179 180 if (pmu->events_host) 181 write_sysreg(pmu->events_host, pmcntenset_el0); 182 } 183 #else 184 #define __pmu_switch_to_guest(v) ({ false; }) 185 #define __pmu_switch_to_host(v) do {} while (0) 186 #endif 187 188 /* 189 * Handler for protected VM MSR, MRS or System instruction execution in AArch64. 190 * 191 * Returns true if the hypervisor has handled the exit, and control should go 192 * back to the guest, or false if it hasn't. 193 */ 194 static bool kvm_handle_pvm_sys64(struct kvm_vcpu *vcpu, u64 *exit_code) 195 { 196 /* 197 * Make sure we handle the exit for workarounds and ptrauth 198 * before the pKVM handling, as the latter could decide to 199 * UNDEF. 200 */ 201 return (kvm_hyp_handle_sysreg(vcpu, exit_code) || 202 kvm_handle_pvm_sysreg(vcpu, exit_code)); 203 } 204 205 static const exit_handler_fn hyp_exit_handlers[] = { 206 [0 ... ESR_ELx_EC_MAX] = NULL, 207 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 208 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 209 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 210 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 211 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 212 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 213 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth, 214 }; 215 216 static const exit_handler_fn pvm_exit_handlers[] = { 217 [0 ... ESR_ELx_EC_MAX] = NULL, 218 [ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64, 219 [ESR_ELx_EC_SVE] = kvm_handle_pvm_restricted, 220 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 221 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 222 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 223 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth, 224 }; 225 226 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 227 { 228 if (unlikely(kvm_vm_is_protected(kern_hyp_va(vcpu->kvm)))) 229 return pvm_exit_handlers; 230 231 return hyp_exit_handlers; 232 } 233 234 /* 235 * Some guests (e.g., protected VMs) are not be allowed to run in AArch32. 236 * The ARMv8 architecture does not give the hypervisor a mechanism to prevent a 237 * guest from dropping to AArch32 EL0 if implemented by the CPU. If the 238 * hypervisor spots a guest in such a state ensure it is handled, and don't 239 * trust the host to spot or fix it. The check below is based on the one in 240 * kvm_arch_vcpu_ioctl_run(). 241 * 242 * Returns false if the guest ran in AArch32 when it shouldn't have, and 243 * thus should exit to the host, or true if a the guest run loop can continue. 244 */ 245 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code) 246 { 247 struct kvm *kvm = kern_hyp_va(vcpu->kvm); 248 249 if (kvm_vm_is_protected(kvm) && vcpu_mode_is_32bit(vcpu)) { 250 /* 251 * As we have caught the guest red-handed, decide that it isn't 252 * fit for purpose anymore by making the vcpu invalid. The VMM 253 * can try and fix it by re-initializing the vcpu with 254 * KVM_ARM_VCPU_INIT, however, this is likely not possible for 255 * protected VMs. 256 */ 257 vcpu->arch.target = -1; 258 *exit_code &= BIT(ARM_EXIT_WITH_SERROR_BIT); 259 *exit_code |= ARM_EXCEPTION_IL; 260 } 261 } 262 263 /* Switch to the guest for legacy non-VHE systems */ 264 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 265 { 266 struct kvm_cpu_context *host_ctxt; 267 struct kvm_cpu_context *guest_ctxt; 268 struct kvm_s2_mmu *mmu; 269 bool pmu_switch_needed; 270 u64 exit_code; 271 272 /* 273 * Having IRQs masked via PMR when entering the guest means the GIC 274 * will not signal the CPU of interrupts of lower priority, and the 275 * only way to get out will be via guest exceptions. 276 * Naturally, we want to avoid this. 277 */ 278 if (system_uses_irq_prio_masking()) { 279 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); 280 pmr_sync(); 281 } 282 283 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 284 host_ctxt->__hyp_running_vcpu = vcpu; 285 guest_ctxt = &vcpu->arch.ctxt; 286 287 pmu_switch_needed = __pmu_switch_to_guest(vcpu); 288 289 __sysreg_save_state_nvhe(host_ctxt); 290 /* 291 * We must flush and disable the SPE buffer for nVHE, as 292 * the translation regime(EL1&0) is going to be loaded with 293 * that of the guest. And we must do this before we change the 294 * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and 295 * before we load guest Stage1. 296 */ 297 __debug_save_host_buffers_nvhe(vcpu); 298 299 __kvm_adjust_pc(vcpu); 300 301 /* 302 * We must restore the 32-bit state before the sysregs, thanks 303 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72). 304 * 305 * Also, and in order to be able to deal with erratum #1319537 (A57) 306 * and #1319367 (A72), we must ensure that all VM-related sysreg are 307 * restored before we enable S2 translation. 308 */ 309 __sysreg32_restore_state(vcpu); 310 __sysreg_restore_state_nvhe(guest_ctxt); 311 312 mmu = kern_hyp_va(vcpu->arch.hw_mmu); 313 __load_stage2(mmu, kern_hyp_va(mmu->arch)); 314 __activate_traps(vcpu); 315 316 __hyp_vgic_restore_state(vcpu); 317 __timer_enable_traps(vcpu); 318 319 __debug_switch_to_guest(vcpu); 320 321 do { 322 /* Jump in the fire! */ 323 exit_code = __guest_enter(vcpu); 324 325 /* And we're baaack! */ 326 } while (fixup_guest_exit(vcpu, &exit_code)); 327 328 __sysreg_save_state_nvhe(guest_ctxt); 329 __sysreg32_save_state(vcpu); 330 __timer_disable_traps(vcpu); 331 __hyp_vgic_save_state(vcpu); 332 333 __deactivate_traps(vcpu); 334 __load_host_stage2(); 335 336 __sysreg_restore_state_nvhe(host_ctxt); 337 338 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) 339 __fpsimd_save_fpexc32(vcpu); 340 341 __debug_switch_to_host(vcpu); 342 /* 343 * This must come after restoring the host sysregs, since a non-VHE 344 * system may enable SPE here and make use of the TTBRs. 345 */ 346 __debug_restore_host_buffers_nvhe(vcpu); 347 348 if (pmu_switch_needed) 349 __pmu_switch_to_host(vcpu); 350 351 /* Returning to host will clear PSR.I, remask PMR if needed */ 352 if (system_uses_irq_prio_masking()) 353 gic_write_pmr(GIC_PRIO_IRQOFF); 354 355 host_ctxt->__hyp_running_vcpu = NULL; 356 357 return exit_code; 358 } 359 360 asmlinkage void __noreturn hyp_panic(void) 361 { 362 u64 spsr = read_sysreg_el2(SYS_SPSR); 363 u64 elr = read_sysreg_el2(SYS_ELR); 364 u64 par = read_sysreg_par(); 365 struct kvm_cpu_context *host_ctxt; 366 struct kvm_vcpu *vcpu; 367 368 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 369 vcpu = host_ctxt->__hyp_running_vcpu; 370 371 if (vcpu) { 372 __timer_disable_traps(vcpu); 373 __deactivate_traps(vcpu); 374 __load_host_stage2(); 375 __sysreg_restore_state_nvhe(host_ctxt); 376 } 377 378 __hyp_do_panic(host_ctxt, spsr, elr, par); 379 unreachable(); 380 } 381 382 asmlinkage void __noreturn hyp_panic_bad_stack(void) 383 { 384 hyp_panic(); 385 } 386 387 asmlinkage void kvm_unexpected_el2_exception(void) 388 { 389 return __kvm_unexpected_el2_exception(); 390 } 391