109cf57ebSDavid Brazdil // SPDX-License-Identifier: GPL-2.0-only 209cf57ebSDavid Brazdil /* 309cf57ebSDavid Brazdil * Copyright (C) 2015 - ARM Ltd 409cf57ebSDavid Brazdil * Author: Marc Zyngier <marc.zyngier@arm.com> 509cf57ebSDavid Brazdil */ 609cf57ebSDavid Brazdil 7cdb5e02eSMarc Zyngier #include <hyp/adjust_pc.h> 809cf57ebSDavid Brazdil #include <hyp/switch.h> 913aeb9b4SDavid Brazdil #include <hyp/sysreg-sr.h> 1009cf57ebSDavid Brazdil 1109cf57ebSDavid Brazdil #include <linux/arm-smccc.h> 1209cf57ebSDavid Brazdil #include <linux/kvm_host.h> 1309cf57ebSDavid Brazdil #include <linux/types.h> 1409cf57ebSDavid Brazdil #include <linux/jump_label.h> 1509cf57ebSDavid Brazdil #include <uapi/linux/psci.h> 1609cf57ebSDavid Brazdil 1709cf57ebSDavid Brazdil #include <kvm/arm_psci.h> 1809cf57ebSDavid Brazdil 1909cf57ebSDavid Brazdil #include <asm/barrier.h> 2009cf57ebSDavid Brazdil #include <asm/cpufeature.h> 2109cf57ebSDavid Brazdil #include <asm/kprobes.h> 2209cf57ebSDavid Brazdil #include <asm/kvm_asm.h> 2309cf57ebSDavid Brazdil #include <asm/kvm_emulate.h> 2409cf57ebSDavid Brazdil #include <asm/kvm_hyp.h> 2509cf57ebSDavid Brazdil #include <asm/kvm_mmu.h> 2609cf57ebSDavid Brazdil #include <asm/fpsimd.h> 2709cf57ebSDavid Brazdil #include <asm/debug-monitors.h> 2809cf57ebSDavid Brazdil #include <asm/processor.h> 2909cf57ebSDavid Brazdil #include <asm/thread_info.h> 3009cf57ebSDavid Brazdil 3114ef9d04SMarc Zyngier /* Non-VHE specific context */ 3214ef9d04SMarc Zyngier DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 3314ef9d04SMarc Zyngier DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 3414ef9d04SMarc Zyngier DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 352a1198c9SDavid Brazdil 36c50cb043SDavid Brazdil static void __activate_traps(struct kvm_vcpu *vcpu) 3709cf57ebSDavid Brazdil { 3809cf57ebSDavid Brazdil u64 val; 3909cf57ebSDavid Brazdil 4009cf57ebSDavid Brazdil ___activate_traps(vcpu); 4109cf57ebSDavid Brazdil __activate_traps_common(vcpu); 4209cf57ebSDavid Brazdil 4309cf57ebSDavid Brazdil val = CPTR_EL2_DEFAULT; 4409cf57ebSDavid Brazdil val |= CPTR_EL2_TTA | CPTR_EL2_TZ | CPTR_EL2_TAM; 4509cf57ebSDavid Brazdil if (!update_fp_enabled(vcpu)) { 4609cf57ebSDavid Brazdil val |= CPTR_EL2_TFP; 4709cf57ebSDavid Brazdil __activate_traps_fpsimd32(vcpu); 4809cf57ebSDavid Brazdil } 4909cf57ebSDavid Brazdil 5009cf57ebSDavid Brazdil write_sysreg(val, cptr_el2); 5114ef9d04SMarc Zyngier write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); 5209cf57ebSDavid Brazdil 5309cf57ebSDavid Brazdil if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 5409cf57ebSDavid Brazdil struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; 5509cf57ebSDavid Brazdil 5609cf57ebSDavid Brazdil isb(); 5709cf57ebSDavid Brazdil /* 5809cf57ebSDavid Brazdil * At this stage, and thanks to the above isb(), S2 is 5909cf57ebSDavid Brazdil * configured and enabled. We can now restore the guest's S1 6009cf57ebSDavid Brazdil * configuration: SCTLR, and only then TCR. 6109cf57ebSDavid Brazdil */ 6271071acfSMarc Zyngier write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR); 6309cf57ebSDavid Brazdil isb(); 6471071acfSMarc Zyngier write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); 6509cf57ebSDavid Brazdil } 6609cf57ebSDavid Brazdil } 6709cf57ebSDavid Brazdil 68c50cb043SDavid Brazdil static void __deactivate_traps(struct kvm_vcpu *vcpu) 6909cf57ebSDavid Brazdil { 706e3bfbb2SAndrew Scull extern char __kvm_hyp_host_vector[]; 71*beed0906SMarc Zyngier u64 mdcr_el2, cptr; 7209cf57ebSDavid Brazdil 7309cf57ebSDavid Brazdil ___deactivate_traps(vcpu); 7409cf57ebSDavid Brazdil 7509cf57ebSDavid Brazdil mdcr_el2 = read_sysreg(mdcr_el2); 7609cf57ebSDavid Brazdil 7709cf57ebSDavid Brazdil if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 7809cf57ebSDavid Brazdil u64 val; 7909cf57ebSDavid Brazdil 8009cf57ebSDavid Brazdil /* 8109cf57ebSDavid Brazdil * Set the TCR and SCTLR registers in the exact opposite 8209cf57ebSDavid Brazdil * sequence as __activate_traps (first prevent walks, 8309cf57ebSDavid Brazdil * then force the MMU on). A generous sprinkling of isb() 8409cf57ebSDavid Brazdil * ensure that things happen in this exact order. 8509cf57ebSDavid Brazdil */ 8609cf57ebSDavid Brazdil val = read_sysreg_el1(SYS_TCR); 8709cf57ebSDavid Brazdil write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR); 8809cf57ebSDavid Brazdil isb(); 8909cf57ebSDavid Brazdil val = read_sysreg_el1(SYS_SCTLR); 9009cf57ebSDavid Brazdil write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR); 9109cf57ebSDavid Brazdil isb(); 9209cf57ebSDavid Brazdil } 9309cf57ebSDavid Brazdil 9409cf57ebSDavid Brazdil __deactivate_traps_common(); 9509cf57ebSDavid Brazdil 9609cf57ebSDavid Brazdil mdcr_el2 &= MDCR_EL2_HPMN_MASK; 9709cf57ebSDavid Brazdil mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT; 9809cf57ebSDavid Brazdil 9909cf57ebSDavid Brazdil write_sysreg(mdcr_el2, mdcr_el2); 100b93c17c4SDavid Brazdil if (is_protected_kvm_enabled()) 101b93c17c4SDavid Brazdil write_sysreg(HCR_HOST_NVHE_PROTECTED_FLAGS, hcr_el2); 102b93c17c4SDavid Brazdil else 10309cf57ebSDavid Brazdil write_sysreg(HCR_HOST_NVHE_FLAGS, hcr_el2); 104*beed0906SMarc Zyngier 105*beed0906SMarc Zyngier cptr = CPTR_EL2_DEFAULT; 106*beed0906SMarc Zyngier if (vcpu_has_sve(vcpu) && (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)) 107*beed0906SMarc Zyngier cptr |= CPTR_EL2_TZ; 108*beed0906SMarc Zyngier 109*beed0906SMarc Zyngier write_sysreg(cptr, cptr_el2); 1106e3bfbb2SAndrew Scull write_sysreg(__kvm_hyp_host_vector, vbar_el2); 11109cf57ebSDavid Brazdil } 11209cf57ebSDavid Brazdil 113501a67a2SAndrew Scull static void __load_host_stage2(void) 11409cf57ebSDavid Brazdil { 11509cf57ebSDavid Brazdil write_sysreg(0, vttbr_el2); 11609cf57ebSDavid Brazdil } 11709cf57ebSDavid Brazdil 11809cf57ebSDavid Brazdil /* Save VGICv3 state on non-VHE systems */ 119c50cb043SDavid Brazdil static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu) 12009cf57ebSDavid Brazdil { 12109cf57ebSDavid Brazdil if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 12209cf57ebSDavid Brazdil __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3); 12309cf57ebSDavid Brazdil __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 12409cf57ebSDavid Brazdil } 12509cf57ebSDavid Brazdil } 12609cf57ebSDavid Brazdil 12709cf57ebSDavid Brazdil /* Restore VGICv3 state on non_VEH systems */ 128c50cb043SDavid Brazdil static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu) 12909cf57ebSDavid Brazdil { 13009cf57ebSDavid Brazdil if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 13109cf57ebSDavid Brazdil __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 13209cf57ebSDavid Brazdil __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3); 13309cf57ebSDavid Brazdil } 13409cf57ebSDavid Brazdil } 13509cf57ebSDavid Brazdil 13609cf57ebSDavid Brazdil /** 13709cf57ebSDavid Brazdil * Disable host events, enable guest events 13809cf57ebSDavid Brazdil */ 139c50cb043SDavid Brazdil static bool __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt) 14009cf57ebSDavid Brazdil { 14109cf57ebSDavid Brazdil struct kvm_host_data *host; 14209cf57ebSDavid Brazdil struct kvm_pmu_events *pmu; 14309cf57ebSDavid Brazdil 14409cf57ebSDavid Brazdil host = container_of(host_ctxt, struct kvm_host_data, host_ctxt); 14509cf57ebSDavid Brazdil pmu = &host->pmu_events; 14609cf57ebSDavid Brazdil 14709cf57ebSDavid Brazdil if (pmu->events_host) 14809cf57ebSDavid Brazdil write_sysreg(pmu->events_host, pmcntenclr_el0); 14909cf57ebSDavid Brazdil 15009cf57ebSDavid Brazdil if (pmu->events_guest) 15109cf57ebSDavid Brazdil write_sysreg(pmu->events_guest, pmcntenset_el0); 15209cf57ebSDavid Brazdil 15309cf57ebSDavid Brazdil return (pmu->events_host || pmu->events_guest); 15409cf57ebSDavid Brazdil } 15509cf57ebSDavid Brazdil 15609cf57ebSDavid Brazdil /** 15709cf57ebSDavid Brazdil * Disable guest events, enable host events 15809cf57ebSDavid Brazdil */ 159c50cb043SDavid Brazdil static void __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt) 16009cf57ebSDavid Brazdil { 16109cf57ebSDavid Brazdil struct kvm_host_data *host; 16209cf57ebSDavid Brazdil struct kvm_pmu_events *pmu; 16309cf57ebSDavid Brazdil 16409cf57ebSDavid Brazdil host = container_of(host_ctxt, struct kvm_host_data, host_ctxt); 16509cf57ebSDavid Brazdil pmu = &host->pmu_events; 16609cf57ebSDavid Brazdil 16709cf57ebSDavid Brazdil if (pmu->events_guest) 16809cf57ebSDavid Brazdil write_sysreg(pmu->events_guest, pmcntenclr_el0); 16909cf57ebSDavid Brazdil 17009cf57ebSDavid Brazdil if (pmu->events_host) 17109cf57ebSDavid Brazdil write_sysreg(pmu->events_host, pmcntenset_el0); 17209cf57ebSDavid Brazdil } 17309cf57ebSDavid Brazdil 17409cf57ebSDavid Brazdil /* Switch to the guest for legacy non-VHE systems */ 175c50cb043SDavid Brazdil int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 17609cf57ebSDavid Brazdil { 17709cf57ebSDavid Brazdil struct kvm_cpu_context *host_ctxt; 17809cf57ebSDavid Brazdil struct kvm_cpu_context *guest_ctxt; 17909cf57ebSDavid Brazdil bool pmu_switch_needed; 18009cf57ebSDavid Brazdil u64 exit_code; 18109cf57ebSDavid Brazdil 18209cf57ebSDavid Brazdil /* 18309cf57ebSDavid Brazdil * Having IRQs masked via PMR when entering the guest means the GIC 18409cf57ebSDavid Brazdil * will not signal the CPU of interrupts of lower priority, and the 18509cf57ebSDavid Brazdil * only way to get out will be via guest exceptions. 18609cf57ebSDavid Brazdil * Naturally, we want to avoid this. 18709cf57ebSDavid Brazdil */ 18809cf57ebSDavid Brazdil if (system_uses_irq_prio_masking()) { 18909cf57ebSDavid Brazdil gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); 19009cf57ebSDavid Brazdil pmr_sync(); 19109cf57ebSDavid Brazdil } 19209cf57ebSDavid Brazdil 193717cf94aSDavid Brazdil host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 19409cf57ebSDavid Brazdil host_ctxt->__hyp_running_vcpu = vcpu; 19509cf57ebSDavid Brazdil guest_ctxt = &vcpu->arch.ctxt; 19609cf57ebSDavid Brazdil 19709cf57ebSDavid Brazdil pmu_switch_needed = __pmu_switch_to_guest(host_ctxt); 19809cf57ebSDavid Brazdil 19909cf57ebSDavid Brazdil __sysreg_save_state_nvhe(host_ctxt); 20009cf57ebSDavid Brazdil 201cdb5e02eSMarc Zyngier __adjust_pc(vcpu); 202cdb5e02eSMarc Zyngier 20309cf57ebSDavid Brazdil /* 20409cf57ebSDavid Brazdil * We must restore the 32-bit state before the sysregs, thanks 20509cf57ebSDavid Brazdil * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72). 20609cf57ebSDavid Brazdil * 20709cf57ebSDavid Brazdil * Also, and in order to be able to deal with erratum #1319537 (A57) 20809cf57ebSDavid Brazdil * and #1319367 (A72), we must ensure that all VM-related sysreg are 20909cf57ebSDavid Brazdil * restored before we enable S2 translation. 21009cf57ebSDavid Brazdil */ 21109cf57ebSDavid Brazdil __sysreg32_restore_state(vcpu); 21209cf57ebSDavid Brazdil __sysreg_restore_state_nvhe(guest_ctxt); 21309cf57ebSDavid Brazdil 214501a67a2SAndrew Scull __load_guest_stage2(kern_hyp_va(vcpu->arch.hw_mmu)); 21509cf57ebSDavid Brazdil __activate_traps(vcpu); 21609cf57ebSDavid Brazdil 21709cf57ebSDavid Brazdil __hyp_vgic_restore_state(vcpu); 21809cf57ebSDavid Brazdil __timer_enable_traps(vcpu); 21909cf57ebSDavid Brazdil 22009cf57ebSDavid Brazdil __debug_switch_to_guest(vcpu); 22109cf57ebSDavid Brazdil 22209cf57ebSDavid Brazdil do { 22309cf57ebSDavid Brazdil /* Jump in the fire! */ 224b619d9aaSAndrew Scull exit_code = __guest_enter(vcpu); 22509cf57ebSDavid Brazdil 22609cf57ebSDavid Brazdil /* And we're baaack! */ 22709cf57ebSDavid Brazdil } while (fixup_guest_exit(vcpu, &exit_code)); 22809cf57ebSDavid Brazdil 22909cf57ebSDavid Brazdil __sysreg_save_state_nvhe(guest_ctxt); 23009cf57ebSDavid Brazdil __sysreg32_save_state(vcpu); 23109cf57ebSDavid Brazdil __timer_disable_traps(vcpu); 23209cf57ebSDavid Brazdil __hyp_vgic_save_state(vcpu); 23309cf57ebSDavid Brazdil 23409cf57ebSDavid Brazdil __deactivate_traps(vcpu); 235501a67a2SAndrew Scull __load_host_stage2(); 23609cf57ebSDavid Brazdil 23709cf57ebSDavid Brazdil __sysreg_restore_state_nvhe(host_ctxt); 23809cf57ebSDavid Brazdil 23909cf57ebSDavid Brazdil if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) 24009cf57ebSDavid Brazdil __fpsimd_save_fpexc32(vcpu); 24109cf57ebSDavid Brazdil 24209cf57ebSDavid Brazdil /* 24309cf57ebSDavid Brazdil * This must come after restoring the host sysregs, since a non-VHE 24409cf57ebSDavid Brazdil * system may enable SPE here and make use of the TTBRs. 24509cf57ebSDavid Brazdil */ 24609cf57ebSDavid Brazdil __debug_switch_to_host(vcpu); 24709cf57ebSDavid Brazdil 24809cf57ebSDavid Brazdil if (pmu_switch_needed) 24909cf57ebSDavid Brazdil __pmu_switch_to_host(host_ctxt); 25009cf57ebSDavid Brazdil 25109cf57ebSDavid Brazdil /* Returning to host will clear PSR.I, remask PMR if needed */ 25209cf57ebSDavid Brazdil if (system_uses_irq_prio_masking()) 25309cf57ebSDavid Brazdil gic_write_pmr(GIC_PRIO_IRQOFF); 25409cf57ebSDavid Brazdil 255a2e102e2SAndrew Scull host_ctxt->__hyp_running_vcpu = NULL; 256a2e102e2SAndrew Scull 25709cf57ebSDavid Brazdil return exit_code; 25809cf57ebSDavid Brazdil } 25909cf57ebSDavid Brazdil 2606a0259edSAndrew Scull void __noreturn hyp_panic(void) 26109cf57ebSDavid Brazdil { 26209cf57ebSDavid Brazdil u64 spsr = read_sysreg_el2(SYS_SPSR); 26309cf57ebSDavid Brazdil u64 elr = read_sysreg_el2(SYS_ELR); 26496d389caSRob Herring u64 par = read_sysreg_par(); 265a2e102e2SAndrew Scull bool restore_host = true; 2666a0259edSAndrew Scull struct kvm_cpu_context *host_ctxt; 2676a0259edSAndrew Scull struct kvm_vcpu *vcpu; 26809cf57ebSDavid Brazdil 26914ef9d04SMarc Zyngier host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; 2706a0259edSAndrew Scull vcpu = host_ctxt->__hyp_running_vcpu; 2716a0259edSAndrew Scull 272a2e102e2SAndrew Scull if (vcpu) { 27309cf57ebSDavid Brazdil __timer_disable_traps(vcpu); 27409cf57ebSDavid Brazdil __deactivate_traps(vcpu); 275501a67a2SAndrew Scull __load_host_stage2(); 27609cf57ebSDavid Brazdil __sysreg_restore_state_nvhe(host_ctxt); 27709cf57ebSDavid Brazdil } 27809cf57ebSDavid Brazdil 279a2e102e2SAndrew Scull __hyp_do_panic(restore_host, spsr, elr, par); 28009cf57ebSDavid Brazdil unreachable(); 28109cf57ebSDavid Brazdil } 282e9ee186bSJames Morse 283e9ee186bSJames Morse asmlinkage void kvm_unexpected_el2_exception(void) 284e9ee186bSJames Morse { 285e9ee186bSJames Morse return __kvm_unexpected_el2_exception(); 286e9ee186bSJames Morse } 287