109cf57ebSDavid Brazdil // SPDX-License-Identifier: GPL-2.0-only
209cf57ebSDavid Brazdil /*
309cf57ebSDavid Brazdil * Copyright (C) 2015 - ARM Ltd
409cf57ebSDavid Brazdil * Author: Marc Zyngier <marc.zyngier@arm.com>
509cf57ebSDavid Brazdil */
609cf57ebSDavid Brazdil
709cf57ebSDavid Brazdil #include <hyp/switch.h>
813aeb9b4SDavid Brazdil #include <hyp/sysreg-sr.h>
909cf57ebSDavid Brazdil
1009cf57ebSDavid Brazdil #include <linux/arm-smccc.h>
1109cf57ebSDavid Brazdil #include <linux/kvm_host.h>
1209cf57ebSDavid Brazdil #include <linux/types.h>
1309cf57ebSDavid Brazdil #include <linux/jump_label.h>
1409cf57ebSDavid Brazdil #include <uapi/linux/psci.h>
1509cf57ebSDavid Brazdil
1609cf57ebSDavid Brazdil #include <kvm/arm_psci.h>
1709cf57ebSDavid Brazdil
1809cf57ebSDavid Brazdil #include <asm/barrier.h>
1909cf57ebSDavid Brazdil #include <asm/cpufeature.h>
2009cf57ebSDavid Brazdil #include <asm/kprobes.h>
2109cf57ebSDavid Brazdil #include <asm/kvm_asm.h>
2209cf57ebSDavid Brazdil #include <asm/kvm_emulate.h>
2309cf57ebSDavid Brazdil #include <asm/kvm_hyp.h>
2409cf57ebSDavid Brazdil #include <asm/kvm_mmu.h>
2509cf57ebSDavid Brazdil #include <asm/fpsimd.h>
2609cf57ebSDavid Brazdil #include <asm/debug-monitors.h>
2709cf57ebSDavid Brazdil #include <asm/processor.h>
2809cf57ebSDavid Brazdil
293061725dSMarc Zyngier #include <nvhe/fixed_config.h>
301025c8c0SQuentin Perret #include <nvhe/mem_protect.h>
311025c8c0SQuentin Perret
3214ef9d04SMarc Zyngier /* Non-VHE specific context */
3314ef9d04SMarc Zyngier DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
3414ef9d04SMarc Zyngier DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
3514ef9d04SMarc Zyngier DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
362a1198c9SDavid Brazdil
37879e5ac7SKalesh Singh extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc);
38879e5ac7SKalesh Singh
__activate_traps(struct kvm_vcpu * vcpu)39c50cb043SDavid Brazdil static void __activate_traps(struct kvm_vcpu *vcpu)
4009cf57ebSDavid Brazdil {
4109cf57ebSDavid Brazdil u64 val;
4209cf57ebSDavid Brazdil
4309cf57ebSDavid Brazdil ___activate_traps(vcpu);
4409cf57ebSDavid Brazdil __activate_traps_common(vcpu);
4509cf57ebSDavid Brazdil
46cd496228SFuad Tabba val = vcpu->arch.cptr_el2;
4775c76ab5SMarc Zyngier val |= CPTR_EL2_TAM; /* Same bit irrespective of E2H */
4875c76ab5SMarc Zyngier val |= has_hvhe() ? CPACR_EL1_TTA : CPTR_EL2_TTA;
4975c76ab5SMarc Zyngier if (cpus_have_final_cap(ARM64_SME)) {
5075c76ab5SMarc Zyngier if (has_hvhe())
5175c76ab5SMarc Zyngier val &= ~(CPACR_EL1_SMEN_EL1EN | CPACR_EL1_SMEN_EL0EN);
5275c76ab5SMarc Zyngier else
5375c76ab5SMarc Zyngier val |= CPTR_EL2_TSM;
5475c76ab5SMarc Zyngier }
5575c76ab5SMarc Zyngier
56e9ada6c2SMarc Zyngier if (!guest_owns_fp_regs(vcpu)) {
5775c76ab5SMarc Zyngier if (has_hvhe())
5875c76ab5SMarc Zyngier val &= ~(CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |
5975c76ab5SMarc Zyngier CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN);
6075c76ab5SMarc Zyngier else
618c8010d6SMarc Zyngier val |= CPTR_EL2_TFP | CPTR_EL2_TZ;
6275c76ab5SMarc Zyngier
6309cf57ebSDavid Brazdil __activate_traps_fpsimd32(vcpu);
6409cf57ebSDavid Brazdil }
6509cf57ebSDavid Brazdil
66*a9626099SFuad Tabba kvm_write_cptr_el2(val);
6714ef9d04SMarc Zyngier write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2);
6809cf57ebSDavid Brazdil
6909cf57ebSDavid Brazdil if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
7009cf57ebSDavid Brazdil struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
7109cf57ebSDavid Brazdil
7209cf57ebSDavid Brazdil isb();
7309cf57ebSDavid Brazdil /*
7409cf57ebSDavid Brazdil * At this stage, and thanks to the above isb(), S2 is
7509cf57ebSDavid Brazdil * configured and enabled. We can now restore the guest's S1
7609cf57ebSDavid Brazdil * configuration: SCTLR, and only then TCR.
7709cf57ebSDavid Brazdil */
7871071acfSMarc Zyngier write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
7909cf57ebSDavid Brazdil isb();
8071071acfSMarc Zyngier write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
8109cf57ebSDavid Brazdil }
8209cf57ebSDavid Brazdil }
8309cf57ebSDavid Brazdil
__deactivate_traps(struct kvm_vcpu * vcpu)84c50cb043SDavid Brazdil static void __deactivate_traps(struct kvm_vcpu *vcpu)
8509cf57ebSDavid Brazdil {
866e3bfbb2SAndrew Scull extern char __kvm_hyp_host_vector[];
8709cf57ebSDavid Brazdil
8809cf57ebSDavid Brazdil ___deactivate_traps(vcpu);
8909cf57ebSDavid Brazdil
9009cf57ebSDavid Brazdil if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
9109cf57ebSDavid Brazdil u64 val;
9209cf57ebSDavid Brazdil
9309cf57ebSDavid Brazdil /*
9409cf57ebSDavid Brazdil * Set the TCR and SCTLR registers in the exact opposite
9509cf57ebSDavid Brazdil * sequence as __activate_traps (first prevent walks,
9609cf57ebSDavid Brazdil * then force the MMU on). A generous sprinkling of isb()
9709cf57ebSDavid Brazdil * ensure that things happen in this exact order.
9809cf57ebSDavid Brazdil */
9909cf57ebSDavid Brazdil val = read_sysreg_el1(SYS_TCR);
10009cf57ebSDavid Brazdil write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR);
10109cf57ebSDavid Brazdil isb();
10209cf57ebSDavid Brazdil val = read_sysreg_el1(SYS_SCTLR);
10309cf57ebSDavid Brazdil write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR);
10409cf57ebSDavid Brazdil isb();
10509cf57ebSDavid Brazdil }
10609cf57ebSDavid Brazdil
1071460b4b2SFuad Tabba __deactivate_traps_common(vcpu);
10809cf57ebSDavid Brazdil
109734864c1SQuentin Perret write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2);
11009cf57ebSDavid Brazdil
11175c76ab5SMarc Zyngier kvm_reset_cptr_el2(vcpu);
112501a67a2SAndrew Scull write_sysreg(__kvm_hyp_host_vector, vbar_el2);
11309cf57ebSDavid Brazdil }
11409cf57ebSDavid Brazdil
11509cf57ebSDavid Brazdil /* Save VGICv3 state on non-VHE systems */
__hyp_vgic_save_state(struct kvm_vcpu * vcpu)116c50cb043SDavid Brazdil static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
11709cf57ebSDavid Brazdil {
11809cf57ebSDavid Brazdil if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
11909cf57ebSDavid Brazdil __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3);
12009cf57ebSDavid Brazdil __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
12109cf57ebSDavid Brazdil }
12209cf57ebSDavid Brazdil }
12309cf57ebSDavid Brazdil
12443b233b1SWei-Lin Chang /* Restore VGICv3 state on non-VHE systems */
__hyp_vgic_restore_state(struct kvm_vcpu * vcpu)125c50cb043SDavid Brazdil static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
12609cf57ebSDavid Brazdil {
12709cf57ebSDavid Brazdil if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
12809cf57ebSDavid Brazdil __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
12909cf57ebSDavid Brazdil __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3);
13009cf57ebSDavid Brazdil }
13109cf57ebSDavid Brazdil }
13209cf57ebSDavid Brazdil
133bd61395aSRandy Dunlap /*
13409cf57ebSDavid Brazdil * Disable host events, enable guest events
13509cf57ebSDavid Brazdil */
13620492a62SMarc Zyngier #ifdef CONFIG_HW_PERF_EVENTS
__pmu_switch_to_guest(struct kvm_vcpu * vcpu)13784d751a0SFuad Tabba static bool __pmu_switch_to_guest(struct kvm_vcpu *vcpu)
13809cf57ebSDavid Brazdil {
13984d751a0SFuad Tabba struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events;
14009cf57ebSDavid Brazdil
14109cf57ebSDavid Brazdil if (pmu->events_host)
14209cf57ebSDavid Brazdil write_sysreg(pmu->events_host, pmcntenclr_el0);
14309cf57ebSDavid Brazdil
14409cf57ebSDavid Brazdil if (pmu->events_guest)
14509cf57ebSDavid Brazdil write_sysreg(pmu->events_guest, pmcntenset_el0);
14609cf57ebSDavid Brazdil
14709cf57ebSDavid Brazdil return (pmu->events_host || pmu->events_guest);
14809cf57ebSDavid Brazdil }
14909cf57ebSDavid Brazdil
150bd61395aSRandy Dunlap /*
15109cf57ebSDavid Brazdil * Disable guest events, enable host events
15209cf57ebSDavid Brazdil */
__pmu_switch_to_host(struct kvm_vcpu * vcpu)15384d751a0SFuad Tabba static void __pmu_switch_to_host(struct kvm_vcpu *vcpu)
15409cf57ebSDavid Brazdil {
15584d751a0SFuad Tabba struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events;
15609cf57ebSDavid Brazdil
15709cf57ebSDavid Brazdil if (pmu->events_guest)
15809cf57ebSDavid Brazdil write_sysreg(pmu->events_guest, pmcntenclr_el0);
15909cf57ebSDavid Brazdil
16009cf57ebSDavid Brazdil if (pmu->events_host)
16109cf57ebSDavid Brazdil write_sysreg(pmu->events_host, pmcntenset_el0);
16209cf57ebSDavid Brazdil }
16320492a62SMarc Zyngier #else
16420492a62SMarc Zyngier #define __pmu_switch_to_guest(v) ({ false; })
16520492a62SMarc Zyngier #define __pmu_switch_to_host(v) do {} while (0)
16620492a62SMarc Zyngier #endif
16709cf57ebSDavid Brazdil
168bd61395aSRandy Dunlap /*
1691423afcbSFuad Tabba * Handler for protected VM MSR, MRS or System instruction execution in AArch64.
1701423afcbSFuad Tabba *
1711423afcbSFuad Tabba * Returns true if the hypervisor has handled the exit, and control should go
1721423afcbSFuad Tabba * back to the guest, or false if it hasn't.
1731423afcbSFuad Tabba */
kvm_handle_pvm_sys64(struct kvm_vcpu * vcpu,u64 * exit_code)1741423afcbSFuad Tabba static bool kvm_handle_pvm_sys64(struct kvm_vcpu *vcpu, u64 *exit_code)
1751423afcbSFuad Tabba {
17607305590SMarc Zyngier /*
17707305590SMarc Zyngier * Make sure we handle the exit for workarounds and ptrauth
17807305590SMarc Zyngier * before the pKVM handling, as the latter could decide to
17907305590SMarc Zyngier * UNDEF.
18007305590SMarc Zyngier */
18107305590SMarc Zyngier return (kvm_hyp_handle_sysreg(vcpu, exit_code) ||
18207305590SMarc Zyngier kvm_handle_pvm_sysreg(vcpu, exit_code));
1831423afcbSFuad Tabba }
1841423afcbSFuad Tabba
1858fb20461SMarc Zyngier static const exit_handler_fn hyp_exit_handlers[] = {
1868fb20461SMarc Zyngier [0 ... ESR_ELx_EC_MAX] = NULL,
1878fb20461SMarc Zyngier [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
1888fb20461SMarc Zyngier [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg,
1898fb20461SMarc Zyngier [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
1908fb20461SMarc Zyngier [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
1918fb20461SMarc Zyngier [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
1928fb20461SMarc Zyngier [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
193811154e2SAkihiko Odaki [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low,
1948fb20461SMarc Zyngier [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth,
1958fb20461SMarc Zyngier };
1968fb20461SMarc Zyngier
1971423afcbSFuad Tabba static const exit_handler_fn pvm_exit_handlers[] = {
1981423afcbSFuad Tabba [0 ... ESR_ELx_EC_MAX] = NULL,
1991423afcbSFuad Tabba [ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64,
2001423afcbSFuad Tabba [ESR_ELx_EC_SVE] = kvm_handle_pvm_restricted,
2014d2e469eSOliver Upton [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
2021423afcbSFuad Tabba [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
2031423afcbSFuad Tabba [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
204811154e2SAkihiko Odaki [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low,
2051423afcbSFuad Tabba [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth,
2061423afcbSFuad Tabba };
2071423afcbSFuad Tabba
kvm_get_exit_handler_array(struct kvm_vcpu * vcpu)2080c7639ccSMarc Zyngier static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu)
2098fb20461SMarc Zyngier {
2100c7639ccSMarc Zyngier if (unlikely(kvm_vm_is_protected(kern_hyp_va(vcpu->kvm))))
2111423afcbSFuad Tabba return pvm_exit_handlers;
2121423afcbSFuad Tabba
2138fb20461SMarc Zyngier return hyp_exit_handlers;
2148fb20461SMarc Zyngier }
2158fb20461SMarc Zyngier
2165f39efc4SFuad Tabba /*
2175f39efc4SFuad Tabba * Some guests (e.g., protected VMs) are not be allowed to run in AArch32.
2185f39efc4SFuad Tabba * The ARMv8 architecture does not give the hypervisor a mechanism to prevent a
2195f39efc4SFuad Tabba * guest from dropping to AArch32 EL0 if implemented by the CPU. If the
2205f39efc4SFuad Tabba * hypervisor spots a guest in such a state ensure it is handled, and don't
2215f39efc4SFuad Tabba * trust the host to spot or fix it. The check below is based on the one in
2225f39efc4SFuad Tabba * kvm_arch_vcpu_ioctl_run().
2235f39efc4SFuad Tabba *
2245f39efc4SFuad Tabba * Returns false if the guest ran in AArch32 when it shouldn't have, and
2255f39efc4SFuad Tabba * thus should exit to the host, or true if a the guest run loop can continue.
2265f39efc4SFuad Tabba */
early_exit_filter(struct kvm_vcpu * vcpu,u64 * exit_code)2277183b2b5SMarc Zyngier static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code)
2285f39efc4SFuad Tabba {
2295f39efc4SFuad Tabba struct kvm *kvm = kern_hyp_va(vcpu->kvm);
2305f39efc4SFuad Tabba
2315f39efc4SFuad Tabba if (kvm_vm_is_protected(kvm) && vcpu_mode_is_32bit(vcpu)) {
2325f39efc4SFuad Tabba /*
2335f39efc4SFuad Tabba * As we have caught the guest red-handed, decide that it isn't
2345f39efc4SFuad Tabba * fit for purpose anymore by making the vcpu invalid. The VMM
2355f39efc4SFuad Tabba * can try and fix it by re-initializing the vcpu with
2365f39efc4SFuad Tabba * KVM_ARM_VCPU_INIT, however, this is likely not possible for
2375f39efc4SFuad Tabba * protected VMs.
2385f39efc4SFuad Tabba */
2395f39efc4SFuad Tabba vcpu_clear_flag(vcpu, VCPU_INITIALIZED);
240271b7286SMarc Zyngier *exit_code &= BIT(ARM_EXIT_WITH_SERROR_BIT);
241271b7286SMarc Zyngier *exit_code |= ARM_EXCEPTION_IL;
2425f39efc4SFuad Tabba }
2435f39efc4SFuad Tabba }
2445f39efc4SFuad Tabba
24509cf57ebSDavid Brazdil /* Switch to the guest for legacy non-VHE systems */
__kvm_vcpu_run(struct kvm_vcpu * vcpu)246c50cb043SDavid Brazdil int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
24709cf57ebSDavid Brazdil {
24809cf57ebSDavid Brazdil struct kvm_cpu_context *host_ctxt;
24909cf57ebSDavid Brazdil struct kvm_cpu_context *guest_ctxt;
250923a547dSMarc Zyngier struct kvm_s2_mmu *mmu;
25109cf57ebSDavid Brazdil bool pmu_switch_needed;
25209cf57ebSDavid Brazdil u64 exit_code;
25309cf57ebSDavid Brazdil
25409cf57ebSDavid Brazdil /*
25509cf57ebSDavid Brazdil * Having IRQs masked via PMR when entering the guest means the GIC
25609cf57ebSDavid Brazdil * will not signal the CPU of interrupts of lower priority, and the
25709cf57ebSDavid Brazdil * only way to get out will be via guest exceptions.
25809cf57ebSDavid Brazdil * Naturally, we want to avoid this.
25909cf57ebSDavid Brazdil */
26009cf57ebSDavid Brazdil if (system_uses_irq_prio_masking()) {
26109cf57ebSDavid Brazdil gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
26209cf57ebSDavid Brazdil pmr_sync();
26309cf57ebSDavid Brazdil }
26409cf57ebSDavid Brazdil
265717cf94aSDavid Brazdil host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
26609cf57ebSDavid Brazdil host_ctxt->__hyp_running_vcpu = vcpu;
26709cf57ebSDavid Brazdil guest_ctxt = &vcpu->arch.ctxt;
26809cf57ebSDavid Brazdil
26984d751a0SFuad Tabba pmu_switch_needed = __pmu_switch_to_guest(vcpu);
27009cf57ebSDavid Brazdil
27109cf57ebSDavid Brazdil __sysreg_save_state_nvhe(host_ctxt);
272b96b0c5dSSuzuki K Poulose /*
273b96b0c5dSSuzuki K Poulose * We must flush and disable the SPE buffer for nVHE, as
274b96b0c5dSSuzuki K Poulose * the translation regime(EL1&0) is going to be loaded with
275b96b0c5dSSuzuki K Poulose * that of the guest. And we must do this before we change the
276b96b0c5dSSuzuki K Poulose * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and
277b96b0c5dSSuzuki K Poulose * before we load guest Stage1.
278b96b0c5dSSuzuki K Poulose */
279b96b0c5dSSuzuki K Poulose __debug_save_host_buffers_nvhe(vcpu);
28009cf57ebSDavid Brazdil
28155b5bac1SMarc Zyngier /*
28255b5bac1SMarc Zyngier * We're about to restore some new MMU state. Make sure
28355b5bac1SMarc Zyngier * ongoing page-table walks that have started before we
28455b5bac1SMarc Zyngier * trapped to EL2 have completed. This also synchronises the
28555b5bac1SMarc Zyngier * above disabling of SPE and TRBE.
28655b5bac1SMarc Zyngier *
28755b5bac1SMarc Zyngier * See DDI0487I.a D8.1.5 "Out-of-context translation regimes",
28855b5bac1SMarc Zyngier * rule R_LFHQG and subsequent information statements.
28955b5bac1SMarc Zyngier */
29055b5bac1SMarc Zyngier dsb(nsh);
29155b5bac1SMarc Zyngier
292f5e30680SMarc Zyngier __kvm_adjust_pc(vcpu);
293cdb5e02eSMarc Zyngier
29409cf57ebSDavid Brazdil /*
29509cf57ebSDavid Brazdil * We must restore the 32-bit state before the sysregs, thanks
29609cf57ebSDavid Brazdil * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
29709cf57ebSDavid Brazdil *
29809cf57ebSDavid Brazdil * Also, and in order to be able to deal with erratum #1319537 (A57)
29909cf57ebSDavid Brazdil * and #1319367 (A72), we must ensure that all VM-related sysreg are
30009cf57ebSDavid Brazdil * restored before we enable S2 translation.
30109cf57ebSDavid Brazdil */
30209cf57ebSDavid Brazdil __sysreg32_restore_state(vcpu);
30309cf57ebSDavid Brazdil __sysreg_restore_state_nvhe(guest_ctxt);
30409cf57ebSDavid Brazdil
305923a547dSMarc Zyngier mmu = kern_hyp_va(vcpu->arch.hw_mmu);
3064efc0edeSMarc Zyngier __load_stage2(mmu, kern_hyp_va(mmu->arch));
30709cf57ebSDavid Brazdil __activate_traps(vcpu);
30809cf57ebSDavid Brazdil
30909cf57ebSDavid Brazdil __hyp_vgic_restore_state(vcpu);
31009cf57ebSDavid Brazdil __timer_enable_traps(vcpu);
31109cf57ebSDavid Brazdil
31209cf57ebSDavid Brazdil __debug_switch_to_guest(vcpu);
31309cf57ebSDavid Brazdil
31409cf57ebSDavid Brazdil do {
31509cf57ebSDavid Brazdil /* Jump in the fire! */
316b619d9aaSAndrew Scull exit_code = __guest_enter(vcpu);
31709cf57ebSDavid Brazdil
31809cf57ebSDavid Brazdil /* And we're baaack! */
31909cf57ebSDavid Brazdil } while (fixup_guest_exit(vcpu, &exit_code));
32009cf57ebSDavid Brazdil
32109cf57ebSDavid Brazdil __sysreg_save_state_nvhe(guest_ctxt);
32209cf57ebSDavid Brazdil __sysreg32_save_state(vcpu);
32309cf57ebSDavid Brazdil __timer_disable_traps(vcpu);
32409cf57ebSDavid Brazdil __hyp_vgic_save_state(vcpu);
32509cf57ebSDavid Brazdil
32655b5bac1SMarc Zyngier /*
32755b5bac1SMarc Zyngier * Same thing as before the guest run: we're about to switch
32855b5bac1SMarc Zyngier * the MMU context, so let's make sure we don't have any
32955b5bac1SMarc Zyngier * ongoing EL1&0 translations.
33055b5bac1SMarc Zyngier */
33155b5bac1SMarc Zyngier dsb(nsh);
33255b5bac1SMarc Zyngier
33309cf57ebSDavid Brazdil __deactivate_traps(vcpu);
334501a67a2SAndrew Scull __load_host_stage2();
33509cf57ebSDavid Brazdil
33609cf57ebSDavid Brazdil __sysreg_restore_state_nvhe(host_ctxt);
33709cf57ebSDavid Brazdil
338f8077b0dSMarc Zyngier if (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED)
33909cf57ebSDavid Brazdil __fpsimd_save_fpexc32(vcpu);
34009cf57ebSDavid Brazdil
341b96b0c5dSSuzuki K Poulose __debug_switch_to_host(vcpu);
34209cf57ebSDavid Brazdil /*
34309cf57ebSDavid Brazdil * This must come after restoring the host sysregs, since a non-VHE
34409cf57ebSDavid Brazdil * system may enable SPE here and make use of the TTBRs.
34509cf57ebSDavid Brazdil */
346b96b0c5dSSuzuki K Poulose __debug_restore_host_buffers_nvhe(vcpu);
34709cf57ebSDavid Brazdil
34809cf57ebSDavid Brazdil if (pmu_switch_needed)
34984d751a0SFuad Tabba __pmu_switch_to_host(vcpu);
35009cf57ebSDavid Brazdil
35109cf57ebSDavid Brazdil /* Returning to host will clear PSR.I, remask PMR if needed */
35209cf57ebSDavid Brazdil if (system_uses_irq_prio_masking())
35309cf57ebSDavid Brazdil gic_write_pmr(GIC_PRIO_IRQOFF);
35409cf57ebSDavid Brazdil
355a2e102e2SAndrew Scull host_ctxt->__hyp_running_vcpu = NULL;
356a2e102e2SAndrew Scull
35709cf57ebSDavid Brazdil return exit_code;
35809cf57ebSDavid Brazdil }
35909cf57ebSDavid Brazdil
hyp_panic(void)36066de19faSKalesh Singh asmlinkage void __noreturn hyp_panic(void)
36109cf57ebSDavid Brazdil {
36209cf57ebSDavid Brazdil u64 spsr = read_sysreg_el2(SYS_SPSR);
36309cf57ebSDavid Brazdil u64 elr = read_sysreg_el2(SYS_ELR);
36496d389caSRob Herring u64 par = read_sysreg_par();
3656a0259edSAndrew Scull struct kvm_cpu_context *host_ctxt;
3666a0259edSAndrew Scull struct kvm_vcpu *vcpu;
36709cf57ebSDavid Brazdil
36814ef9d04SMarc Zyngier host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
3696a0259edSAndrew Scull vcpu = host_ctxt->__hyp_running_vcpu;
3706a0259edSAndrew Scull
371a2e102e2SAndrew Scull if (vcpu) {
37209cf57ebSDavid Brazdil __timer_disable_traps(vcpu);
37309cf57ebSDavid Brazdil __deactivate_traps(vcpu);
374501a67a2SAndrew Scull __load_host_stage2();
37509cf57ebSDavid Brazdil __sysreg_restore_state_nvhe(host_ctxt);
37609cf57ebSDavid Brazdil }
37709cf57ebSDavid Brazdil
378879e5ac7SKalesh Singh /* Prepare to dump kvm nvhe hyp stacktrace */
379879e5ac7SKalesh Singh kvm_nvhe_prepare_backtrace((unsigned long)__builtin_frame_address(0),
380879e5ac7SKalesh Singh _THIS_IP_);
381879e5ac7SKalesh Singh
382c4b000c3SAndrew Scull __hyp_do_panic(host_ctxt, spsr, elr, par);
38309cf57ebSDavid Brazdil unreachable();
38409cf57ebSDavid Brazdil }
385e9ee186bSJames Morse
hyp_panic_bad_stack(void)38666de19faSKalesh Singh asmlinkage void __noreturn hyp_panic_bad_stack(void)
38766de19faSKalesh Singh {
38866de19faSKalesh Singh hyp_panic();
38966de19faSKalesh Singh }
39066de19faSKalesh Singh
kvm_unexpected_el2_exception(void)391e9ee186bSJames Morse asmlinkage void kvm_unexpected_el2_exception(void)
392e9ee186bSJames Morse {
3931c3ace2bSQuentin Perret __kvm_unexpected_el2_exception();
394e9ee186bSJames Morse }
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