xref: /openbmc/linux/arch/arm64/kvm/hyp/include/hyp/switch.h (revision df0e68c1) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2015 - ARM Ltd
4  * Author: Marc Zyngier <marc.zyngier@arm.com>
5  */
6 
7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
8 #define __ARM64_KVM_HYP_SWITCH_H__
9 
10 #include <hyp/adjust_pc.h>
11 #include <hyp/fault.h>
12 
13 #include <linux/arm-smccc.h>
14 #include <linux/kvm_host.h>
15 #include <linux/types.h>
16 #include <linux/jump_label.h>
17 #include <uapi/linux/psci.h>
18 
19 #include <kvm/arm_psci.h>
20 
21 #include <asm/barrier.h>
22 #include <asm/cpufeature.h>
23 #include <asm/extable.h>
24 #include <asm/kprobes.h>
25 #include <asm/kvm_asm.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_hyp.h>
28 #include <asm/kvm_mmu.h>
29 #include <asm/fpsimd.h>
30 #include <asm/debug-monitors.h>
31 #include <asm/processor.h>
32 #include <asm/thread_info.h>
33 
34 struct kvm_exception_table_entry {
35 	int insn, fixup;
36 };
37 
38 extern struct kvm_exception_table_entry __start___kvm_ex_table;
39 extern struct kvm_exception_table_entry __stop___kvm_ex_table;
40 
41 /* Check whether the FP regs were dirtied while in the host-side run loop: */
42 static inline bool update_fp_enabled(struct kvm_vcpu *vcpu)
43 {
44 	/*
45 	 * When the system doesn't support FP/SIMD, we cannot rely on
46 	 * the _TIF_FOREIGN_FPSTATE flag. However, we always inject an
47 	 * abort on the very first access to FP and thus we should never
48 	 * see KVM_ARM64_FP_ENABLED. For added safety, make sure we always
49 	 * trap the accesses.
50 	 */
51 	if (!system_supports_fpsimd() ||
52 	    vcpu->arch.host_thread_info->flags & _TIF_FOREIGN_FPSTATE)
53 		vcpu->arch.flags &= ~(KVM_ARM64_FP_ENABLED |
54 				      KVM_ARM64_FP_HOST);
55 
56 	return !!(vcpu->arch.flags & KVM_ARM64_FP_ENABLED);
57 }
58 
59 /* Save the 32-bit only FPSIMD system register state */
60 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
61 {
62 	if (!vcpu_el1_is_32bit(vcpu))
63 		return;
64 
65 	__vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2);
66 }
67 
68 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
69 {
70 	/*
71 	 * We are about to set CPTR_EL2.TFP to trap all floating point
72 	 * register accesses to EL2, however, the ARM ARM clearly states that
73 	 * traps are only taken to EL2 if the operation would not otherwise
74 	 * trap to EL1.  Therefore, always make sure that for 32-bit guests,
75 	 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
76 	 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
77 	 * it will cause an exception.
78 	 */
79 	if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
80 		write_sysreg(1 << 30, fpexc32_el2);
81 		isb();
82 	}
83 }
84 
85 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
86 {
87 	/* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
88 	write_sysreg(1 << 15, hstr_el2);
89 
90 	/*
91 	 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
92 	 * PMSELR_EL0 to make sure it never contains the cycle
93 	 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
94 	 * EL1 instead of being trapped to EL2.
95 	 */
96 	if (kvm_arm_support_pmu_v3()) {
97 		write_sysreg(0, pmselr_el0);
98 		write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
99 	}
100 
101 	vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2);
102 	write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
103 }
104 
105 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
106 {
107 	write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2);
108 
109 	write_sysreg(0, hstr_el2);
110 	if (kvm_arm_support_pmu_v3())
111 		write_sysreg(0, pmuserenr_el0);
112 }
113 
114 static inline void ___activate_traps(struct kvm_vcpu *vcpu)
115 {
116 	u64 hcr = vcpu->arch.hcr_el2;
117 
118 	if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
119 		hcr |= HCR_TVM;
120 
121 	write_sysreg(hcr, hcr_el2);
122 
123 	if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
124 		write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
125 }
126 
127 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
128 {
129 	/*
130 	 * If we pended a virtual abort, preserve it until it gets
131 	 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
132 	 * the crucial bit is "On taking a vSError interrupt,
133 	 * HCR_EL2.VSE is cleared to 0."
134 	 */
135 	if (vcpu->arch.hcr_el2 & HCR_VSE) {
136 		vcpu->arch.hcr_el2 &= ~HCR_VSE;
137 		vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
138 	}
139 }
140 
141 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
142 {
143 	return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
144 }
145 
146 static inline void __hyp_sve_save_host(struct kvm_vcpu *vcpu)
147 {
148 	struct thread_struct *thread;
149 
150 	thread = container_of(vcpu->arch.host_fpsimd_state, struct thread_struct,
151 			      uw.fpsimd_state);
152 
153 	__sve_save_state(sve_pffr(thread), &vcpu->arch.host_fpsimd_state->fpsr);
154 }
155 
156 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
157 {
158 	sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
159 	__sve_restore_state(vcpu_sve_pffr(vcpu),
160 			    &vcpu->arch.ctxt.fp_regs.fpsr);
161 	write_sysreg_el1(__vcpu_sys_reg(vcpu, ZCR_EL1), SYS_ZCR);
162 }
163 
164 /*
165  * We trap the first access to the FP/SIMD to save the host context and
166  * restore the guest context lazily.
167  * If FP/SIMD is not implemented, handle the trap and inject an undefined
168  * instruction exception to the guest. Similarly for trapped SVE accesses.
169  */
170 static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
171 {
172 	bool sve_guest, sve_host;
173 	u8 esr_ec;
174 	u64 reg;
175 
176 	if (!system_supports_fpsimd())
177 		return false;
178 
179 	if (system_supports_sve()) {
180 		sve_guest = vcpu_has_sve(vcpu);
181 		sve_host = vcpu->arch.flags & KVM_ARM64_HOST_SVE_IN_USE;
182 	} else {
183 		sve_guest = false;
184 		sve_host = false;
185 	}
186 
187 	esr_ec = kvm_vcpu_trap_get_class(vcpu);
188 
189 	/* Don't handle SVE traps for non-SVE vcpus here: */
190 	if (!sve_guest && esr_ec != ESR_ELx_EC_FP_ASIMD)
191 		return false;
192 
193 	/* Valid trap.  Switch the context: */
194 	if (has_vhe()) {
195 		reg = CPACR_EL1_FPEN;
196 		if (sve_guest)
197 			reg |= CPACR_EL1_ZEN;
198 
199 		sysreg_clear_set(cpacr_el1, 0, reg);
200 	} else {
201 		reg = CPTR_EL2_TFP;
202 		if (sve_guest)
203 			reg |= CPTR_EL2_TZ;
204 
205 		sysreg_clear_set(cptr_el2, reg, 0);
206 	}
207 	isb();
208 
209 	if (vcpu->arch.flags & KVM_ARM64_FP_HOST) {
210 		if (sve_host)
211 			__hyp_sve_save_host(vcpu);
212 		else
213 			__fpsimd_save_state(vcpu->arch.host_fpsimd_state);
214 
215 		vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
216 	}
217 
218 	if (sve_guest)
219 		__hyp_sve_restore_guest(vcpu);
220 	else
221 		__fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
222 
223 	/* Skip restoring fpexc32 for AArch64 guests */
224 	if (!(read_sysreg(hcr_el2) & HCR_RW))
225 		write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
226 
227 	vcpu->arch.flags |= KVM_ARM64_FP_ENABLED;
228 
229 	return true;
230 }
231 
232 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
233 {
234 	u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
235 	int rt = kvm_vcpu_sys_get_rt(vcpu);
236 	u64 val = vcpu_get_reg(vcpu, rt);
237 
238 	/*
239 	 * The normal sysreg handling code expects to see the traps,
240 	 * let's not do anything here.
241 	 */
242 	if (vcpu->arch.hcr_el2 & HCR_TVM)
243 		return false;
244 
245 	switch (sysreg) {
246 	case SYS_SCTLR_EL1:
247 		write_sysreg_el1(val, SYS_SCTLR);
248 		break;
249 	case SYS_TTBR0_EL1:
250 		write_sysreg_el1(val, SYS_TTBR0);
251 		break;
252 	case SYS_TTBR1_EL1:
253 		write_sysreg_el1(val, SYS_TTBR1);
254 		break;
255 	case SYS_TCR_EL1:
256 		write_sysreg_el1(val, SYS_TCR);
257 		break;
258 	case SYS_ESR_EL1:
259 		write_sysreg_el1(val, SYS_ESR);
260 		break;
261 	case SYS_FAR_EL1:
262 		write_sysreg_el1(val, SYS_FAR);
263 		break;
264 	case SYS_AFSR0_EL1:
265 		write_sysreg_el1(val, SYS_AFSR0);
266 		break;
267 	case SYS_AFSR1_EL1:
268 		write_sysreg_el1(val, SYS_AFSR1);
269 		break;
270 	case SYS_MAIR_EL1:
271 		write_sysreg_el1(val, SYS_MAIR);
272 		break;
273 	case SYS_AMAIR_EL1:
274 		write_sysreg_el1(val, SYS_AMAIR);
275 		break;
276 	case SYS_CONTEXTIDR_EL1:
277 		write_sysreg_el1(val, SYS_CONTEXTIDR);
278 		break;
279 	default:
280 		return false;
281 	}
282 
283 	__kvm_skip_instr(vcpu);
284 	return true;
285 }
286 
287 static inline bool esr_is_ptrauth_trap(u32 esr)
288 {
289 	switch (esr_sys64_to_sysreg(esr)) {
290 	case SYS_APIAKEYLO_EL1:
291 	case SYS_APIAKEYHI_EL1:
292 	case SYS_APIBKEYLO_EL1:
293 	case SYS_APIBKEYHI_EL1:
294 	case SYS_APDAKEYLO_EL1:
295 	case SYS_APDAKEYHI_EL1:
296 	case SYS_APDBKEYLO_EL1:
297 	case SYS_APDBKEYHI_EL1:
298 	case SYS_APGAKEYLO_EL1:
299 	case SYS_APGAKEYHI_EL1:
300 		return true;
301 	}
302 
303 	return false;
304 }
305 
306 #define __ptrauth_save_key(ctxt, key)					\
307 	do {								\
308 	u64 __val;                                                      \
309 	__val = read_sysreg_s(SYS_ ## key ## KEYLO_EL1);                \
310 	ctxt_sys_reg(ctxt, key ## KEYLO_EL1) = __val;                   \
311 	__val = read_sysreg_s(SYS_ ## key ## KEYHI_EL1);                \
312 	ctxt_sys_reg(ctxt, key ## KEYHI_EL1) = __val;                   \
313 } while(0)
314 
315 DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
316 
317 static bool kvm_hyp_handle_ptrauth(struct kvm_vcpu *vcpu, u64 *exit_code)
318 {
319 	struct kvm_cpu_context *ctxt;
320 	u64 val;
321 
322 	if (!vcpu_has_ptrauth(vcpu))
323 		return false;
324 
325 	ctxt = this_cpu_ptr(&kvm_hyp_ctxt);
326 	__ptrauth_save_key(ctxt, APIA);
327 	__ptrauth_save_key(ctxt, APIB);
328 	__ptrauth_save_key(ctxt, APDA);
329 	__ptrauth_save_key(ctxt, APDB);
330 	__ptrauth_save_key(ctxt, APGA);
331 
332 	vcpu_ptrauth_enable(vcpu);
333 
334 	val = read_sysreg(hcr_el2);
335 	val |= (HCR_API | HCR_APK);
336 	write_sysreg(val, hcr_el2);
337 
338 	return true;
339 }
340 
341 static bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
342 {
343 	if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
344 	    handle_tx2_tvm(vcpu))
345 		return true;
346 
347 	if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
348 	    __vgic_v3_perform_cpuif_access(vcpu) == 1)
349 		return true;
350 
351 	if (esr_is_ptrauth_trap(kvm_vcpu_get_esr(vcpu)))
352 		return kvm_hyp_handle_ptrauth(vcpu, exit_code);
353 
354 	return false;
355 }
356 
357 static bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
358 {
359 	if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
360 	    __vgic_v3_perform_cpuif_access(vcpu) == 1)
361 		return true;
362 
363 	return false;
364 }
365 
366 static bool kvm_hyp_handle_iabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
367 {
368 	if (!__populate_fault_info(vcpu))
369 		return true;
370 
371 	return false;
372 }
373 
374 static bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
375 {
376 	if (!__populate_fault_info(vcpu))
377 		return true;
378 
379 	if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
380 		bool valid;
381 
382 		valid = kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
383 			kvm_vcpu_dabt_isvalid(vcpu) &&
384 			!kvm_vcpu_abt_issea(vcpu) &&
385 			!kvm_vcpu_abt_iss1tw(vcpu);
386 
387 		if (valid) {
388 			int ret = __vgic_v2_perform_cpuif_access(vcpu);
389 
390 			if (ret == 1)
391 				return true;
392 
393 			/* Promote an illegal access to an SError.*/
394 			if (ret == -1)
395 				*exit_code = ARM_EXCEPTION_EL1_SERROR;
396 		}
397 	}
398 
399 	return false;
400 }
401 
402 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
403 
404 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu);
405 
406 /*
407  * Allow the hypervisor to handle the exit with an exit handler if it has one.
408  *
409  * Returns true if the hypervisor handled the exit, and control should go back
410  * to the guest, or false if it hasn't.
411  */
412 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
413 {
414 	const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu);
415 	exit_handler_fn fn;
416 
417 	fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
418 
419 	if (fn)
420 		return fn(vcpu, exit_code);
421 
422 	return false;
423 }
424 
425 /*
426  * Return true when we were able to fixup the guest exit and should return to
427  * the guest, false when we should restore the host state and return to the
428  * main run loop.
429  */
430 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
431 {
432 	if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
433 		vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
434 
435 	if (ARM_SERROR_PENDING(*exit_code)) {
436 		u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
437 
438 		/*
439 		 * HVC already have an adjusted PC, which we need to
440 		 * correct in order to return to after having injected
441 		 * the SError.
442 		 *
443 		 * SMC, on the other hand, is *trapped*, meaning its
444 		 * preferred return address is the SMC itself.
445 		 */
446 		if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
447 			write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
448 	}
449 
450 	/*
451 	 * We're using the raw exception code in order to only process
452 	 * the trap if no SError is pending. We will come back to the
453 	 * same PC once the SError has been injected, and replay the
454 	 * trapping instruction.
455 	 */
456 	if (*exit_code != ARM_EXCEPTION_TRAP)
457 		goto exit;
458 
459 	/* Check if there's an exit handler and allow it to handle the exit. */
460 	if (kvm_hyp_handle_exit(vcpu, exit_code))
461 		goto guest;
462 exit:
463 	/* Return to the host kernel and handle the exit */
464 	return false;
465 
466 guest:
467 	/* Re-enter the guest */
468 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
469 	return true;
470 }
471 
472 static inline void __kvm_unexpected_el2_exception(void)
473 {
474 	extern char __guest_exit_panic[];
475 	unsigned long addr, fixup;
476 	struct kvm_exception_table_entry *entry, *end;
477 	unsigned long elr_el2 = read_sysreg(elr_el2);
478 
479 	entry = &__start___kvm_ex_table;
480 	end = &__stop___kvm_ex_table;
481 
482 	while (entry < end) {
483 		addr = (unsigned long)&entry->insn + entry->insn;
484 		fixup = (unsigned long)&entry->fixup + entry->fixup;
485 
486 		if (addr != elr_el2) {
487 			entry++;
488 			continue;
489 		}
490 
491 		write_sysreg(fixup, elr_el2);
492 		return;
493 	}
494 
495 	/* Trigger a panic after restoring the hyp context. */
496 	write_sysreg(__guest_exit_panic, elr_el2);
497 }
498 
499 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */
500