1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_HYP_SWITCH_H__ 8 #define __ARM64_KVM_HYP_SWITCH_H__ 9 10 #include <hyp/adjust_pc.h> 11 #include <hyp/fault.h> 12 13 #include <linux/arm-smccc.h> 14 #include <linux/kvm_host.h> 15 #include <linux/types.h> 16 #include <linux/jump_label.h> 17 #include <uapi/linux/psci.h> 18 19 #include <kvm/arm_psci.h> 20 21 #include <asm/barrier.h> 22 #include <asm/cpufeature.h> 23 #include <asm/extable.h> 24 #include <asm/kprobes.h> 25 #include <asm/kvm_asm.h> 26 #include <asm/kvm_emulate.h> 27 #include <asm/kvm_hyp.h> 28 #include <asm/kvm_mmu.h> 29 #include <asm/fpsimd.h> 30 #include <asm/debug-monitors.h> 31 #include <asm/processor.h> 32 33 struct kvm_exception_table_entry { 34 int insn, fixup; 35 }; 36 37 extern struct kvm_exception_table_entry __start___kvm_ex_table; 38 extern struct kvm_exception_table_entry __stop___kvm_ex_table; 39 40 /* Check whether the FP regs are owned by the guest */ 41 static inline bool guest_owns_fp_regs(struct kvm_vcpu *vcpu) 42 { 43 return vcpu->arch.fp_state == FP_STATE_GUEST_OWNED; 44 } 45 46 /* Save the 32-bit only FPSIMD system register state */ 47 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu) 48 { 49 if (!vcpu_el1_is_32bit(vcpu)) 50 return; 51 52 __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2); 53 } 54 55 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu) 56 { 57 /* 58 * We are about to set CPTR_EL2.TFP to trap all floating point 59 * register accesses to EL2, however, the ARM ARM clearly states that 60 * traps are only taken to EL2 if the operation would not otherwise 61 * trap to EL1. Therefore, always make sure that for 32-bit guests, 62 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit. 63 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to 64 * it will cause an exception. 65 */ 66 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) { 67 write_sysreg(1 << 30, fpexc32_el2); 68 isb(); 69 } 70 } 71 72 static inline void __activate_traps_common(struct kvm_vcpu *vcpu) 73 { 74 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */ 75 write_sysreg(1 << 15, hstr_el2); 76 77 /* 78 * Make sure we trap PMU access from EL0 to EL2. Also sanitize 79 * PMSELR_EL0 to make sure it never contains the cycle 80 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at 81 * EL1 instead of being trapped to EL2. 82 */ 83 if (kvm_arm_support_pmu_v3()) { 84 write_sysreg(0, pmselr_el0); 85 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); 86 } 87 88 vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2); 89 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); 90 91 if (cpus_have_final_cap(ARM64_SME)) { 92 sysreg_clear_set_s(SYS_HFGRTR_EL2, 93 HFGxTR_EL2_nSMPRI_EL1_MASK | 94 HFGxTR_EL2_nTPIDR2_EL0_MASK, 95 0); 96 sysreg_clear_set_s(SYS_HFGWTR_EL2, 97 HFGxTR_EL2_nSMPRI_EL1_MASK | 98 HFGxTR_EL2_nTPIDR2_EL0_MASK, 99 0); 100 } 101 } 102 103 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) 104 { 105 write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2); 106 107 write_sysreg(0, hstr_el2); 108 if (kvm_arm_support_pmu_v3()) 109 write_sysreg(0, pmuserenr_el0); 110 111 if (cpus_have_final_cap(ARM64_SME)) { 112 sysreg_clear_set_s(SYS_HFGRTR_EL2, 0, 113 HFGxTR_EL2_nSMPRI_EL1_MASK | 114 HFGxTR_EL2_nTPIDR2_EL0_MASK); 115 sysreg_clear_set_s(SYS_HFGWTR_EL2, 0, 116 HFGxTR_EL2_nSMPRI_EL1_MASK | 117 HFGxTR_EL2_nTPIDR2_EL0_MASK); 118 } 119 } 120 121 static inline void ___activate_traps(struct kvm_vcpu *vcpu) 122 { 123 u64 hcr = vcpu->arch.hcr_el2; 124 125 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM)) 126 hcr |= HCR_TVM; 127 128 write_sysreg(hcr, hcr_el2); 129 130 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE)) 131 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2); 132 } 133 134 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu) 135 { 136 /* 137 * If we pended a virtual abort, preserve it until it gets 138 * cleared. See D1.14.3 (Virtual Interrupts) for details, but 139 * the crucial bit is "On taking a vSError interrupt, 140 * HCR_EL2.VSE is cleared to 0." 141 */ 142 if (vcpu->arch.hcr_el2 & HCR_VSE) { 143 vcpu->arch.hcr_el2 &= ~HCR_VSE; 144 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE; 145 } 146 } 147 148 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu) 149 { 150 return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault); 151 } 152 153 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu) 154 { 155 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2); 156 __sve_restore_state(vcpu_sve_pffr(vcpu), 157 &vcpu->arch.ctxt.fp_regs.fpsr); 158 write_sysreg_el1(__vcpu_sys_reg(vcpu, ZCR_EL1), SYS_ZCR); 159 } 160 161 /* 162 * We trap the first access to the FP/SIMD to save the host context and 163 * restore the guest context lazily. 164 * If FP/SIMD is not implemented, handle the trap and inject an undefined 165 * instruction exception to the guest. Similarly for trapped SVE accesses. 166 */ 167 static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code) 168 { 169 bool sve_guest; 170 u8 esr_ec; 171 u64 reg; 172 173 if (!system_supports_fpsimd()) 174 return false; 175 176 sve_guest = vcpu_has_sve(vcpu); 177 esr_ec = kvm_vcpu_trap_get_class(vcpu); 178 179 /* Don't handle SVE traps for non-SVE vcpus here: */ 180 if (!sve_guest && esr_ec != ESR_ELx_EC_FP_ASIMD) 181 return false; 182 183 /* Valid trap. Switch the context: */ 184 185 /* First disable enough traps to allow us to update the registers */ 186 if (has_vhe()) { 187 reg = CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN; 188 if (sve_guest) 189 reg |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN; 190 191 sysreg_clear_set(cpacr_el1, 0, reg); 192 } else { 193 reg = CPTR_EL2_TFP; 194 if (sve_guest) 195 reg |= CPTR_EL2_TZ; 196 197 sysreg_clear_set(cptr_el2, reg, 0); 198 } 199 isb(); 200 201 /* Write out the host state if it's in the registers */ 202 if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED) 203 __fpsimd_save_state(vcpu->arch.host_fpsimd_state); 204 205 /* Restore the guest state */ 206 if (sve_guest) 207 __hyp_sve_restore_guest(vcpu); 208 else 209 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs); 210 211 /* Skip restoring fpexc32 for AArch64 guests */ 212 if (!(read_sysreg(hcr_el2) & HCR_RW)) 213 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2); 214 215 vcpu->arch.fp_state = FP_STATE_GUEST_OWNED; 216 217 return true; 218 } 219 220 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu) 221 { 222 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); 223 int rt = kvm_vcpu_sys_get_rt(vcpu); 224 u64 val = vcpu_get_reg(vcpu, rt); 225 226 /* 227 * The normal sysreg handling code expects to see the traps, 228 * let's not do anything here. 229 */ 230 if (vcpu->arch.hcr_el2 & HCR_TVM) 231 return false; 232 233 switch (sysreg) { 234 case SYS_SCTLR_EL1: 235 write_sysreg_el1(val, SYS_SCTLR); 236 break; 237 case SYS_TTBR0_EL1: 238 write_sysreg_el1(val, SYS_TTBR0); 239 break; 240 case SYS_TTBR1_EL1: 241 write_sysreg_el1(val, SYS_TTBR1); 242 break; 243 case SYS_TCR_EL1: 244 write_sysreg_el1(val, SYS_TCR); 245 break; 246 case SYS_ESR_EL1: 247 write_sysreg_el1(val, SYS_ESR); 248 break; 249 case SYS_FAR_EL1: 250 write_sysreg_el1(val, SYS_FAR); 251 break; 252 case SYS_AFSR0_EL1: 253 write_sysreg_el1(val, SYS_AFSR0); 254 break; 255 case SYS_AFSR1_EL1: 256 write_sysreg_el1(val, SYS_AFSR1); 257 break; 258 case SYS_MAIR_EL1: 259 write_sysreg_el1(val, SYS_MAIR); 260 break; 261 case SYS_AMAIR_EL1: 262 write_sysreg_el1(val, SYS_AMAIR); 263 break; 264 case SYS_CONTEXTIDR_EL1: 265 write_sysreg_el1(val, SYS_CONTEXTIDR); 266 break; 267 default: 268 return false; 269 } 270 271 __kvm_skip_instr(vcpu); 272 return true; 273 } 274 275 static inline bool esr_is_ptrauth_trap(u64 esr) 276 { 277 switch (esr_sys64_to_sysreg(esr)) { 278 case SYS_APIAKEYLO_EL1: 279 case SYS_APIAKEYHI_EL1: 280 case SYS_APIBKEYLO_EL1: 281 case SYS_APIBKEYHI_EL1: 282 case SYS_APDAKEYLO_EL1: 283 case SYS_APDAKEYHI_EL1: 284 case SYS_APDBKEYLO_EL1: 285 case SYS_APDBKEYHI_EL1: 286 case SYS_APGAKEYLO_EL1: 287 case SYS_APGAKEYHI_EL1: 288 return true; 289 } 290 291 return false; 292 } 293 294 #define __ptrauth_save_key(ctxt, key) \ 295 do { \ 296 u64 __val; \ 297 __val = read_sysreg_s(SYS_ ## key ## KEYLO_EL1); \ 298 ctxt_sys_reg(ctxt, key ## KEYLO_EL1) = __val; \ 299 __val = read_sysreg_s(SYS_ ## key ## KEYHI_EL1); \ 300 ctxt_sys_reg(ctxt, key ## KEYHI_EL1) = __val; \ 301 } while(0) 302 303 DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 304 305 static bool kvm_hyp_handle_ptrauth(struct kvm_vcpu *vcpu, u64 *exit_code) 306 { 307 struct kvm_cpu_context *ctxt; 308 u64 val; 309 310 if (!vcpu_has_ptrauth(vcpu)) 311 return false; 312 313 ctxt = this_cpu_ptr(&kvm_hyp_ctxt); 314 __ptrauth_save_key(ctxt, APIA); 315 __ptrauth_save_key(ctxt, APIB); 316 __ptrauth_save_key(ctxt, APDA); 317 __ptrauth_save_key(ctxt, APDB); 318 __ptrauth_save_key(ctxt, APGA); 319 320 vcpu_ptrauth_enable(vcpu); 321 322 val = read_sysreg(hcr_el2); 323 val |= (HCR_API | HCR_APK); 324 write_sysreg(val, hcr_el2); 325 326 return true; 327 } 328 329 static bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code) 330 { 331 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) && 332 handle_tx2_tvm(vcpu)) 333 return true; 334 335 if (static_branch_unlikely(&vgic_v3_cpuif_trap) && 336 __vgic_v3_perform_cpuif_access(vcpu) == 1) 337 return true; 338 339 if (esr_is_ptrauth_trap(kvm_vcpu_get_esr(vcpu))) 340 return kvm_hyp_handle_ptrauth(vcpu, exit_code); 341 342 return false; 343 } 344 345 static bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code) 346 { 347 if (static_branch_unlikely(&vgic_v3_cpuif_trap) && 348 __vgic_v3_perform_cpuif_access(vcpu) == 1) 349 return true; 350 351 return false; 352 } 353 354 static bool kvm_hyp_handle_iabt_low(struct kvm_vcpu *vcpu, u64 *exit_code) 355 { 356 if (!__populate_fault_info(vcpu)) 357 return true; 358 359 return false; 360 } 361 362 static bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code) 363 { 364 if (!__populate_fault_info(vcpu)) 365 return true; 366 367 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) { 368 bool valid; 369 370 valid = kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT && 371 kvm_vcpu_dabt_isvalid(vcpu) && 372 !kvm_vcpu_abt_issea(vcpu) && 373 !kvm_vcpu_abt_iss1tw(vcpu); 374 375 if (valid) { 376 int ret = __vgic_v2_perform_cpuif_access(vcpu); 377 378 if (ret == 1) 379 return true; 380 381 /* Promote an illegal access to an SError.*/ 382 if (ret == -1) 383 *exit_code = ARM_EXCEPTION_EL1_SERROR; 384 } 385 } 386 387 return false; 388 } 389 390 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *); 391 392 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu); 393 394 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code); 395 396 /* 397 * Allow the hypervisor to handle the exit with an exit handler if it has one. 398 * 399 * Returns true if the hypervisor handled the exit, and control should go back 400 * to the guest, or false if it hasn't. 401 */ 402 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code) 403 { 404 const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu); 405 exit_handler_fn fn; 406 407 fn = handlers[kvm_vcpu_trap_get_class(vcpu)]; 408 409 if (fn) 410 return fn(vcpu, exit_code); 411 412 return false; 413 } 414 415 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code) 416 { 417 /* 418 * Check for the conditions of Cortex-A510's #2077057. When these occur 419 * SPSR_EL2 can't be trusted, but isn't needed either as it is 420 * unchanged from the value in vcpu_gp_regs(vcpu)->pstate. 421 * Are we single-stepping the guest, and took a PAC exception from the 422 * active-not-pending state? 423 */ 424 if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) && 425 vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 426 *vcpu_cpsr(vcpu) & DBG_SPSR_SS && 427 ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC) 428 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR); 429 430 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR); 431 } 432 433 /* 434 * Return true when we were able to fixup the guest exit and should return to 435 * the guest, false when we should restore the host state and return to the 436 * main run loop. 437 */ 438 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) 439 { 440 /* 441 * Save PSTATE early so that we can evaluate the vcpu mode 442 * early on. 443 */ 444 synchronize_vcpu_pstate(vcpu, exit_code); 445 446 /* 447 * Check whether we want to repaint the state one way or 448 * another. 449 */ 450 early_exit_filter(vcpu, exit_code); 451 452 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) 453 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR); 454 455 if (ARM_SERROR_PENDING(*exit_code) && 456 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) { 457 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 458 459 /* 460 * HVC already have an adjusted PC, which we need to 461 * correct in order to return to after having injected 462 * the SError. 463 * 464 * SMC, on the other hand, is *trapped*, meaning its 465 * preferred return address is the SMC itself. 466 */ 467 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64) 468 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR); 469 } 470 471 /* 472 * We're using the raw exception code in order to only process 473 * the trap if no SError is pending. We will come back to the 474 * same PC once the SError has been injected, and replay the 475 * trapping instruction. 476 */ 477 if (*exit_code != ARM_EXCEPTION_TRAP) 478 goto exit; 479 480 /* Check if there's an exit handler and allow it to handle the exit. */ 481 if (kvm_hyp_handle_exit(vcpu, exit_code)) 482 goto guest; 483 exit: 484 /* Return to the host kernel and handle the exit */ 485 return false; 486 487 guest: 488 /* Re-enter the guest */ 489 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); 490 return true; 491 } 492 493 static inline void __kvm_unexpected_el2_exception(void) 494 { 495 extern char __guest_exit_panic[]; 496 unsigned long addr, fixup; 497 struct kvm_exception_table_entry *entry, *end; 498 unsigned long elr_el2 = read_sysreg(elr_el2); 499 500 entry = &__start___kvm_ex_table; 501 end = &__stop___kvm_ex_table; 502 503 while (entry < end) { 504 addr = (unsigned long)&entry->insn + entry->insn; 505 fixup = (unsigned long)&entry->fixup + entry->fixup; 506 507 if (addr != elr_el2) { 508 entry++; 509 continue; 510 } 511 512 write_sysreg(fixup, elr_el2); 513 return; 514 } 515 516 /* Trigger a panic after restoring the hyp context. */ 517 write_sysreg(__guest_exit_panic, elr_el2); 518 } 519 520 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */ 521