1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_HYP_SWITCH_H__ 8 #define __ARM64_KVM_HYP_SWITCH_H__ 9 10 #include <hyp/adjust_pc.h> 11 #include <hyp/fault.h> 12 13 #include <linux/arm-smccc.h> 14 #include <linux/kvm_host.h> 15 #include <linux/types.h> 16 #include <linux/jump_label.h> 17 #include <uapi/linux/psci.h> 18 19 #include <kvm/arm_psci.h> 20 21 #include <asm/barrier.h> 22 #include <asm/cpufeature.h> 23 #include <asm/extable.h> 24 #include <asm/kprobes.h> 25 #include <asm/kvm_asm.h> 26 #include <asm/kvm_emulate.h> 27 #include <asm/kvm_hyp.h> 28 #include <asm/kvm_mmu.h> 29 #include <asm/fpsimd.h> 30 #include <asm/debug-monitors.h> 31 #include <asm/processor.h> 32 33 struct kvm_exception_table_entry { 34 int insn, fixup; 35 }; 36 37 extern struct kvm_exception_table_entry __start___kvm_ex_table; 38 extern struct kvm_exception_table_entry __stop___kvm_ex_table; 39 40 /* Check whether the FP regs are owned by the guest */ 41 static inline bool guest_owns_fp_regs(struct kvm_vcpu *vcpu) 42 { 43 return vcpu->arch.fp_state == FP_STATE_GUEST_OWNED; 44 } 45 46 /* Save the 32-bit only FPSIMD system register state */ 47 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu) 48 { 49 if (!vcpu_el1_is_32bit(vcpu)) 50 return; 51 52 __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2); 53 } 54 55 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu) 56 { 57 /* 58 * We are about to set CPTR_EL2.TFP to trap all floating point 59 * register accesses to EL2, however, the ARM ARM clearly states that 60 * traps are only taken to EL2 if the operation would not otherwise 61 * trap to EL1. Therefore, always make sure that for 32-bit guests, 62 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit. 63 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to 64 * it will cause an exception. 65 */ 66 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) { 67 write_sysreg(1 << 30, fpexc32_el2); 68 isb(); 69 } 70 } 71 72 static inline void __activate_traps_common(struct kvm_vcpu *vcpu) 73 { 74 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */ 75 write_sysreg(1 << 15, hstr_el2); 76 77 /* 78 * Make sure we trap PMU access from EL0 to EL2. Also sanitize 79 * PMSELR_EL0 to make sure it never contains the cycle 80 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at 81 * EL1 instead of being trapped to EL2. 82 */ 83 if (kvm_arm_support_pmu_v3()) { 84 write_sysreg(0, pmselr_el0); 85 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); 86 } 87 88 vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2); 89 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); 90 } 91 92 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) 93 { 94 write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2); 95 96 write_sysreg(0, hstr_el2); 97 if (kvm_arm_support_pmu_v3()) 98 write_sysreg(0, pmuserenr_el0); 99 } 100 101 static inline void ___activate_traps(struct kvm_vcpu *vcpu) 102 { 103 u64 hcr = vcpu->arch.hcr_el2; 104 105 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM)) 106 hcr |= HCR_TVM; 107 108 write_sysreg(hcr, hcr_el2); 109 110 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE)) 111 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2); 112 } 113 114 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu) 115 { 116 /* 117 * If we pended a virtual abort, preserve it until it gets 118 * cleared. See D1.14.3 (Virtual Interrupts) for details, but 119 * the crucial bit is "On taking a vSError interrupt, 120 * HCR_EL2.VSE is cleared to 0." 121 */ 122 if (vcpu->arch.hcr_el2 & HCR_VSE) { 123 vcpu->arch.hcr_el2 &= ~HCR_VSE; 124 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE; 125 } 126 } 127 128 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu) 129 { 130 return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault); 131 } 132 133 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu) 134 { 135 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2); 136 __sve_restore_state(vcpu_sve_pffr(vcpu), 137 &vcpu->arch.ctxt.fp_regs.fpsr); 138 write_sysreg_el1(__vcpu_sys_reg(vcpu, ZCR_EL1), SYS_ZCR); 139 } 140 141 /* 142 * We trap the first access to the FP/SIMD to save the host context and 143 * restore the guest context lazily. 144 * If FP/SIMD is not implemented, handle the trap and inject an undefined 145 * instruction exception to the guest. Similarly for trapped SVE accesses. 146 */ 147 static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code) 148 { 149 bool sve_guest; 150 u8 esr_ec; 151 u64 reg; 152 153 if (!system_supports_fpsimd()) 154 return false; 155 156 sve_guest = vcpu_has_sve(vcpu); 157 esr_ec = kvm_vcpu_trap_get_class(vcpu); 158 159 /* Don't handle SVE traps for non-SVE vcpus here: */ 160 if (!sve_guest && esr_ec != ESR_ELx_EC_FP_ASIMD) 161 return false; 162 163 /* Valid trap. Switch the context: */ 164 165 /* First disable enough traps to allow us to update the registers */ 166 if (has_vhe()) { 167 reg = CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN; 168 if (sve_guest) 169 reg |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN; 170 171 sysreg_clear_set(cpacr_el1, 0, reg); 172 } else { 173 reg = CPTR_EL2_TFP; 174 if (sve_guest) 175 reg |= CPTR_EL2_TZ; 176 177 sysreg_clear_set(cptr_el2, reg, 0); 178 } 179 isb(); 180 181 /* Write out the host state if it's in the registers */ 182 if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED) 183 __fpsimd_save_state(vcpu->arch.host_fpsimd_state); 184 185 /* Restore the guest state */ 186 if (sve_guest) 187 __hyp_sve_restore_guest(vcpu); 188 else 189 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs); 190 191 /* Skip restoring fpexc32 for AArch64 guests */ 192 if (!(read_sysreg(hcr_el2) & HCR_RW)) 193 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2); 194 195 vcpu->arch.fp_state = FP_STATE_GUEST_OWNED; 196 197 return true; 198 } 199 200 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu) 201 { 202 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); 203 int rt = kvm_vcpu_sys_get_rt(vcpu); 204 u64 val = vcpu_get_reg(vcpu, rt); 205 206 /* 207 * The normal sysreg handling code expects to see the traps, 208 * let's not do anything here. 209 */ 210 if (vcpu->arch.hcr_el2 & HCR_TVM) 211 return false; 212 213 switch (sysreg) { 214 case SYS_SCTLR_EL1: 215 write_sysreg_el1(val, SYS_SCTLR); 216 break; 217 case SYS_TTBR0_EL1: 218 write_sysreg_el1(val, SYS_TTBR0); 219 break; 220 case SYS_TTBR1_EL1: 221 write_sysreg_el1(val, SYS_TTBR1); 222 break; 223 case SYS_TCR_EL1: 224 write_sysreg_el1(val, SYS_TCR); 225 break; 226 case SYS_ESR_EL1: 227 write_sysreg_el1(val, SYS_ESR); 228 break; 229 case SYS_FAR_EL1: 230 write_sysreg_el1(val, SYS_FAR); 231 break; 232 case SYS_AFSR0_EL1: 233 write_sysreg_el1(val, SYS_AFSR0); 234 break; 235 case SYS_AFSR1_EL1: 236 write_sysreg_el1(val, SYS_AFSR1); 237 break; 238 case SYS_MAIR_EL1: 239 write_sysreg_el1(val, SYS_MAIR); 240 break; 241 case SYS_AMAIR_EL1: 242 write_sysreg_el1(val, SYS_AMAIR); 243 break; 244 case SYS_CONTEXTIDR_EL1: 245 write_sysreg_el1(val, SYS_CONTEXTIDR); 246 break; 247 default: 248 return false; 249 } 250 251 __kvm_skip_instr(vcpu); 252 return true; 253 } 254 255 static inline bool esr_is_ptrauth_trap(u64 esr) 256 { 257 switch (esr_sys64_to_sysreg(esr)) { 258 case SYS_APIAKEYLO_EL1: 259 case SYS_APIAKEYHI_EL1: 260 case SYS_APIBKEYLO_EL1: 261 case SYS_APIBKEYHI_EL1: 262 case SYS_APDAKEYLO_EL1: 263 case SYS_APDAKEYHI_EL1: 264 case SYS_APDBKEYLO_EL1: 265 case SYS_APDBKEYHI_EL1: 266 case SYS_APGAKEYLO_EL1: 267 case SYS_APGAKEYHI_EL1: 268 return true; 269 } 270 271 return false; 272 } 273 274 #define __ptrauth_save_key(ctxt, key) \ 275 do { \ 276 u64 __val; \ 277 __val = read_sysreg_s(SYS_ ## key ## KEYLO_EL1); \ 278 ctxt_sys_reg(ctxt, key ## KEYLO_EL1) = __val; \ 279 __val = read_sysreg_s(SYS_ ## key ## KEYHI_EL1); \ 280 ctxt_sys_reg(ctxt, key ## KEYHI_EL1) = __val; \ 281 } while(0) 282 283 DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 284 285 static bool kvm_hyp_handle_ptrauth(struct kvm_vcpu *vcpu, u64 *exit_code) 286 { 287 struct kvm_cpu_context *ctxt; 288 u64 val; 289 290 if (!vcpu_has_ptrauth(vcpu)) 291 return false; 292 293 ctxt = this_cpu_ptr(&kvm_hyp_ctxt); 294 __ptrauth_save_key(ctxt, APIA); 295 __ptrauth_save_key(ctxt, APIB); 296 __ptrauth_save_key(ctxt, APDA); 297 __ptrauth_save_key(ctxt, APDB); 298 __ptrauth_save_key(ctxt, APGA); 299 300 vcpu_ptrauth_enable(vcpu); 301 302 val = read_sysreg(hcr_el2); 303 val |= (HCR_API | HCR_APK); 304 write_sysreg(val, hcr_el2); 305 306 return true; 307 } 308 309 static bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code) 310 { 311 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) && 312 handle_tx2_tvm(vcpu)) 313 return true; 314 315 if (static_branch_unlikely(&vgic_v3_cpuif_trap) && 316 __vgic_v3_perform_cpuif_access(vcpu) == 1) 317 return true; 318 319 if (esr_is_ptrauth_trap(kvm_vcpu_get_esr(vcpu))) 320 return kvm_hyp_handle_ptrauth(vcpu, exit_code); 321 322 return false; 323 } 324 325 static bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code) 326 { 327 if (static_branch_unlikely(&vgic_v3_cpuif_trap) && 328 __vgic_v3_perform_cpuif_access(vcpu) == 1) 329 return true; 330 331 return false; 332 } 333 334 static bool kvm_hyp_handle_iabt_low(struct kvm_vcpu *vcpu, u64 *exit_code) 335 { 336 if (!__populate_fault_info(vcpu)) 337 return true; 338 339 return false; 340 } 341 342 static bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code) 343 { 344 if (!__populate_fault_info(vcpu)) 345 return true; 346 347 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) { 348 bool valid; 349 350 valid = kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT && 351 kvm_vcpu_dabt_isvalid(vcpu) && 352 !kvm_vcpu_abt_issea(vcpu) && 353 !kvm_vcpu_abt_iss1tw(vcpu); 354 355 if (valid) { 356 int ret = __vgic_v2_perform_cpuif_access(vcpu); 357 358 if (ret == 1) 359 return true; 360 361 /* Promote an illegal access to an SError.*/ 362 if (ret == -1) 363 *exit_code = ARM_EXCEPTION_EL1_SERROR; 364 } 365 } 366 367 return false; 368 } 369 370 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *); 371 372 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu); 373 374 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code); 375 376 /* 377 * Allow the hypervisor to handle the exit with an exit handler if it has one. 378 * 379 * Returns true if the hypervisor handled the exit, and control should go back 380 * to the guest, or false if it hasn't. 381 */ 382 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code) 383 { 384 const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu); 385 exit_handler_fn fn; 386 387 fn = handlers[kvm_vcpu_trap_get_class(vcpu)]; 388 389 if (fn) 390 return fn(vcpu, exit_code); 391 392 return false; 393 } 394 395 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code) 396 { 397 /* 398 * Check for the conditions of Cortex-A510's #2077057. When these occur 399 * SPSR_EL2 can't be trusted, but isn't needed either as it is 400 * unchanged from the value in vcpu_gp_regs(vcpu)->pstate. 401 * Are we single-stepping the guest, and took a PAC exception from the 402 * active-not-pending state? 403 */ 404 if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) && 405 vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 406 *vcpu_cpsr(vcpu) & DBG_SPSR_SS && 407 ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC) 408 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR); 409 410 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR); 411 } 412 413 /* 414 * Return true when we were able to fixup the guest exit and should return to 415 * the guest, false when we should restore the host state and return to the 416 * main run loop. 417 */ 418 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) 419 { 420 /* 421 * Save PSTATE early so that we can evaluate the vcpu mode 422 * early on. 423 */ 424 synchronize_vcpu_pstate(vcpu, exit_code); 425 426 /* 427 * Check whether we want to repaint the state one way or 428 * another. 429 */ 430 early_exit_filter(vcpu, exit_code); 431 432 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) 433 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR); 434 435 if (ARM_SERROR_PENDING(*exit_code) && 436 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) { 437 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 438 439 /* 440 * HVC already have an adjusted PC, which we need to 441 * correct in order to return to after having injected 442 * the SError. 443 * 444 * SMC, on the other hand, is *trapped*, meaning its 445 * preferred return address is the SMC itself. 446 */ 447 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64) 448 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR); 449 } 450 451 /* 452 * We're using the raw exception code in order to only process 453 * the trap if no SError is pending. We will come back to the 454 * same PC once the SError has been injected, and replay the 455 * trapping instruction. 456 */ 457 if (*exit_code != ARM_EXCEPTION_TRAP) 458 goto exit; 459 460 /* Check if there's an exit handler and allow it to handle the exit. */ 461 if (kvm_hyp_handle_exit(vcpu, exit_code)) 462 goto guest; 463 exit: 464 /* Return to the host kernel and handle the exit */ 465 return false; 466 467 guest: 468 /* Re-enter the guest */ 469 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); 470 return true; 471 } 472 473 static inline void __kvm_unexpected_el2_exception(void) 474 { 475 extern char __guest_exit_panic[]; 476 unsigned long addr, fixup; 477 struct kvm_exception_table_entry *entry, *end; 478 unsigned long elr_el2 = read_sysreg(elr_el2); 479 480 entry = &__start___kvm_ex_table; 481 end = &__stop___kvm_ex_table; 482 483 while (entry < end) { 484 addr = (unsigned long)&entry->insn + entry->insn; 485 fixup = (unsigned long)&entry->fixup + entry->fixup; 486 487 if (addr != elr_el2) { 488 entry++; 489 continue; 490 } 491 492 write_sysreg(fixup, elr_el2); 493 return; 494 } 495 496 /* Trigger a panic after restoring the hyp context. */ 497 write_sysreg(__guest_exit_panic, elr_el2); 498 } 499 500 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */ 501