1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_HYP_SWITCH_H__ 8 #define __ARM64_KVM_HYP_SWITCH_H__ 9 10 #include <hyp/adjust_pc.h> 11 #include <hyp/fault.h> 12 13 #include <linux/arm-smccc.h> 14 #include <linux/kvm_host.h> 15 #include <linux/types.h> 16 #include <linux/jump_label.h> 17 #include <uapi/linux/psci.h> 18 19 #include <kvm/arm_psci.h> 20 21 #include <asm/barrier.h> 22 #include <asm/cpufeature.h> 23 #include <asm/extable.h> 24 #include <asm/kprobes.h> 25 #include <asm/kvm_asm.h> 26 #include <asm/kvm_emulate.h> 27 #include <asm/kvm_hyp.h> 28 #include <asm/kvm_mmu.h> 29 #include <asm/kvm_nested.h> 30 #include <asm/fpsimd.h> 31 #include <asm/debug-monitors.h> 32 #include <asm/processor.h> 33 34 struct kvm_exception_table_entry { 35 int insn, fixup; 36 }; 37 38 extern struct kvm_exception_table_entry __start___kvm_ex_table; 39 extern struct kvm_exception_table_entry __stop___kvm_ex_table; 40 41 /* Check whether the FP regs are owned by the guest */ 42 static inline bool guest_owns_fp_regs(struct kvm_vcpu *vcpu) 43 { 44 return vcpu->arch.fp_state == FP_STATE_GUEST_OWNED; 45 } 46 47 /* Save the 32-bit only FPSIMD system register state */ 48 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu) 49 { 50 if (!vcpu_el1_is_32bit(vcpu)) 51 return; 52 53 __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2); 54 } 55 56 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu) 57 { 58 /* 59 * We are about to set CPTR_EL2.TFP to trap all floating point 60 * register accesses to EL2, however, the ARM ARM clearly states that 61 * traps are only taken to EL2 if the operation would not otherwise 62 * trap to EL1. Therefore, always make sure that for 32-bit guests, 63 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit. 64 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to 65 * it will cause an exception. 66 */ 67 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) { 68 write_sysreg(1 << 30, fpexc32_el2); 69 isb(); 70 } 71 } 72 73 static inline void __activate_traps_common(struct kvm_vcpu *vcpu) 74 { 75 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */ 76 write_sysreg(1 << 15, hstr_el2); 77 78 /* 79 * Make sure we trap PMU access from EL0 to EL2. Also sanitize 80 * PMSELR_EL0 to make sure it never contains the cycle 81 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at 82 * EL1 instead of being trapped to EL2. 83 */ 84 if (kvm_arm_support_pmu_v3()) { 85 write_sysreg(0, pmselr_el0); 86 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); 87 } 88 89 vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2); 90 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); 91 92 if (cpus_have_final_cap(ARM64_SME)) { 93 sysreg_clear_set_s(SYS_HFGRTR_EL2, 94 HFGxTR_EL2_nSMPRI_EL1_MASK | 95 HFGxTR_EL2_nTPIDR2_EL0_MASK, 96 0); 97 sysreg_clear_set_s(SYS_HFGWTR_EL2, 98 HFGxTR_EL2_nSMPRI_EL1_MASK | 99 HFGxTR_EL2_nTPIDR2_EL0_MASK, 100 0); 101 } 102 } 103 104 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) 105 { 106 write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2); 107 108 write_sysreg(0, hstr_el2); 109 if (kvm_arm_support_pmu_v3()) 110 write_sysreg(0, pmuserenr_el0); 111 112 if (cpus_have_final_cap(ARM64_SME)) { 113 sysreg_clear_set_s(SYS_HFGRTR_EL2, 0, 114 HFGxTR_EL2_nSMPRI_EL1_MASK | 115 HFGxTR_EL2_nTPIDR2_EL0_MASK); 116 sysreg_clear_set_s(SYS_HFGWTR_EL2, 0, 117 HFGxTR_EL2_nSMPRI_EL1_MASK | 118 HFGxTR_EL2_nTPIDR2_EL0_MASK); 119 } 120 } 121 122 static inline void ___activate_traps(struct kvm_vcpu *vcpu) 123 { 124 u64 hcr = vcpu->arch.hcr_el2; 125 126 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM)) 127 hcr |= HCR_TVM; 128 129 write_sysreg(hcr, hcr_el2); 130 131 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE)) 132 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2); 133 } 134 135 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu) 136 { 137 /* 138 * If we pended a virtual abort, preserve it until it gets 139 * cleared. See D1.14.3 (Virtual Interrupts) for details, but 140 * the crucial bit is "On taking a vSError interrupt, 141 * HCR_EL2.VSE is cleared to 0." 142 */ 143 if (vcpu->arch.hcr_el2 & HCR_VSE) { 144 vcpu->arch.hcr_el2 &= ~HCR_VSE; 145 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE; 146 } 147 } 148 149 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu) 150 { 151 return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault); 152 } 153 154 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu) 155 { 156 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2); 157 __sve_restore_state(vcpu_sve_pffr(vcpu), 158 &vcpu->arch.ctxt.fp_regs.fpsr); 159 write_sysreg_el1(__vcpu_sys_reg(vcpu, ZCR_EL1), SYS_ZCR); 160 } 161 162 /* 163 * We trap the first access to the FP/SIMD to save the host context and 164 * restore the guest context lazily. 165 * If FP/SIMD is not implemented, handle the trap and inject an undefined 166 * instruction exception to the guest. Similarly for trapped SVE accesses. 167 */ 168 static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code) 169 { 170 bool sve_guest; 171 u8 esr_ec; 172 u64 reg; 173 174 if (!system_supports_fpsimd()) 175 return false; 176 177 sve_guest = vcpu_has_sve(vcpu); 178 esr_ec = kvm_vcpu_trap_get_class(vcpu); 179 180 /* Don't handle SVE traps for non-SVE vcpus here: */ 181 if (!sve_guest && esr_ec != ESR_ELx_EC_FP_ASIMD) 182 return false; 183 184 /* Valid trap. Switch the context: */ 185 186 /* First disable enough traps to allow us to update the registers */ 187 if (has_vhe()) { 188 reg = CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN; 189 if (sve_guest) 190 reg |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN; 191 192 sysreg_clear_set(cpacr_el1, 0, reg); 193 } else { 194 reg = CPTR_EL2_TFP; 195 if (sve_guest) 196 reg |= CPTR_EL2_TZ; 197 198 sysreg_clear_set(cptr_el2, reg, 0); 199 } 200 isb(); 201 202 /* Write out the host state if it's in the registers */ 203 if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED) 204 __fpsimd_save_state(vcpu->arch.host_fpsimd_state); 205 206 /* Restore the guest state */ 207 if (sve_guest) 208 __hyp_sve_restore_guest(vcpu); 209 else 210 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs); 211 212 /* Skip restoring fpexc32 for AArch64 guests */ 213 if (!(read_sysreg(hcr_el2) & HCR_RW)) 214 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2); 215 216 vcpu->arch.fp_state = FP_STATE_GUEST_OWNED; 217 218 return true; 219 } 220 221 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu) 222 { 223 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); 224 int rt = kvm_vcpu_sys_get_rt(vcpu); 225 u64 val = vcpu_get_reg(vcpu, rt); 226 227 /* 228 * The normal sysreg handling code expects to see the traps, 229 * let's not do anything here. 230 */ 231 if (vcpu->arch.hcr_el2 & HCR_TVM) 232 return false; 233 234 switch (sysreg) { 235 case SYS_SCTLR_EL1: 236 write_sysreg_el1(val, SYS_SCTLR); 237 break; 238 case SYS_TTBR0_EL1: 239 write_sysreg_el1(val, SYS_TTBR0); 240 break; 241 case SYS_TTBR1_EL1: 242 write_sysreg_el1(val, SYS_TTBR1); 243 break; 244 case SYS_TCR_EL1: 245 write_sysreg_el1(val, SYS_TCR); 246 break; 247 case SYS_ESR_EL1: 248 write_sysreg_el1(val, SYS_ESR); 249 break; 250 case SYS_FAR_EL1: 251 write_sysreg_el1(val, SYS_FAR); 252 break; 253 case SYS_AFSR0_EL1: 254 write_sysreg_el1(val, SYS_AFSR0); 255 break; 256 case SYS_AFSR1_EL1: 257 write_sysreg_el1(val, SYS_AFSR1); 258 break; 259 case SYS_MAIR_EL1: 260 write_sysreg_el1(val, SYS_MAIR); 261 break; 262 case SYS_AMAIR_EL1: 263 write_sysreg_el1(val, SYS_AMAIR); 264 break; 265 case SYS_CONTEXTIDR_EL1: 266 write_sysreg_el1(val, SYS_CONTEXTIDR); 267 break; 268 default: 269 return false; 270 } 271 272 __kvm_skip_instr(vcpu); 273 return true; 274 } 275 276 static inline bool esr_is_ptrauth_trap(u64 esr) 277 { 278 switch (esr_sys64_to_sysreg(esr)) { 279 case SYS_APIAKEYLO_EL1: 280 case SYS_APIAKEYHI_EL1: 281 case SYS_APIBKEYLO_EL1: 282 case SYS_APIBKEYHI_EL1: 283 case SYS_APDAKEYLO_EL1: 284 case SYS_APDAKEYHI_EL1: 285 case SYS_APDBKEYLO_EL1: 286 case SYS_APDBKEYHI_EL1: 287 case SYS_APGAKEYLO_EL1: 288 case SYS_APGAKEYHI_EL1: 289 return true; 290 } 291 292 return false; 293 } 294 295 #define __ptrauth_save_key(ctxt, key) \ 296 do { \ 297 u64 __val; \ 298 __val = read_sysreg_s(SYS_ ## key ## KEYLO_EL1); \ 299 ctxt_sys_reg(ctxt, key ## KEYLO_EL1) = __val; \ 300 __val = read_sysreg_s(SYS_ ## key ## KEYHI_EL1); \ 301 ctxt_sys_reg(ctxt, key ## KEYHI_EL1) = __val; \ 302 } while(0) 303 304 DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 305 306 static bool kvm_hyp_handle_ptrauth(struct kvm_vcpu *vcpu, u64 *exit_code) 307 { 308 struct kvm_cpu_context *ctxt; 309 u64 val; 310 311 if (!vcpu_has_ptrauth(vcpu)) 312 return false; 313 314 ctxt = this_cpu_ptr(&kvm_hyp_ctxt); 315 __ptrauth_save_key(ctxt, APIA); 316 __ptrauth_save_key(ctxt, APIB); 317 __ptrauth_save_key(ctxt, APDA); 318 __ptrauth_save_key(ctxt, APDB); 319 __ptrauth_save_key(ctxt, APGA); 320 321 vcpu_ptrauth_enable(vcpu); 322 323 val = read_sysreg(hcr_el2); 324 val |= (HCR_API | HCR_APK); 325 write_sysreg(val, hcr_el2); 326 327 return true; 328 } 329 330 static bool kvm_hyp_handle_cntpct(struct kvm_vcpu *vcpu) 331 { 332 struct arch_timer_context *ctxt; 333 u32 sysreg; 334 u64 val; 335 336 /* 337 * We only get here for 64bit guests, 32bit guests will hit 338 * the long and winding road all the way to the standard 339 * handling. Yes, it sucks to be irrelevant. 340 */ 341 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); 342 343 switch (sysreg) { 344 case SYS_CNTPCT_EL0: 345 case SYS_CNTPCTSS_EL0: 346 if (vcpu_has_nv(vcpu)) { 347 if (is_hyp_ctxt(vcpu)) { 348 ctxt = vcpu_hptimer(vcpu); 349 break; 350 } 351 352 /* Check for guest hypervisor trapping */ 353 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2); 354 if (!vcpu_el2_e2h_is_set(vcpu)) 355 val = (val & CNTHCTL_EL1PCTEN) << 10; 356 357 if (!(val & (CNTHCTL_EL1PCTEN << 10))) 358 return false; 359 } 360 361 ctxt = vcpu_ptimer(vcpu); 362 break; 363 default: 364 return false; 365 } 366 367 val = arch_timer_read_cntpct_el0(); 368 369 if (ctxt->offset.vm_offset) 370 val -= *kern_hyp_va(ctxt->offset.vm_offset); 371 if (ctxt->offset.vcpu_offset) 372 val -= *kern_hyp_va(ctxt->offset.vcpu_offset); 373 374 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val); 375 __kvm_skip_instr(vcpu); 376 return true; 377 } 378 379 static bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code) 380 { 381 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) && 382 handle_tx2_tvm(vcpu)) 383 return true; 384 385 if (static_branch_unlikely(&vgic_v3_cpuif_trap) && 386 __vgic_v3_perform_cpuif_access(vcpu) == 1) 387 return true; 388 389 if (esr_is_ptrauth_trap(kvm_vcpu_get_esr(vcpu))) 390 return kvm_hyp_handle_ptrauth(vcpu, exit_code); 391 392 if (kvm_hyp_handle_cntpct(vcpu)) 393 return true; 394 395 return false; 396 } 397 398 static bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code) 399 { 400 if (static_branch_unlikely(&vgic_v3_cpuif_trap) && 401 __vgic_v3_perform_cpuif_access(vcpu) == 1) 402 return true; 403 404 return false; 405 } 406 407 static bool kvm_hyp_handle_iabt_low(struct kvm_vcpu *vcpu, u64 *exit_code) 408 { 409 if (!__populate_fault_info(vcpu)) 410 return true; 411 412 return false; 413 } 414 415 static bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code) 416 { 417 if (!__populate_fault_info(vcpu)) 418 return true; 419 420 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) { 421 bool valid; 422 423 valid = kvm_vcpu_trap_get_fault_type(vcpu) == ESR_ELx_FSC_FAULT && 424 kvm_vcpu_dabt_isvalid(vcpu) && 425 !kvm_vcpu_abt_issea(vcpu) && 426 !kvm_vcpu_abt_iss1tw(vcpu); 427 428 if (valid) { 429 int ret = __vgic_v2_perform_cpuif_access(vcpu); 430 431 if (ret == 1) 432 return true; 433 434 /* Promote an illegal access to an SError.*/ 435 if (ret == -1) 436 *exit_code = ARM_EXCEPTION_EL1_SERROR; 437 } 438 } 439 440 return false; 441 } 442 443 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *); 444 445 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu); 446 447 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code); 448 449 /* 450 * Allow the hypervisor to handle the exit with an exit handler if it has one. 451 * 452 * Returns true if the hypervisor handled the exit, and control should go back 453 * to the guest, or false if it hasn't. 454 */ 455 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code) 456 { 457 const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu); 458 exit_handler_fn fn; 459 460 fn = handlers[kvm_vcpu_trap_get_class(vcpu)]; 461 462 if (fn) 463 return fn(vcpu, exit_code); 464 465 return false; 466 } 467 468 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code) 469 { 470 /* 471 * Check for the conditions of Cortex-A510's #2077057. When these occur 472 * SPSR_EL2 can't be trusted, but isn't needed either as it is 473 * unchanged from the value in vcpu_gp_regs(vcpu)->pstate. 474 * Are we single-stepping the guest, and took a PAC exception from the 475 * active-not-pending state? 476 */ 477 if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) && 478 vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 479 *vcpu_cpsr(vcpu) & DBG_SPSR_SS && 480 ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC) 481 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR); 482 483 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR); 484 } 485 486 /* 487 * Return true when we were able to fixup the guest exit and should return to 488 * the guest, false when we should restore the host state and return to the 489 * main run loop. 490 */ 491 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) 492 { 493 /* 494 * Save PSTATE early so that we can evaluate the vcpu mode 495 * early on. 496 */ 497 synchronize_vcpu_pstate(vcpu, exit_code); 498 499 /* 500 * Check whether we want to repaint the state one way or 501 * another. 502 */ 503 early_exit_filter(vcpu, exit_code); 504 505 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) 506 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR); 507 508 if (ARM_SERROR_PENDING(*exit_code) && 509 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) { 510 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 511 512 /* 513 * HVC already have an adjusted PC, which we need to 514 * correct in order to return to after having injected 515 * the SError. 516 * 517 * SMC, on the other hand, is *trapped*, meaning its 518 * preferred return address is the SMC itself. 519 */ 520 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64) 521 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR); 522 } 523 524 /* 525 * We're using the raw exception code in order to only process 526 * the trap if no SError is pending. We will come back to the 527 * same PC once the SError has been injected, and replay the 528 * trapping instruction. 529 */ 530 if (*exit_code != ARM_EXCEPTION_TRAP) 531 goto exit; 532 533 /* Check if there's an exit handler and allow it to handle the exit. */ 534 if (kvm_hyp_handle_exit(vcpu, exit_code)) 535 goto guest; 536 exit: 537 /* Return to the host kernel and handle the exit */ 538 return false; 539 540 guest: 541 /* Re-enter the guest */ 542 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); 543 return true; 544 } 545 546 static inline void __kvm_unexpected_el2_exception(void) 547 { 548 extern char __guest_exit_panic[]; 549 unsigned long addr, fixup; 550 struct kvm_exception_table_entry *entry, *end; 551 unsigned long elr_el2 = read_sysreg(elr_el2); 552 553 entry = &__start___kvm_ex_table; 554 end = &__stop___kvm_ex_table; 555 556 while (entry < end) { 557 addr = (unsigned long)&entry->insn + entry->insn; 558 fixup = (unsigned long)&entry->fixup + entry->fixup; 559 560 if (addr != elr_el2) { 561 entry++; 562 continue; 563 } 564 565 write_sysreg(fixup, elr_el2); 566 return; 567 } 568 569 /* Trigger a panic after restoring the hyp context. */ 570 write_sysreg(__guest_exit_panic, elr_el2); 571 } 572 573 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */ 574