1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Fault injection for both 32 and 64bit guests. 4 * 5 * Copyright (C) 2012,2013 - ARM Ltd 6 * Author: Marc Zyngier <marc.zyngier@arm.com> 7 * 8 * Based on arch/arm/kvm/emulate.c 9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 10 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 11 */ 12 13 #include <hyp/adjust_pc.h> 14 #include <linux/kvm_host.h> 15 #include <asm/kvm_emulate.h> 16 17 #if !defined (__KVM_NVHE_HYPERVISOR__) && !defined (__KVM_VHE_HYPERVISOR__) 18 #error Hypervisor code only! 19 #endif 20 21 static inline u64 __vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 22 { 23 u64 val; 24 25 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 26 return val; 27 28 return __vcpu_sys_reg(vcpu, reg); 29 } 30 31 static inline void __vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 32 { 33 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 34 return; 35 36 __vcpu_sys_reg(vcpu, reg) = val; 37 } 38 39 static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, u64 val) 40 { 41 if (has_vhe()) 42 write_sysreg_el1(val, SYS_SPSR); 43 else 44 __vcpu_sys_reg(vcpu, SPSR_EL1) = val; 45 } 46 47 static void __vcpu_write_spsr_abt(struct kvm_vcpu *vcpu, u64 val) 48 { 49 if (has_vhe()) 50 write_sysreg(val, spsr_abt); 51 else 52 vcpu->arch.ctxt.spsr_abt = val; 53 } 54 55 static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu, u64 val) 56 { 57 if (has_vhe()) 58 write_sysreg(val, spsr_und); 59 else 60 vcpu->arch.ctxt.spsr_und = val; 61 } 62 63 /* 64 * This performs the exception entry at a given EL (@target_mode), stashing PC 65 * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTATE. 66 * The EL passed to this function *must* be a non-secure, privileged mode with 67 * bit 0 being set (PSTATE.SP == 1). 68 * 69 * When an exception is taken, most PSTATE fields are left unchanged in the 70 * handler. However, some are explicitly overridden (e.g. M[4:0]). Luckily all 71 * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx 72 * layouts, so we don't need to shuffle these for exceptions from AArch32 EL0. 73 * 74 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429. 75 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426. 76 * 77 * Here we manipulate the fields in order of the AArch64 SPSR_ELx layout, from 78 * MSB to LSB. 79 */ 80 static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode, 81 enum exception_type type) 82 { 83 unsigned long sctlr, vbar, old, new, mode; 84 u64 exc_offset; 85 86 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT); 87 88 if (mode == target_mode) 89 exc_offset = CURRENT_EL_SP_ELx_VECTOR; 90 else if ((mode | PSR_MODE_THREAD_BIT) == target_mode) 91 exc_offset = CURRENT_EL_SP_EL0_VECTOR; 92 else if (!(mode & PSR_MODE32_BIT)) 93 exc_offset = LOWER_EL_AArch64_VECTOR; 94 else 95 exc_offset = LOWER_EL_AArch32_VECTOR; 96 97 switch (target_mode) { 98 case PSR_MODE_EL1h: 99 vbar = __vcpu_read_sys_reg(vcpu, VBAR_EL1); 100 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1); 101 __vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL1); 102 break; 103 default: 104 /* Don't do that */ 105 BUG(); 106 } 107 108 *vcpu_pc(vcpu) = vbar + exc_offset + type; 109 110 old = *vcpu_cpsr(vcpu); 111 new = 0; 112 113 new |= (old & PSR_N_BIT); 114 new |= (old & PSR_Z_BIT); 115 new |= (old & PSR_C_BIT); 116 new |= (old & PSR_V_BIT); 117 118 if (kvm_has_mte(vcpu->kvm)) 119 new |= PSR_TCO_BIT; 120 121 new |= (old & PSR_DIT_BIT); 122 123 // PSTATE.UAO is set to zero upon any exception to AArch64 124 // See ARM DDI 0487E.a, page D5-2579. 125 126 // PSTATE.PAN is unchanged unless SCTLR_ELx.SPAN == 0b0 127 // SCTLR_ELx.SPAN is RES1 when ARMv8.1-PAN is not implemented 128 // See ARM DDI 0487E.a, page D5-2578. 129 new |= (old & PSR_PAN_BIT); 130 if (!(sctlr & SCTLR_EL1_SPAN)) 131 new |= PSR_PAN_BIT; 132 133 // PSTATE.SS is set to zero upon any exception to AArch64 134 // See ARM DDI 0487E.a, page D2-2452. 135 136 // PSTATE.IL is set to zero upon any exception to AArch64 137 // See ARM DDI 0487E.a, page D1-2306. 138 139 // PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64 140 // See ARM DDI 0487E.a, page D13-3258 141 if (sctlr & SCTLR_ELx_DSSBS) 142 new |= PSR_SSBS_BIT; 143 144 // PSTATE.BTYPE is set to zero upon any exception to AArch64 145 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. 146 147 new |= PSR_D_BIT; 148 new |= PSR_A_BIT; 149 new |= PSR_I_BIT; 150 new |= PSR_F_BIT; 151 152 new |= target_mode; 153 154 *vcpu_cpsr(vcpu) = new; 155 __vcpu_write_spsr(vcpu, old); 156 } 157 158 /* 159 * When an exception is taken, most CPSR fields are left unchanged in the 160 * handler. However, some are explicitly overridden (e.g. M[4:0]). 161 * 162 * The SPSR/SPSR_ELx layouts differ, and the below is intended to work with 163 * either format. Note: SPSR.J bit doesn't exist in SPSR_ELx, but this bit was 164 * obsoleted by the ARMv7 virtualization extensions and is RES0. 165 * 166 * For the SPSR layout seen from AArch32, see: 167 * - ARM DDI 0406C.d, page B1-1148 168 * - ARM DDI 0487E.a, page G8-6264 169 * 170 * For the SPSR_ELx layout for AArch32 seen from AArch64, see: 171 * - ARM DDI 0487E.a, page C5-426 172 * 173 * Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from 174 * MSB to LSB. 175 */ 176 static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode) 177 { 178 u32 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1); 179 unsigned long old, new; 180 181 old = *vcpu_cpsr(vcpu); 182 new = 0; 183 184 new |= (old & PSR_AA32_N_BIT); 185 new |= (old & PSR_AA32_Z_BIT); 186 new |= (old & PSR_AA32_C_BIT); 187 new |= (old & PSR_AA32_V_BIT); 188 new |= (old & PSR_AA32_Q_BIT); 189 190 // CPSR.IT[7:0] are set to zero upon any exception 191 // See ARM DDI 0487E.a, section G1.12.3 192 // See ARM DDI 0406C.d, section B1.8.3 193 194 new |= (old & PSR_AA32_DIT_BIT); 195 196 // CPSR.SSBS is set to SCTLR.DSSBS upon any exception 197 // See ARM DDI 0487E.a, page G8-6244 198 if (sctlr & BIT(31)) 199 new |= PSR_AA32_SSBS_BIT; 200 201 // CPSR.PAN is unchanged unless SCTLR.SPAN == 0b0 202 // SCTLR.SPAN is RES1 when ARMv8.1-PAN is not implemented 203 // See ARM DDI 0487E.a, page G8-6246 204 new |= (old & PSR_AA32_PAN_BIT); 205 if (!(sctlr & BIT(23))) 206 new |= PSR_AA32_PAN_BIT; 207 208 // SS does not exist in AArch32, so ignore 209 210 // CPSR.IL is set to zero upon any exception 211 // See ARM DDI 0487E.a, page G1-5527 212 213 new |= (old & PSR_AA32_GE_MASK); 214 215 // CPSR.IT[7:0] are set to zero upon any exception 216 // See prior comment above 217 218 // CPSR.E is set to SCTLR.EE upon any exception 219 // See ARM DDI 0487E.a, page G8-6245 220 // See ARM DDI 0406C.d, page B4-1701 221 if (sctlr & BIT(25)) 222 new |= PSR_AA32_E_BIT; 223 224 // CPSR.A is unchanged upon an exception to Undefined, Supervisor 225 // CPSR.A is set upon an exception to other modes 226 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 227 // See ARM DDI 0406C.d, page B1-1182 228 new |= (old & PSR_AA32_A_BIT); 229 if (mode != PSR_AA32_MODE_UND && mode != PSR_AA32_MODE_SVC) 230 new |= PSR_AA32_A_BIT; 231 232 // CPSR.I is set upon any exception 233 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 234 // See ARM DDI 0406C.d, page B1-1182 235 new |= PSR_AA32_I_BIT; 236 237 // CPSR.F is set upon an exception to FIQ 238 // CPSR.F is unchanged upon an exception to other modes 239 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 240 // See ARM DDI 0406C.d, page B1-1182 241 new |= (old & PSR_AA32_F_BIT); 242 if (mode == PSR_AA32_MODE_FIQ) 243 new |= PSR_AA32_F_BIT; 244 245 // CPSR.T is set to SCTLR.TE upon any exception 246 // See ARM DDI 0487E.a, page G8-5514 247 // See ARM DDI 0406C.d, page B1-1181 248 if (sctlr & BIT(30)) 249 new |= PSR_AA32_T_BIT; 250 251 new |= mode; 252 253 return new; 254 } 255 256 /* 257 * Table taken from ARMv8 ARM DDI0487B-B, table G1-10. 258 */ 259 static const u8 return_offsets[8][2] = { 260 [0] = { 0, 0 }, /* Reset, unused */ 261 [1] = { 4, 2 }, /* Undefined */ 262 [2] = { 0, 0 }, /* SVC, unused */ 263 [3] = { 4, 4 }, /* Prefetch abort */ 264 [4] = { 8, 8 }, /* Data abort */ 265 [5] = { 0, 0 }, /* HVC, unused */ 266 [6] = { 4, 4 }, /* IRQ, unused */ 267 [7] = { 4, 4 }, /* FIQ, unused */ 268 }; 269 270 static void enter_exception32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) 271 { 272 unsigned long spsr = *vcpu_cpsr(vcpu); 273 bool is_thumb = (spsr & PSR_AA32_T_BIT); 274 u32 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1); 275 u32 return_address; 276 277 *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode); 278 return_address = *vcpu_pc(vcpu); 279 return_address += return_offsets[vect_offset >> 2][is_thumb]; 280 281 /* KVM only enters the ABT and UND modes, so only deal with those */ 282 switch(mode) { 283 case PSR_AA32_MODE_ABT: 284 __vcpu_write_spsr_abt(vcpu, host_spsr_to_spsr32(spsr)); 285 vcpu_gp_regs(vcpu)->compat_lr_abt = return_address; 286 break; 287 288 case PSR_AA32_MODE_UND: 289 __vcpu_write_spsr_und(vcpu, host_spsr_to_spsr32(spsr)); 290 vcpu_gp_regs(vcpu)->compat_lr_und = return_address; 291 break; 292 } 293 294 /* Branch to exception vector */ 295 if (sctlr & (1 << 13)) 296 vect_offset += 0xffff0000; 297 else /* always have security exceptions */ 298 vect_offset += __vcpu_read_sys_reg(vcpu, VBAR_EL1); 299 300 *vcpu_pc(vcpu) = vect_offset; 301 } 302 303 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 304 { 305 if (vcpu_el1_is_32bit(vcpu)) { 306 switch (vcpu->arch.flags & KVM_ARM64_EXCEPT_MASK) { 307 case KVM_ARM64_EXCEPT_AA32_UND: 308 enter_exception32(vcpu, PSR_AA32_MODE_UND, 4); 309 break; 310 case KVM_ARM64_EXCEPT_AA32_IABT: 311 enter_exception32(vcpu, PSR_AA32_MODE_ABT, 12); 312 break; 313 case KVM_ARM64_EXCEPT_AA32_DABT: 314 enter_exception32(vcpu, PSR_AA32_MODE_ABT, 16); 315 break; 316 default: 317 /* Err... */ 318 break; 319 } 320 } else { 321 switch (vcpu->arch.flags & KVM_ARM64_EXCEPT_MASK) { 322 case (KVM_ARM64_EXCEPT_AA64_ELx_SYNC | 323 KVM_ARM64_EXCEPT_AA64_EL1): 324 enter_exception64(vcpu, PSR_MODE_EL1h, except_type_sync); 325 break; 326 default: 327 /* 328 * Only EL1_SYNC makes sense so far, EL2_{SYNC,IRQ} 329 * will be implemented at some point. Everything 330 * else gets silently ignored. 331 */ 332 break; 333 } 334 } 335 } 336 337 /* 338 * Adjust the guest PC (and potentially exception state) depending on 339 * flags provided by the emulation code. 340 */ 341 void __kvm_adjust_pc(struct kvm_vcpu *vcpu) 342 { 343 if (vcpu->arch.flags & KVM_ARM64_PENDING_EXCEPTION) { 344 kvm_inject_exception(vcpu); 345 vcpu->arch.flags &= ~(KVM_ARM64_PENDING_EXCEPTION | 346 KVM_ARM64_EXCEPT_MASK); 347 } else if (vcpu->arch.flags & KVM_ARM64_INCREMENT_PC) { 348 kvm_skip_instr(vcpu); 349 vcpu->arch.flags &= ~KVM_ARM64_INCREMENT_PC; 350 } 351 } 352