1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/traps.c 4 * 5 * Copyright (C) 1995-2009 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 9 #include <linux/bug.h> 10 #include <linux/context_tracking.h> 11 #include <linux/signal.h> 12 #include <linux/personality.h> 13 #include <linux/kallsyms.h> 14 #include <linux/kprobes.h> 15 #include <linux/spinlock.h> 16 #include <linux/uaccess.h> 17 #include <linux/hardirq.h> 18 #include <linux/kdebug.h> 19 #include <linux/module.h> 20 #include <linux/kexec.h> 21 #include <linux/delay.h> 22 #include <linux/init.h> 23 #include <linux/sched/signal.h> 24 #include <linux/sched/debug.h> 25 #include <linux/sched/task_stack.h> 26 #include <linux/sizes.h> 27 #include <linux/syscalls.h> 28 #include <linux/mm_types.h> 29 #include <linux/kasan.h> 30 31 #include <asm/atomic.h> 32 #include <asm/bug.h> 33 #include <asm/cpufeature.h> 34 #include <asm/daifflags.h> 35 #include <asm/debug-monitors.h> 36 #include <asm/esr.h> 37 #include <asm/insn.h> 38 #include <asm/kprobes.h> 39 #include <asm/traps.h> 40 #include <asm/smp.h> 41 #include <asm/stack_pointer.h> 42 #include <asm/stacktrace.h> 43 #include <asm/exception.h> 44 #include <asm/system_misc.h> 45 #include <asm/sysreg.h> 46 47 static const char *handler[]= { 48 "Synchronous Abort", 49 "IRQ", 50 "FIQ", 51 "Error" 52 }; 53 54 int show_unhandled_signals = 0; 55 56 static void dump_backtrace_entry(unsigned long where) 57 { 58 printk(" %pS\n", (void *)where); 59 } 60 61 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) 62 { 63 unsigned long addr = instruction_pointer(regs); 64 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 65 int i; 66 67 if (user_mode(regs)) 68 return; 69 70 for (i = -4; i < 1; i++) { 71 unsigned int val, bad; 72 73 bad = aarch64_insn_read(&((u32 *)addr)[i], &val); 74 75 if (!bad) 76 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); 77 else { 78 p += sprintf(p, "bad PC value"); 79 break; 80 } 81 } 82 83 printk("%sCode: %s\n", lvl, str); 84 } 85 86 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) 87 { 88 struct stackframe frame; 89 int skip = 0; 90 91 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); 92 93 if (regs) { 94 if (user_mode(regs)) 95 return; 96 skip = 1; 97 } 98 99 if (!tsk) 100 tsk = current; 101 102 if (!try_get_task_stack(tsk)) 103 return; 104 105 if (tsk == current) { 106 start_backtrace(&frame, 107 (unsigned long)__builtin_frame_address(0), 108 (unsigned long)dump_backtrace); 109 } else { 110 /* 111 * task blocked in __switch_to 112 */ 113 start_backtrace(&frame, 114 thread_saved_fp(tsk), 115 thread_saved_pc(tsk)); 116 } 117 118 printk("Call trace:\n"); 119 do { 120 /* skip until specified stack frame */ 121 if (!skip) { 122 dump_backtrace_entry(frame.pc); 123 } else if (frame.fp == regs->regs[29]) { 124 skip = 0; 125 /* 126 * Mostly, this is the case where this function is 127 * called in panic/abort. As exception handler's 128 * stack frame does not contain the corresponding pc 129 * at which an exception has taken place, use regs->pc 130 * instead. 131 */ 132 dump_backtrace_entry(regs->pc); 133 } 134 } while (!unwind_frame(tsk, &frame)); 135 136 put_task_stack(tsk); 137 } 138 139 void show_stack(struct task_struct *tsk, unsigned long *sp) 140 { 141 dump_backtrace(NULL, tsk); 142 barrier(); 143 } 144 145 #ifdef CONFIG_PREEMPT 146 #define S_PREEMPT " PREEMPT" 147 #elif defined(CONFIG_PREEMPT_RT) 148 #define S_PREEMPT " PREEMPT_RT" 149 #else 150 #define S_PREEMPT "" 151 #endif 152 153 #define S_SMP " SMP" 154 155 static int __die(const char *str, int err, struct pt_regs *regs) 156 { 157 static int die_counter; 158 int ret; 159 160 pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", 161 str, err, ++die_counter); 162 163 /* trap and error numbers are mostly meaningless on ARM */ 164 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); 165 if (ret == NOTIFY_STOP) 166 return ret; 167 168 print_modules(); 169 show_regs(regs); 170 171 dump_kernel_instr(KERN_EMERG, regs); 172 173 return ret; 174 } 175 176 static DEFINE_RAW_SPINLOCK(die_lock); 177 178 /* 179 * This function is protected against re-entrancy. 180 */ 181 void die(const char *str, struct pt_regs *regs, int err) 182 { 183 int ret; 184 unsigned long flags; 185 186 raw_spin_lock_irqsave(&die_lock, flags); 187 188 oops_enter(); 189 190 console_verbose(); 191 bust_spinlocks(1); 192 ret = __die(str, err, regs); 193 194 if (regs && kexec_should_crash(current)) 195 crash_kexec(regs); 196 197 bust_spinlocks(0); 198 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 199 oops_exit(); 200 201 if (in_interrupt()) 202 panic("Fatal exception in interrupt"); 203 if (panic_on_oops) 204 panic("Fatal exception"); 205 206 raw_spin_unlock_irqrestore(&die_lock, flags); 207 208 if (ret != NOTIFY_STOP) 209 do_exit(SIGSEGV); 210 } 211 212 static void arm64_show_signal(int signo, const char *str) 213 { 214 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 215 DEFAULT_RATELIMIT_BURST); 216 struct task_struct *tsk = current; 217 unsigned int esr = tsk->thread.fault_code; 218 struct pt_regs *regs = task_pt_regs(tsk); 219 220 /* Leave if the signal won't be shown */ 221 if (!show_unhandled_signals || 222 !unhandled_signal(tsk, signo) || 223 !__ratelimit(&rs)) 224 return; 225 226 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); 227 if (esr) 228 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr); 229 230 pr_cont("%s", str); 231 print_vma_addr(KERN_CONT " in ", regs->pc); 232 pr_cont("\n"); 233 __show_regs(regs); 234 } 235 236 void arm64_force_sig_fault(int signo, int code, void __user *addr, 237 const char *str) 238 { 239 arm64_show_signal(signo, str); 240 if (signo == SIGKILL) 241 force_sig(SIGKILL); 242 else 243 force_sig_fault(signo, code, addr); 244 } 245 246 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb, 247 const char *str) 248 { 249 arm64_show_signal(SIGBUS, str); 250 force_sig_mceerr(code, addr, lsb); 251 } 252 253 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr, 254 const char *str) 255 { 256 arm64_show_signal(SIGTRAP, str); 257 force_sig_ptrace_errno_trap(errno, addr); 258 } 259 260 void arm64_notify_die(const char *str, struct pt_regs *regs, 261 int signo, int sicode, void __user *addr, 262 int err) 263 { 264 if (user_mode(regs)) { 265 WARN_ON(regs != current_pt_regs()); 266 current->thread.fault_address = 0; 267 current->thread.fault_code = err; 268 269 arm64_force_sig_fault(signo, sicode, addr, str); 270 } else { 271 die(str, regs, err); 272 } 273 } 274 275 #ifdef CONFIG_COMPAT 276 #define PSTATE_IT_1_0_SHIFT 25 277 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) 278 #define PSTATE_IT_7_2_SHIFT 10 279 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) 280 281 static u32 compat_get_it_state(struct pt_regs *regs) 282 { 283 u32 it, pstate = regs->pstate; 284 285 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; 286 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; 287 288 return it; 289 } 290 291 static void compat_set_it_state(struct pt_regs *regs, u32 it) 292 { 293 u32 pstate_it; 294 295 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; 296 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; 297 298 regs->pstate &= ~PSR_AA32_IT_MASK; 299 regs->pstate |= pstate_it; 300 } 301 302 static void advance_itstate(struct pt_regs *regs) 303 { 304 u32 it; 305 306 /* ARM mode */ 307 if (!(regs->pstate & PSR_AA32_T_BIT) || 308 !(regs->pstate & PSR_AA32_IT_MASK)) 309 return; 310 311 it = compat_get_it_state(regs); 312 313 /* 314 * If this is the last instruction of the block, wipe the IT 315 * state. Otherwise advance it. 316 */ 317 if (!(it & 7)) 318 it = 0; 319 else 320 it = (it & 0xe0) | ((it << 1) & 0x1f); 321 322 compat_set_it_state(regs, it); 323 } 324 #else 325 static void advance_itstate(struct pt_regs *regs) 326 { 327 } 328 #endif 329 330 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) 331 { 332 regs->pc += size; 333 334 /* 335 * If we were single stepping, we want to get the step exception after 336 * we return from the trap. 337 */ 338 if (user_mode(regs)) 339 user_fastforward_single_step(current); 340 341 if (compat_user_mode(regs)) 342 advance_itstate(regs); 343 else 344 regs->pstate &= ~PSR_BTYPE_MASK; 345 } 346 347 static LIST_HEAD(undef_hook); 348 static DEFINE_RAW_SPINLOCK(undef_lock); 349 350 void register_undef_hook(struct undef_hook *hook) 351 { 352 unsigned long flags; 353 354 raw_spin_lock_irqsave(&undef_lock, flags); 355 list_add(&hook->node, &undef_hook); 356 raw_spin_unlock_irqrestore(&undef_lock, flags); 357 } 358 359 void unregister_undef_hook(struct undef_hook *hook) 360 { 361 unsigned long flags; 362 363 raw_spin_lock_irqsave(&undef_lock, flags); 364 list_del(&hook->node); 365 raw_spin_unlock_irqrestore(&undef_lock, flags); 366 } 367 368 static int call_undef_hook(struct pt_regs *regs) 369 { 370 struct undef_hook *hook; 371 unsigned long flags; 372 u32 instr; 373 int (*fn)(struct pt_regs *regs, u32 instr) = NULL; 374 void __user *pc = (void __user *)instruction_pointer(regs); 375 376 if (!user_mode(regs)) { 377 __le32 instr_le; 378 if (probe_kernel_address((__force __le32 *)pc, instr_le)) 379 goto exit; 380 instr = le32_to_cpu(instr_le); 381 } else if (compat_thumb_mode(regs)) { 382 /* 16-bit Thumb instruction */ 383 __le16 instr_le; 384 if (get_user(instr_le, (__le16 __user *)pc)) 385 goto exit; 386 instr = le16_to_cpu(instr_le); 387 if (aarch32_insn_is_wide(instr)) { 388 u32 instr2; 389 390 if (get_user(instr_le, (__le16 __user *)(pc + 2))) 391 goto exit; 392 instr2 = le16_to_cpu(instr_le); 393 instr = (instr << 16) | instr2; 394 } 395 } else { 396 /* 32-bit ARM instruction */ 397 __le32 instr_le; 398 if (get_user(instr_le, (__le32 __user *)pc)) 399 goto exit; 400 instr = le32_to_cpu(instr_le); 401 } 402 403 raw_spin_lock_irqsave(&undef_lock, flags); 404 list_for_each_entry(hook, &undef_hook, node) 405 if ((instr & hook->instr_mask) == hook->instr_val && 406 (regs->pstate & hook->pstate_mask) == hook->pstate_val) 407 fn = hook->fn; 408 409 raw_spin_unlock_irqrestore(&undef_lock, flags); 410 exit: 411 return fn ? fn(regs, instr) : 1; 412 } 413 414 void force_signal_inject(int signal, int code, unsigned long address) 415 { 416 const char *desc; 417 struct pt_regs *regs = current_pt_regs(); 418 419 if (WARN_ON(!user_mode(regs))) 420 return; 421 422 switch (signal) { 423 case SIGILL: 424 desc = "undefined instruction"; 425 break; 426 case SIGSEGV: 427 desc = "illegal memory access"; 428 break; 429 default: 430 desc = "unknown or unrecoverable error"; 431 break; 432 } 433 434 /* Force signals we don't understand to SIGKILL */ 435 if (WARN_ON(signal != SIGKILL && 436 siginfo_layout(signal, code) != SIL_FAULT)) { 437 signal = SIGKILL; 438 } 439 440 arm64_notify_die(desc, regs, signal, code, (void __user *)address, 0); 441 } 442 443 /* 444 * Set up process info to signal segmentation fault - called on access error. 445 */ 446 void arm64_notify_segfault(unsigned long addr) 447 { 448 int code; 449 450 down_read(¤t->mm->mmap_sem); 451 if (find_vma(current->mm, addr) == NULL) 452 code = SEGV_MAPERR; 453 else 454 code = SEGV_ACCERR; 455 up_read(¤t->mm->mmap_sem); 456 457 force_signal_inject(SIGSEGV, code, addr); 458 } 459 460 void do_undefinstr(struct pt_regs *regs) 461 { 462 /* check for AArch32 breakpoint instructions */ 463 if (!aarch32_break_handler(regs)) 464 return; 465 466 if (call_undef_hook(regs) == 0) 467 return; 468 469 BUG_ON(!user_mode(regs)); 470 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 471 } 472 NOKPROBE_SYMBOL(do_undefinstr); 473 474 void do_bti(struct pt_regs *regs) 475 { 476 BUG_ON(!user_mode(regs)); 477 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 478 } 479 NOKPROBE_SYMBOL(do_bti); 480 481 #define __user_cache_maint(insn, address, res) \ 482 if (address >= user_addr_max()) { \ 483 res = -EFAULT; \ 484 } else { \ 485 uaccess_ttbr0_enable(); \ 486 asm volatile ( \ 487 "1: " insn ", %1\n" \ 488 " mov %w0, #0\n" \ 489 "2:\n" \ 490 " .pushsection .fixup,\"ax\"\n" \ 491 " .align 2\n" \ 492 "3: mov %w0, %w2\n" \ 493 " b 2b\n" \ 494 " .popsection\n" \ 495 _ASM_EXTABLE(1b, 3b) \ 496 : "=r" (res) \ 497 : "r" (address), "i" (-EFAULT)); \ 498 uaccess_ttbr0_disable(); \ 499 } 500 501 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) 502 { 503 unsigned long address; 504 int rt = ESR_ELx_SYS64_ISS_RT(esr); 505 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 506 int ret = 0; 507 508 address = untagged_addr(pt_regs_read_reg(regs, rt)); 509 510 switch (crm) { 511 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ 512 __user_cache_maint("dc civac", address, ret); 513 break; 514 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ 515 __user_cache_maint("dc civac", address, ret); 516 break; 517 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ 518 __user_cache_maint("sys 3, c7, c13, 1", address, ret); 519 break; 520 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ 521 __user_cache_maint("sys 3, c7, c12, 1", address, ret); 522 break; 523 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ 524 __user_cache_maint("dc civac", address, ret); 525 break; 526 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ 527 __user_cache_maint("ic ivau", address, ret); 528 break; 529 default: 530 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 531 return; 532 } 533 534 if (ret) 535 arm64_notify_segfault(address); 536 else 537 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 538 } 539 540 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) 541 { 542 int rt = ESR_ELx_SYS64_ISS_RT(esr); 543 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); 544 545 if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { 546 /* Hide DIC so that we can trap the unnecessary maintenance...*/ 547 val &= ~BIT(CTR_DIC_SHIFT); 548 549 /* ... and fake IminLine to reduce the number of traps. */ 550 val &= ~CTR_IMINLINE_MASK; 551 val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK; 552 } 553 554 pt_regs_write_reg(regs, rt, val); 555 556 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 557 } 558 559 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 560 { 561 int rt = ESR_ELx_SYS64_ISS_RT(esr); 562 563 pt_regs_write_reg(regs, rt, arch_timer_read_counter()); 564 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 565 } 566 567 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 568 { 569 int rt = ESR_ELx_SYS64_ISS_RT(esr); 570 571 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); 572 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 573 } 574 575 static void mrs_handler(unsigned int esr, struct pt_regs *regs) 576 { 577 u32 sysreg, rt; 578 579 rt = ESR_ELx_SYS64_ISS_RT(esr); 580 sysreg = esr_sys64_to_sysreg(esr); 581 582 if (do_emulate_mrs(regs, sysreg, rt) != 0) 583 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 584 } 585 586 static void wfi_handler(unsigned int esr, struct pt_regs *regs) 587 { 588 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 589 } 590 591 struct sys64_hook { 592 unsigned int esr_mask; 593 unsigned int esr_val; 594 void (*handler)(unsigned int esr, struct pt_regs *regs); 595 }; 596 597 static const struct sys64_hook sys64_hooks[] = { 598 { 599 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, 600 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, 601 .handler = user_cache_maint_handler, 602 }, 603 { 604 /* Trap read access to CTR_EL0 */ 605 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 606 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, 607 .handler = ctr_read_handler, 608 }, 609 { 610 /* Trap read access to CNTVCT_EL0 */ 611 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 612 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, 613 .handler = cntvct_read_handler, 614 }, 615 { 616 /* Trap read access to CNTFRQ_EL0 */ 617 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 618 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, 619 .handler = cntfrq_read_handler, 620 }, 621 { 622 /* Trap read access to CPUID registers */ 623 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, 624 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, 625 .handler = mrs_handler, 626 }, 627 { 628 /* Trap WFI instructions executed in userspace */ 629 .esr_mask = ESR_ELx_WFx_MASK, 630 .esr_val = ESR_ELx_WFx_WFI_VAL, 631 .handler = wfi_handler, 632 }, 633 {}, 634 }; 635 636 #ifdef CONFIG_COMPAT 637 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs) 638 { 639 int cond; 640 641 /* Only a T32 instruction can trap without CV being set */ 642 if (!(esr & ESR_ELx_CV)) { 643 u32 it; 644 645 it = compat_get_it_state(regs); 646 if (!it) 647 return true; 648 649 cond = it >> 4; 650 } else { 651 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 652 } 653 654 return aarch32_opcode_cond_checks[cond](regs->pstate); 655 } 656 657 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 658 { 659 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; 660 661 pt_regs_write_reg(regs, reg, arch_timer_get_rate()); 662 arm64_skip_faulting_instruction(regs, 4); 663 } 664 665 static const struct sys64_hook cp15_32_hooks[] = { 666 { 667 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, 668 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, 669 .handler = compat_cntfrq_read_handler, 670 }, 671 {}, 672 }; 673 674 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 675 { 676 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; 677 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; 678 u64 val = arch_timer_read_counter(); 679 680 pt_regs_write_reg(regs, rt, lower_32_bits(val)); 681 pt_regs_write_reg(regs, rt2, upper_32_bits(val)); 682 arm64_skip_faulting_instruction(regs, 4); 683 } 684 685 static const struct sys64_hook cp15_64_hooks[] = { 686 { 687 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 688 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, 689 .handler = compat_cntvct_read_handler, 690 }, 691 {}, 692 }; 693 694 void do_cp15instr(unsigned int esr, struct pt_regs *regs) 695 { 696 const struct sys64_hook *hook, *hook_base; 697 698 if (!cp15_cond_valid(esr, regs)) { 699 /* 700 * There is no T16 variant of a CP access, so we 701 * always advance PC by 4 bytes. 702 */ 703 arm64_skip_faulting_instruction(regs, 4); 704 return; 705 } 706 707 switch (ESR_ELx_EC(esr)) { 708 case ESR_ELx_EC_CP15_32: 709 hook_base = cp15_32_hooks; 710 break; 711 case ESR_ELx_EC_CP15_64: 712 hook_base = cp15_64_hooks; 713 break; 714 default: 715 do_undefinstr(regs); 716 return; 717 } 718 719 for (hook = hook_base; hook->handler; hook++) 720 if ((hook->esr_mask & esr) == hook->esr_val) { 721 hook->handler(esr, regs); 722 return; 723 } 724 725 /* 726 * New cp15 instructions may previously have been undefined at 727 * EL0. Fall back to our usual undefined instruction handler 728 * so that we handle these consistently. 729 */ 730 do_undefinstr(regs); 731 } 732 NOKPROBE_SYMBOL(do_cp15instr); 733 #endif 734 735 void do_sysinstr(unsigned int esr, struct pt_regs *regs) 736 { 737 const struct sys64_hook *hook; 738 739 for (hook = sys64_hooks; hook->handler; hook++) 740 if ((hook->esr_mask & esr) == hook->esr_val) { 741 hook->handler(esr, regs); 742 return; 743 } 744 745 /* 746 * New SYS instructions may previously have been undefined at EL0. Fall 747 * back to our usual undefined instruction handler so that we handle 748 * these consistently. 749 */ 750 do_undefinstr(regs); 751 } 752 NOKPROBE_SYMBOL(do_sysinstr); 753 754 static const char *esr_class_str[] = { 755 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", 756 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", 757 [ESR_ELx_EC_WFx] = "WFI/WFE", 758 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", 759 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", 760 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", 761 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", 762 [ESR_ELx_EC_FP_ASIMD] = "ASIMD", 763 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", 764 [ESR_ELx_EC_PAC] = "PAC", 765 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", 766 [ESR_ELx_EC_BTI] = "BTI", 767 [ESR_ELx_EC_ILL] = "PSTATE.IL", 768 [ESR_ELx_EC_SVC32] = "SVC (AArch32)", 769 [ESR_ELx_EC_HVC32] = "HVC (AArch32)", 770 [ESR_ELx_EC_SMC32] = "SMC (AArch32)", 771 [ESR_ELx_EC_SVC64] = "SVC (AArch64)", 772 [ESR_ELx_EC_HVC64] = "HVC (AArch64)", 773 [ESR_ELx_EC_SMC64] = "SMC (AArch64)", 774 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", 775 [ESR_ELx_EC_SVE] = "SVE", 776 [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", 777 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", 778 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", 779 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", 780 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment", 781 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", 782 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", 783 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment", 784 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", 785 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", 786 [ESR_ELx_EC_SERROR] = "SError", 787 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", 788 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", 789 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", 790 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", 791 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", 792 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", 793 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", 794 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", 795 [ESR_ELx_EC_BRK64] = "BRK (AArch64)", 796 }; 797 798 const char *esr_get_class_string(u32 esr) 799 { 800 return esr_class_str[ESR_ELx_EC(esr)]; 801 } 802 803 /* 804 * bad_mode handles the impossible case in the exception vector. This is always 805 * fatal. 806 */ 807 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr) 808 { 809 console_verbose(); 810 811 pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n", 812 handler[reason], smp_processor_id(), esr, 813 esr_get_class_string(esr)); 814 815 local_daif_mask(); 816 panic("bad mode"); 817 } 818 819 /* 820 * bad_el0_sync handles unexpected, but potentially recoverable synchronous 821 * exceptions taken from EL0. Unlike bad_mode, this returns. 822 */ 823 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr) 824 { 825 void __user *pc = (void __user *)instruction_pointer(regs); 826 827 current->thread.fault_address = 0; 828 current->thread.fault_code = esr; 829 830 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, 831 "Bad EL0 synchronous exception"); 832 } 833 834 #ifdef CONFIG_VMAP_STACK 835 836 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) 837 __aligned(16); 838 839 asmlinkage void handle_bad_stack(struct pt_regs *regs) 840 { 841 unsigned long tsk_stk = (unsigned long)current->stack; 842 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); 843 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); 844 unsigned int esr = read_sysreg(esr_el1); 845 unsigned long far = read_sysreg(far_el1); 846 847 console_verbose(); 848 pr_emerg("Insufficient stack space to handle exception!"); 849 850 pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr)); 851 pr_emerg("FAR: 0x%016lx\n", far); 852 853 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", 854 tsk_stk, tsk_stk + THREAD_SIZE); 855 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", 856 irq_stk, irq_stk + THREAD_SIZE); 857 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", 858 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); 859 860 __show_regs(regs); 861 862 /* 863 * We use nmi_panic to limit the potential for recusive overflows, and 864 * to get a better stack trace. 865 */ 866 nmi_panic(NULL, "kernel stack overflow"); 867 cpu_park_loop(); 868 } 869 #endif 870 871 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr) 872 { 873 console_verbose(); 874 875 pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n", 876 smp_processor_id(), esr, esr_get_class_string(esr)); 877 if (regs) 878 __show_regs(regs); 879 880 nmi_panic(regs, "Asynchronous SError Interrupt"); 881 882 cpu_park_loop(); 883 unreachable(); 884 } 885 886 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr) 887 { 888 u32 aet = arm64_ras_serror_get_severity(esr); 889 890 switch (aet) { 891 case ESR_ELx_AET_CE: /* corrected error */ 892 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ 893 /* 894 * The CPU can make progress. We may take UEO again as 895 * a more severe error. 896 */ 897 return false; 898 899 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ 900 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ 901 /* 902 * The CPU can't make progress. The exception may have 903 * been imprecise. 904 * 905 * Neoverse-N1 #1349291 means a non-KVM SError reported as 906 * Unrecoverable should be treated as Uncontainable. We 907 * call arm64_serror_panic() in both cases. 908 */ 909 return true; 910 911 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ 912 default: 913 /* Error has been silently propagated */ 914 arm64_serror_panic(regs, esr); 915 } 916 } 917 918 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr) 919 { 920 nmi_enter(); 921 922 /* non-RAS errors are not containable */ 923 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) 924 arm64_serror_panic(regs, esr); 925 926 nmi_exit(); 927 } 928 929 asmlinkage void enter_from_user_mode(void) 930 { 931 CT_WARN_ON(ct_state() != CONTEXT_USER); 932 user_exit_irqoff(); 933 } 934 NOKPROBE_SYMBOL(enter_from_user_mode); 935 936 void __pte_error(const char *file, int line, unsigned long val) 937 { 938 pr_err("%s:%d: bad pte %016lx.\n", file, line, val); 939 } 940 941 void __pmd_error(const char *file, int line, unsigned long val) 942 { 943 pr_err("%s:%d: bad pmd %016lx.\n", file, line, val); 944 } 945 946 void __pud_error(const char *file, int line, unsigned long val) 947 { 948 pr_err("%s:%d: bad pud %016lx.\n", file, line, val); 949 } 950 951 void __pgd_error(const char *file, int line, unsigned long val) 952 { 953 pr_err("%s:%d: bad pgd %016lx.\n", file, line, val); 954 } 955 956 /* GENERIC_BUG traps */ 957 958 int is_valid_bugaddr(unsigned long addr) 959 { 960 /* 961 * bug_handler() only called for BRK #BUG_BRK_IMM. 962 * So the answer is trivial -- any spurious instances with no 963 * bug table entry will be rejected by report_bug() and passed 964 * back to the debug-monitors code and handled as a fatal 965 * unexpected debug exception. 966 */ 967 return 1; 968 } 969 970 static int bug_handler(struct pt_regs *regs, unsigned int esr) 971 { 972 switch (report_bug(regs->pc, regs)) { 973 case BUG_TRAP_TYPE_BUG: 974 die("Oops - BUG", regs, 0); 975 break; 976 977 case BUG_TRAP_TYPE_WARN: 978 break; 979 980 default: 981 /* unknown/unrecognised bug trap type */ 982 return DBG_HOOK_ERROR; 983 } 984 985 /* If thread survives, skip over the BUG instruction and continue: */ 986 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 987 return DBG_HOOK_HANDLED; 988 } 989 990 static struct break_hook bug_break_hook = { 991 .fn = bug_handler, 992 .imm = BUG_BRK_IMM, 993 }; 994 995 #ifdef CONFIG_KASAN_SW_TAGS 996 997 #define KASAN_ESR_RECOVER 0x20 998 #define KASAN_ESR_WRITE 0x10 999 #define KASAN_ESR_SIZE_MASK 0x0f 1000 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) 1001 1002 static int kasan_handler(struct pt_regs *regs, unsigned int esr) 1003 { 1004 bool recover = esr & KASAN_ESR_RECOVER; 1005 bool write = esr & KASAN_ESR_WRITE; 1006 size_t size = KASAN_ESR_SIZE(esr); 1007 u64 addr = regs->regs[0]; 1008 u64 pc = regs->pc; 1009 1010 kasan_report(addr, size, write, pc); 1011 1012 /* 1013 * The instrumentation allows to control whether we can proceed after 1014 * a crash was detected. This is done by passing the -recover flag to 1015 * the compiler. Disabling recovery allows to generate more compact 1016 * code. 1017 * 1018 * Unfortunately disabling recovery doesn't work for the kernel right 1019 * now. KASAN reporting is disabled in some contexts (for example when 1020 * the allocator accesses slab object metadata; this is controlled by 1021 * current->kasan_depth). All these accesses are detected by the tool, 1022 * even though the reports for them are not printed. 1023 * 1024 * This is something that might be fixed at some point in the future. 1025 */ 1026 if (!recover) 1027 die("Oops - KASAN", regs, 0); 1028 1029 /* If thread survives, skip over the brk instruction and continue: */ 1030 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1031 return DBG_HOOK_HANDLED; 1032 } 1033 1034 static struct break_hook kasan_break_hook = { 1035 .fn = kasan_handler, 1036 .imm = KASAN_BRK_IMM, 1037 .mask = KASAN_BRK_MASK, 1038 }; 1039 #endif 1040 1041 /* 1042 * Initial handler for AArch64 BRK exceptions 1043 * This handler only used until debug_traps_init(). 1044 */ 1045 int __init early_brk64(unsigned long addr, unsigned int esr, 1046 struct pt_regs *regs) 1047 { 1048 #ifdef CONFIG_KASAN_SW_TAGS 1049 unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; 1050 1051 if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM) 1052 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; 1053 #endif 1054 return bug_handler(regs, esr) != DBG_HOOK_HANDLED; 1055 } 1056 1057 void __init trap_init(void) 1058 { 1059 register_kernel_break_hook(&bug_break_hook); 1060 #ifdef CONFIG_KASAN_SW_TAGS 1061 register_kernel_break_hook(&kasan_break_hook); 1062 #endif 1063 debug_traps_init(); 1064 } 1065