1 /* 2 * Based on arch/arm/kernel/traps.c 3 * 4 * Copyright (C) 1995-2009 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/bug.h> 21 #include <linux/signal.h> 22 #include <linux/personality.h> 23 #include <linux/kallsyms.h> 24 #include <linux/spinlock.h> 25 #include <linux/uaccess.h> 26 #include <linux/hardirq.h> 27 #include <linux/kdebug.h> 28 #include <linux/module.h> 29 #include <linux/kexec.h> 30 #include <linux/delay.h> 31 #include <linux/init.h> 32 #include <linux/sched/signal.h> 33 #include <linux/sched/debug.h> 34 #include <linux/sched/task_stack.h> 35 #include <linux/sizes.h> 36 #include <linux/syscalls.h> 37 #include <linux/mm_types.h> 38 #include <linux/kasan.h> 39 40 #include <asm/atomic.h> 41 #include <asm/bug.h> 42 #include <asm/cpufeature.h> 43 #include <asm/daifflags.h> 44 #include <asm/debug-monitors.h> 45 #include <asm/esr.h> 46 #include <asm/insn.h> 47 #include <asm/traps.h> 48 #include <asm/smp.h> 49 #include <asm/stack_pointer.h> 50 #include <asm/stacktrace.h> 51 #include <asm/exception.h> 52 #include <asm/system_misc.h> 53 #include <asm/sysreg.h> 54 55 static const char *handler[]= { 56 "Synchronous Abort", 57 "IRQ", 58 "FIQ", 59 "Error" 60 }; 61 62 int show_unhandled_signals = 0; 63 64 static void dump_backtrace_entry(unsigned long where) 65 { 66 printk(" %pS\n", (void *)where); 67 } 68 69 static void __dump_instr(const char *lvl, struct pt_regs *regs) 70 { 71 unsigned long addr = instruction_pointer(regs); 72 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 73 int i; 74 75 for (i = -4; i < 1; i++) { 76 unsigned int val, bad; 77 78 bad = get_user(val, &((u32 *)addr)[i]); 79 80 if (!bad) 81 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); 82 else { 83 p += sprintf(p, "bad PC value"); 84 break; 85 } 86 } 87 printk("%sCode: %s\n", lvl, str); 88 } 89 90 static void dump_instr(const char *lvl, struct pt_regs *regs) 91 { 92 if (!user_mode(regs)) { 93 mm_segment_t fs = get_fs(); 94 set_fs(KERNEL_DS); 95 __dump_instr(lvl, regs); 96 set_fs(fs); 97 } else { 98 __dump_instr(lvl, regs); 99 } 100 } 101 102 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) 103 { 104 struct stackframe frame; 105 int skip; 106 107 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); 108 109 if (!tsk) 110 tsk = current; 111 112 if (!try_get_task_stack(tsk)) 113 return; 114 115 if (tsk == current) { 116 frame.fp = (unsigned long)__builtin_frame_address(0); 117 frame.pc = (unsigned long)dump_backtrace; 118 } else { 119 /* 120 * task blocked in __switch_to 121 */ 122 frame.fp = thread_saved_fp(tsk); 123 frame.pc = thread_saved_pc(tsk); 124 } 125 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 126 frame.graph = 0; 127 #endif 128 129 skip = !!regs; 130 printk("Call trace:\n"); 131 do { 132 /* skip until specified stack frame */ 133 if (!skip) { 134 dump_backtrace_entry(frame.pc); 135 } else if (frame.fp == regs->regs[29]) { 136 skip = 0; 137 /* 138 * Mostly, this is the case where this function is 139 * called in panic/abort. As exception handler's 140 * stack frame does not contain the corresponding pc 141 * at which an exception has taken place, use regs->pc 142 * instead. 143 */ 144 dump_backtrace_entry(regs->pc); 145 } 146 } while (!unwind_frame(tsk, &frame)); 147 148 put_task_stack(tsk); 149 } 150 151 void show_stack(struct task_struct *tsk, unsigned long *sp) 152 { 153 dump_backtrace(NULL, tsk); 154 barrier(); 155 } 156 157 #ifdef CONFIG_PREEMPT 158 #define S_PREEMPT " PREEMPT" 159 #else 160 #define S_PREEMPT "" 161 #endif 162 #define S_SMP " SMP" 163 164 static int __die(const char *str, int err, struct pt_regs *regs) 165 { 166 struct task_struct *tsk = current; 167 static int die_counter; 168 int ret; 169 170 pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", 171 str, err, ++die_counter); 172 173 /* trap and error numbers are mostly meaningless on ARM */ 174 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); 175 if (ret == NOTIFY_STOP) 176 return ret; 177 178 print_modules(); 179 __show_regs(regs); 180 pr_emerg("Process %.*s (pid: %d, stack limit = 0x%p)\n", 181 TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), 182 end_of_stack(tsk)); 183 184 if (!user_mode(regs)) { 185 dump_backtrace(regs, tsk); 186 dump_instr(KERN_EMERG, regs); 187 } 188 189 return ret; 190 } 191 192 static DEFINE_RAW_SPINLOCK(die_lock); 193 194 /* 195 * This function is protected against re-entrancy. 196 */ 197 void die(const char *str, struct pt_regs *regs, int err) 198 { 199 int ret; 200 unsigned long flags; 201 202 raw_spin_lock_irqsave(&die_lock, flags); 203 204 oops_enter(); 205 206 console_verbose(); 207 bust_spinlocks(1); 208 ret = __die(str, err, regs); 209 210 if (regs && kexec_should_crash(current)) 211 crash_kexec(regs); 212 213 bust_spinlocks(0); 214 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 215 oops_exit(); 216 217 if (in_interrupt()) 218 panic("Fatal exception in interrupt"); 219 if (panic_on_oops) 220 panic("Fatal exception"); 221 222 raw_spin_unlock_irqrestore(&die_lock, flags); 223 224 if (ret != NOTIFY_STOP) 225 do_exit(SIGSEGV); 226 } 227 228 static void arm64_show_signal(int signo, const char *str) 229 { 230 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 231 DEFAULT_RATELIMIT_BURST); 232 struct task_struct *tsk = current; 233 unsigned int esr = tsk->thread.fault_code; 234 struct pt_regs *regs = task_pt_regs(tsk); 235 236 /* Leave if the signal won't be shown */ 237 if (!show_unhandled_signals || 238 !unhandled_signal(tsk, signo) || 239 !__ratelimit(&rs)) 240 return; 241 242 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); 243 if (esr) 244 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr); 245 246 pr_cont("%s", str); 247 print_vma_addr(KERN_CONT " in ", regs->pc); 248 pr_cont("\n"); 249 __show_regs(regs); 250 } 251 252 void arm64_force_sig_fault(int signo, int code, void __user *addr, 253 const char *str) 254 { 255 arm64_show_signal(signo, str); 256 force_sig_fault(signo, code, addr, current); 257 } 258 259 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb, 260 const char *str) 261 { 262 arm64_show_signal(SIGBUS, str); 263 force_sig_mceerr(code, addr, lsb, current); 264 } 265 266 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr, 267 const char *str) 268 { 269 arm64_show_signal(SIGTRAP, str); 270 force_sig_ptrace_errno_trap(errno, addr); 271 } 272 273 void arm64_notify_die(const char *str, struct pt_regs *regs, 274 int signo, int sicode, void __user *addr, 275 int err) 276 { 277 if (user_mode(regs)) { 278 WARN_ON(regs != current_pt_regs()); 279 current->thread.fault_address = 0; 280 current->thread.fault_code = err; 281 282 arm64_force_sig_fault(signo, sicode, addr, str); 283 } else { 284 die(str, regs, err); 285 } 286 } 287 288 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) 289 { 290 regs->pc += size; 291 292 /* 293 * If we were single stepping, we want to get the step exception after 294 * we return from the trap. 295 */ 296 if (user_mode(regs)) 297 user_fastforward_single_step(current); 298 } 299 300 static LIST_HEAD(undef_hook); 301 static DEFINE_RAW_SPINLOCK(undef_lock); 302 303 void register_undef_hook(struct undef_hook *hook) 304 { 305 unsigned long flags; 306 307 raw_spin_lock_irqsave(&undef_lock, flags); 308 list_add(&hook->node, &undef_hook); 309 raw_spin_unlock_irqrestore(&undef_lock, flags); 310 } 311 312 void unregister_undef_hook(struct undef_hook *hook) 313 { 314 unsigned long flags; 315 316 raw_spin_lock_irqsave(&undef_lock, flags); 317 list_del(&hook->node); 318 raw_spin_unlock_irqrestore(&undef_lock, flags); 319 } 320 321 static int call_undef_hook(struct pt_regs *regs) 322 { 323 struct undef_hook *hook; 324 unsigned long flags; 325 u32 instr; 326 int (*fn)(struct pt_regs *regs, u32 instr) = NULL; 327 void __user *pc = (void __user *)instruction_pointer(regs); 328 329 if (!user_mode(regs)) { 330 __le32 instr_le; 331 if (probe_kernel_address((__force __le32 *)pc, instr_le)) 332 goto exit; 333 instr = le32_to_cpu(instr_le); 334 } else if (compat_thumb_mode(regs)) { 335 /* 16-bit Thumb instruction */ 336 __le16 instr_le; 337 if (get_user(instr_le, (__le16 __user *)pc)) 338 goto exit; 339 instr = le16_to_cpu(instr_le); 340 if (aarch32_insn_is_wide(instr)) { 341 u32 instr2; 342 343 if (get_user(instr_le, (__le16 __user *)(pc + 2))) 344 goto exit; 345 instr2 = le16_to_cpu(instr_le); 346 instr = (instr << 16) | instr2; 347 } 348 } else { 349 /* 32-bit ARM instruction */ 350 __le32 instr_le; 351 if (get_user(instr_le, (__le32 __user *)pc)) 352 goto exit; 353 instr = le32_to_cpu(instr_le); 354 } 355 356 raw_spin_lock_irqsave(&undef_lock, flags); 357 list_for_each_entry(hook, &undef_hook, node) 358 if ((instr & hook->instr_mask) == hook->instr_val && 359 (regs->pstate & hook->pstate_mask) == hook->pstate_val) 360 fn = hook->fn; 361 362 raw_spin_unlock_irqrestore(&undef_lock, flags); 363 exit: 364 return fn ? fn(regs, instr) : 1; 365 } 366 367 void force_signal_inject(int signal, int code, unsigned long address) 368 { 369 const char *desc; 370 struct pt_regs *regs = current_pt_regs(); 371 372 if (WARN_ON(!user_mode(regs))) 373 return; 374 375 switch (signal) { 376 case SIGILL: 377 desc = "undefined instruction"; 378 break; 379 case SIGSEGV: 380 desc = "illegal memory access"; 381 break; 382 default: 383 desc = "unknown or unrecoverable error"; 384 break; 385 } 386 387 /* Force signals we don't understand to SIGKILL */ 388 if (WARN_ON(signal != SIGKILL && 389 siginfo_layout(signal, code) != SIL_FAULT)) { 390 signal = SIGKILL; 391 } 392 393 arm64_notify_die(desc, regs, signal, code, (void __user *)address, 0); 394 } 395 396 /* 397 * Set up process info to signal segmentation fault - called on access error. 398 */ 399 void arm64_notify_segfault(unsigned long addr) 400 { 401 int code; 402 403 down_read(¤t->mm->mmap_sem); 404 if (find_vma(current->mm, addr) == NULL) 405 code = SEGV_MAPERR; 406 else 407 code = SEGV_ACCERR; 408 up_read(¤t->mm->mmap_sem); 409 410 force_signal_inject(SIGSEGV, code, addr); 411 } 412 413 asmlinkage void __exception do_undefinstr(struct pt_regs *regs) 414 { 415 /* check for AArch32 breakpoint instructions */ 416 if (!aarch32_break_handler(regs)) 417 return; 418 419 if (call_undef_hook(regs) == 0) 420 return; 421 422 BUG_ON(!user_mode(regs)); 423 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 424 } 425 426 #define __user_cache_maint(insn, address, res) \ 427 if (address >= user_addr_max()) { \ 428 res = -EFAULT; \ 429 } else { \ 430 uaccess_ttbr0_enable(); \ 431 asm volatile ( \ 432 "1: " insn ", %1\n" \ 433 " mov %w0, #0\n" \ 434 "2:\n" \ 435 " .pushsection .fixup,\"ax\"\n" \ 436 " .align 2\n" \ 437 "3: mov %w0, %w2\n" \ 438 " b 2b\n" \ 439 " .popsection\n" \ 440 _ASM_EXTABLE(1b, 3b) \ 441 : "=r" (res) \ 442 : "r" (address), "i" (-EFAULT)); \ 443 uaccess_ttbr0_disable(); \ 444 } 445 446 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) 447 { 448 unsigned long address; 449 int rt = ESR_ELx_SYS64_ISS_RT(esr); 450 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 451 int ret = 0; 452 453 address = untagged_addr(pt_regs_read_reg(regs, rt)); 454 455 switch (crm) { 456 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ 457 __user_cache_maint("dc civac", address, ret); 458 break; 459 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ 460 __user_cache_maint("dc civac", address, ret); 461 break; 462 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ 463 __user_cache_maint("sys 3, c7, c12, 1", address, ret); 464 break; 465 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ 466 __user_cache_maint("dc civac", address, ret); 467 break; 468 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ 469 __user_cache_maint("ic ivau", address, ret); 470 break; 471 default: 472 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 473 return; 474 } 475 476 if (ret) 477 arm64_notify_segfault(address); 478 else 479 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 480 } 481 482 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) 483 { 484 int rt = ESR_ELx_SYS64_ISS_RT(esr); 485 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); 486 487 pt_regs_write_reg(regs, rt, val); 488 489 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 490 } 491 492 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 493 { 494 int rt = ESR_ELx_SYS64_ISS_RT(esr); 495 496 pt_regs_write_reg(regs, rt, arch_counter_get_cntvct()); 497 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 498 } 499 500 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 501 { 502 int rt = ESR_ELx_SYS64_ISS_RT(esr); 503 504 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); 505 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 506 } 507 508 static void mrs_handler(unsigned int esr, struct pt_regs *regs) 509 { 510 u32 sysreg, rt; 511 512 rt = ESR_ELx_SYS64_ISS_RT(esr); 513 sysreg = esr_sys64_to_sysreg(esr); 514 515 if (do_emulate_mrs(regs, sysreg, rt) != 0) 516 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 517 } 518 519 static void wfi_handler(unsigned int esr, struct pt_regs *regs) 520 { 521 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 522 } 523 524 struct sys64_hook { 525 unsigned int esr_mask; 526 unsigned int esr_val; 527 void (*handler)(unsigned int esr, struct pt_regs *regs); 528 }; 529 530 static struct sys64_hook sys64_hooks[] = { 531 { 532 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, 533 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, 534 .handler = user_cache_maint_handler, 535 }, 536 { 537 /* Trap read access to CTR_EL0 */ 538 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 539 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, 540 .handler = ctr_read_handler, 541 }, 542 { 543 /* Trap read access to CNTVCT_EL0 */ 544 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 545 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, 546 .handler = cntvct_read_handler, 547 }, 548 { 549 /* Trap read access to CNTFRQ_EL0 */ 550 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 551 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, 552 .handler = cntfrq_read_handler, 553 }, 554 { 555 /* Trap read access to CPUID registers */ 556 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, 557 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, 558 .handler = mrs_handler, 559 }, 560 { 561 /* Trap WFI instructions executed in userspace */ 562 .esr_mask = ESR_ELx_WFx_MASK, 563 .esr_val = ESR_ELx_WFx_WFI_VAL, 564 .handler = wfi_handler, 565 }, 566 {}, 567 }; 568 569 570 #ifdef CONFIG_COMPAT 571 #define PSTATE_IT_1_0_SHIFT 25 572 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) 573 #define PSTATE_IT_7_2_SHIFT 10 574 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) 575 576 static u32 compat_get_it_state(struct pt_regs *regs) 577 { 578 u32 it, pstate = regs->pstate; 579 580 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; 581 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; 582 583 return it; 584 } 585 586 static void compat_set_it_state(struct pt_regs *regs, u32 it) 587 { 588 u32 pstate_it; 589 590 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; 591 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; 592 593 regs->pstate &= ~PSR_AA32_IT_MASK; 594 regs->pstate |= pstate_it; 595 } 596 597 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs) 598 { 599 int cond; 600 601 /* Only a T32 instruction can trap without CV being set */ 602 if (!(esr & ESR_ELx_CV)) { 603 u32 it; 604 605 it = compat_get_it_state(regs); 606 if (!it) 607 return true; 608 609 cond = it >> 4; 610 } else { 611 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 612 } 613 614 return aarch32_opcode_cond_checks[cond](regs->pstate); 615 } 616 617 static void advance_itstate(struct pt_regs *regs) 618 { 619 u32 it; 620 621 /* ARM mode */ 622 if (!(regs->pstate & PSR_AA32_T_BIT) || 623 !(regs->pstate & PSR_AA32_IT_MASK)) 624 return; 625 626 it = compat_get_it_state(regs); 627 628 /* 629 * If this is the last instruction of the block, wipe the IT 630 * state. Otherwise advance it. 631 */ 632 if (!(it & 7)) 633 it = 0; 634 else 635 it = (it & 0xe0) | ((it << 1) & 0x1f); 636 637 compat_set_it_state(regs, it); 638 } 639 640 static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs, 641 unsigned int sz) 642 { 643 advance_itstate(regs); 644 arm64_skip_faulting_instruction(regs, sz); 645 } 646 647 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 648 { 649 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; 650 651 pt_regs_write_reg(regs, reg, arch_timer_get_rate()); 652 arm64_compat_skip_faulting_instruction(regs, 4); 653 } 654 655 static struct sys64_hook cp15_32_hooks[] = { 656 { 657 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, 658 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, 659 .handler = compat_cntfrq_read_handler, 660 }, 661 {}, 662 }; 663 664 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 665 { 666 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; 667 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; 668 u64 val = arch_counter_get_cntvct(); 669 670 pt_regs_write_reg(regs, rt, lower_32_bits(val)); 671 pt_regs_write_reg(regs, rt2, upper_32_bits(val)); 672 arm64_compat_skip_faulting_instruction(regs, 4); 673 } 674 675 static struct sys64_hook cp15_64_hooks[] = { 676 { 677 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 678 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, 679 .handler = compat_cntvct_read_handler, 680 }, 681 {}, 682 }; 683 684 asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs) 685 { 686 struct sys64_hook *hook, *hook_base; 687 688 if (!cp15_cond_valid(esr, regs)) { 689 /* 690 * There is no T16 variant of a CP access, so we 691 * always advance PC by 4 bytes. 692 */ 693 arm64_compat_skip_faulting_instruction(regs, 4); 694 return; 695 } 696 697 switch (ESR_ELx_EC(esr)) { 698 case ESR_ELx_EC_CP15_32: 699 hook_base = cp15_32_hooks; 700 break; 701 case ESR_ELx_EC_CP15_64: 702 hook_base = cp15_64_hooks; 703 break; 704 default: 705 do_undefinstr(regs); 706 return; 707 } 708 709 for (hook = hook_base; hook->handler; hook++) 710 if ((hook->esr_mask & esr) == hook->esr_val) { 711 hook->handler(esr, regs); 712 return; 713 } 714 715 /* 716 * New cp15 instructions may previously have been undefined at 717 * EL0. Fall back to our usual undefined instruction handler 718 * so that we handle these consistently. 719 */ 720 do_undefinstr(regs); 721 } 722 #endif 723 724 asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs) 725 { 726 struct sys64_hook *hook; 727 728 for (hook = sys64_hooks; hook->handler; hook++) 729 if ((hook->esr_mask & esr) == hook->esr_val) { 730 hook->handler(esr, regs); 731 return; 732 } 733 734 /* 735 * New SYS instructions may previously have been undefined at EL0. Fall 736 * back to our usual undefined instruction handler so that we handle 737 * these consistently. 738 */ 739 do_undefinstr(regs); 740 } 741 742 static const char *esr_class_str[] = { 743 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", 744 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", 745 [ESR_ELx_EC_WFx] = "WFI/WFE", 746 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", 747 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", 748 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", 749 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", 750 [ESR_ELx_EC_FP_ASIMD] = "ASIMD", 751 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", 752 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", 753 [ESR_ELx_EC_ILL] = "PSTATE.IL", 754 [ESR_ELx_EC_SVC32] = "SVC (AArch32)", 755 [ESR_ELx_EC_HVC32] = "HVC (AArch32)", 756 [ESR_ELx_EC_SMC32] = "SMC (AArch32)", 757 [ESR_ELx_EC_SVC64] = "SVC (AArch64)", 758 [ESR_ELx_EC_HVC64] = "HVC (AArch64)", 759 [ESR_ELx_EC_SMC64] = "SMC (AArch64)", 760 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", 761 [ESR_ELx_EC_SVE] = "SVE", 762 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", 763 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", 764 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", 765 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment", 766 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", 767 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", 768 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment", 769 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", 770 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", 771 [ESR_ELx_EC_SERROR] = "SError", 772 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", 773 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", 774 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", 775 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", 776 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", 777 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", 778 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", 779 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", 780 [ESR_ELx_EC_BRK64] = "BRK (AArch64)", 781 }; 782 783 const char *esr_get_class_string(u32 esr) 784 { 785 return esr_class_str[ESR_ELx_EC(esr)]; 786 } 787 788 /* 789 * bad_mode handles the impossible case in the exception vector. This is always 790 * fatal. 791 */ 792 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr) 793 { 794 console_verbose(); 795 796 pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n", 797 handler[reason], smp_processor_id(), esr, 798 esr_get_class_string(esr)); 799 800 local_daif_mask(); 801 panic("bad mode"); 802 } 803 804 /* 805 * bad_el0_sync handles unexpected, but potentially recoverable synchronous 806 * exceptions taken from EL0. Unlike bad_mode, this returns. 807 */ 808 asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr) 809 { 810 void __user *pc = (void __user *)instruction_pointer(regs); 811 812 current->thread.fault_address = 0; 813 current->thread.fault_code = esr; 814 815 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, 816 "Bad EL0 synchronous exception"); 817 } 818 819 #ifdef CONFIG_VMAP_STACK 820 821 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) 822 __aligned(16); 823 824 asmlinkage void handle_bad_stack(struct pt_regs *regs) 825 { 826 unsigned long tsk_stk = (unsigned long)current->stack; 827 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); 828 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); 829 unsigned int esr = read_sysreg(esr_el1); 830 unsigned long far = read_sysreg(far_el1); 831 832 console_verbose(); 833 pr_emerg("Insufficient stack space to handle exception!"); 834 835 pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr)); 836 pr_emerg("FAR: 0x%016lx\n", far); 837 838 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", 839 tsk_stk, tsk_stk + THREAD_SIZE); 840 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", 841 irq_stk, irq_stk + THREAD_SIZE); 842 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", 843 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); 844 845 __show_regs(regs); 846 847 /* 848 * We use nmi_panic to limit the potential for recusive overflows, and 849 * to get a better stack trace. 850 */ 851 nmi_panic(NULL, "kernel stack overflow"); 852 cpu_park_loop(); 853 } 854 #endif 855 856 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr) 857 { 858 console_verbose(); 859 860 pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n", 861 smp_processor_id(), esr, esr_get_class_string(esr)); 862 if (regs) 863 __show_regs(regs); 864 865 nmi_panic(regs, "Asynchronous SError Interrupt"); 866 867 cpu_park_loop(); 868 unreachable(); 869 } 870 871 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr) 872 { 873 u32 aet = arm64_ras_serror_get_severity(esr); 874 875 switch (aet) { 876 case ESR_ELx_AET_CE: /* corrected error */ 877 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ 878 /* 879 * The CPU can make progress. We may take UEO again as 880 * a more severe error. 881 */ 882 return false; 883 884 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ 885 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ 886 /* 887 * The CPU can't make progress. The exception may have 888 * been imprecise. 889 */ 890 return true; 891 892 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ 893 default: 894 /* Error has been silently propagated */ 895 arm64_serror_panic(regs, esr); 896 } 897 } 898 899 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr) 900 { 901 const bool was_in_nmi = in_nmi(); 902 903 if (!was_in_nmi) 904 nmi_enter(); 905 906 /* non-RAS errors are not containable */ 907 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) 908 arm64_serror_panic(regs, esr); 909 910 if (!was_in_nmi) 911 nmi_exit(); 912 } 913 914 void __pte_error(const char *file, int line, unsigned long val) 915 { 916 pr_err("%s:%d: bad pte %016lx.\n", file, line, val); 917 } 918 919 void __pmd_error(const char *file, int line, unsigned long val) 920 { 921 pr_err("%s:%d: bad pmd %016lx.\n", file, line, val); 922 } 923 924 void __pud_error(const char *file, int line, unsigned long val) 925 { 926 pr_err("%s:%d: bad pud %016lx.\n", file, line, val); 927 } 928 929 void __pgd_error(const char *file, int line, unsigned long val) 930 { 931 pr_err("%s:%d: bad pgd %016lx.\n", file, line, val); 932 } 933 934 /* GENERIC_BUG traps */ 935 936 int is_valid_bugaddr(unsigned long addr) 937 { 938 /* 939 * bug_handler() only called for BRK #BUG_BRK_IMM. 940 * So the answer is trivial -- any spurious instances with no 941 * bug table entry will be rejected by report_bug() and passed 942 * back to the debug-monitors code and handled as a fatal 943 * unexpected debug exception. 944 */ 945 return 1; 946 } 947 948 static int bug_handler(struct pt_regs *regs, unsigned int esr) 949 { 950 if (user_mode(regs)) 951 return DBG_HOOK_ERROR; 952 953 switch (report_bug(regs->pc, regs)) { 954 case BUG_TRAP_TYPE_BUG: 955 die("Oops - BUG", regs, 0); 956 break; 957 958 case BUG_TRAP_TYPE_WARN: 959 break; 960 961 default: 962 /* unknown/unrecognised bug trap type */ 963 return DBG_HOOK_ERROR; 964 } 965 966 /* If thread survives, skip over the BUG instruction and continue: */ 967 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 968 return DBG_HOOK_HANDLED; 969 } 970 971 static struct break_hook bug_break_hook = { 972 .esr_val = 0xf2000000 | BUG_BRK_IMM, 973 .esr_mask = 0xffffffff, 974 .fn = bug_handler, 975 }; 976 977 #ifdef CONFIG_KASAN_SW_TAGS 978 979 #define KASAN_ESR_RECOVER 0x20 980 #define KASAN_ESR_WRITE 0x10 981 #define KASAN_ESR_SIZE_MASK 0x0f 982 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) 983 984 static int kasan_handler(struct pt_regs *regs, unsigned int esr) 985 { 986 bool recover = esr & KASAN_ESR_RECOVER; 987 bool write = esr & KASAN_ESR_WRITE; 988 size_t size = KASAN_ESR_SIZE(esr); 989 u64 addr = regs->regs[0]; 990 u64 pc = regs->pc; 991 992 if (user_mode(regs)) 993 return DBG_HOOK_ERROR; 994 995 kasan_report(addr, size, write, pc); 996 997 /* 998 * The instrumentation allows to control whether we can proceed after 999 * a crash was detected. This is done by passing the -recover flag to 1000 * the compiler. Disabling recovery allows to generate more compact 1001 * code. 1002 * 1003 * Unfortunately disabling recovery doesn't work for the kernel right 1004 * now. KASAN reporting is disabled in some contexts (for example when 1005 * the allocator accesses slab object metadata; this is controlled by 1006 * current->kasan_depth). All these accesses are detected by the tool, 1007 * even though the reports for them are not printed. 1008 * 1009 * This is something that might be fixed at some point in the future. 1010 */ 1011 if (!recover) 1012 die("Oops - KASAN", regs, 0); 1013 1014 /* If thread survives, skip over the brk instruction and continue: */ 1015 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1016 return DBG_HOOK_HANDLED; 1017 } 1018 1019 #define KASAN_ESR_VAL (0xf2000000 | KASAN_BRK_IMM) 1020 #define KASAN_ESR_MASK 0xffffff00 1021 1022 static struct break_hook kasan_break_hook = { 1023 .esr_val = KASAN_ESR_VAL, 1024 .esr_mask = KASAN_ESR_MASK, 1025 .fn = kasan_handler, 1026 }; 1027 #endif 1028 1029 /* 1030 * Initial handler for AArch64 BRK exceptions 1031 * This handler only used until debug_traps_init(). 1032 */ 1033 int __init early_brk64(unsigned long addr, unsigned int esr, 1034 struct pt_regs *regs) 1035 { 1036 #ifdef CONFIG_KASAN_SW_TAGS 1037 if ((esr & KASAN_ESR_MASK) == KASAN_ESR_VAL) 1038 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; 1039 #endif 1040 return bug_handler(regs, esr) != DBG_HOOK_HANDLED; 1041 } 1042 1043 /* This registration must happen early, before debug_traps_init(). */ 1044 void __init trap_init(void) 1045 { 1046 register_break_hook(&bug_break_hook); 1047 #ifdef CONFIG_KASAN_SW_TAGS 1048 register_break_hook(&kasan_break_hook); 1049 #endif 1050 } 1051