1 /* 2 * Based on arch/arm/kernel/traps.c 3 * 4 * Copyright (C) 1995-2009 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/bug.h> 21 #include <linux/signal.h> 22 #include <linux/personality.h> 23 #include <linux/kallsyms.h> 24 #include <linux/spinlock.h> 25 #include <linux/uaccess.h> 26 #include <linux/hardirq.h> 27 #include <linux/kdebug.h> 28 #include <linux/module.h> 29 #include <linux/kexec.h> 30 #include <linux/delay.h> 31 #include <linux/init.h> 32 #include <linux/sched/signal.h> 33 #include <linux/sched/debug.h> 34 #include <linux/sched/task_stack.h> 35 #include <linux/sizes.h> 36 #include <linux/syscalls.h> 37 #include <linux/mm_types.h> 38 #include <linux/kasan.h> 39 40 #include <asm/atomic.h> 41 #include <asm/bug.h> 42 #include <asm/cpufeature.h> 43 #include <asm/daifflags.h> 44 #include <asm/debug-monitors.h> 45 #include <asm/esr.h> 46 #include <asm/insn.h> 47 #include <asm/traps.h> 48 #include <asm/smp.h> 49 #include <asm/stack_pointer.h> 50 #include <asm/stacktrace.h> 51 #include <asm/exception.h> 52 #include <asm/system_misc.h> 53 #include <asm/sysreg.h> 54 55 static const char *handler[]= { 56 "Synchronous Abort", 57 "IRQ", 58 "FIQ", 59 "Error" 60 }; 61 62 int show_unhandled_signals = 0; 63 64 static void dump_backtrace_entry(unsigned long where) 65 { 66 printk(" %pS\n", (void *)where); 67 } 68 69 static void __dump_instr(const char *lvl, struct pt_regs *regs) 70 { 71 unsigned long addr = instruction_pointer(regs); 72 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 73 int i; 74 75 for (i = -4; i < 1; i++) { 76 unsigned int val, bad; 77 78 bad = get_user(val, &((u32 *)addr)[i]); 79 80 if (!bad) 81 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); 82 else { 83 p += sprintf(p, "bad PC value"); 84 break; 85 } 86 } 87 printk("%sCode: %s\n", lvl, str); 88 } 89 90 static void dump_instr(const char *lvl, struct pt_regs *regs) 91 { 92 if (!user_mode(regs)) { 93 mm_segment_t fs = get_fs(); 94 set_fs(KERNEL_DS); 95 __dump_instr(lvl, regs); 96 set_fs(fs); 97 } else { 98 __dump_instr(lvl, regs); 99 } 100 } 101 102 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) 103 { 104 struct stackframe frame; 105 int skip = 0; 106 107 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); 108 109 if (regs) { 110 if (user_mode(regs)) 111 return; 112 skip = 1; 113 } 114 115 if (!tsk) 116 tsk = current; 117 118 if (!try_get_task_stack(tsk)) 119 return; 120 121 if (tsk == current) { 122 frame.fp = (unsigned long)__builtin_frame_address(0); 123 frame.pc = (unsigned long)dump_backtrace; 124 } else { 125 /* 126 * task blocked in __switch_to 127 */ 128 frame.fp = thread_saved_fp(tsk); 129 frame.pc = thread_saved_pc(tsk); 130 } 131 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 132 frame.graph = 0; 133 #endif 134 135 printk("Call trace:\n"); 136 do { 137 /* skip until specified stack frame */ 138 if (!skip) { 139 dump_backtrace_entry(frame.pc); 140 } else if (frame.fp == regs->regs[29]) { 141 skip = 0; 142 /* 143 * Mostly, this is the case where this function is 144 * called in panic/abort. As exception handler's 145 * stack frame does not contain the corresponding pc 146 * at which an exception has taken place, use regs->pc 147 * instead. 148 */ 149 dump_backtrace_entry(regs->pc); 150 } 151 } while (!unwind_frame(tsk, &frame)); 152 153 put_task_stack(tsk); 154 } 155 156 void show_stack(struct task_struct *tsk, unsigned long *sp) 157 { 158 dump_backtrace(NULL, tsk); 159 barrier(); 160 } 161 162 #ifdef CONFIG_PREEMPT 163 #define S_PREEMPT " PREEMPT" 164 #else 165 #define S_PREEMPT "" 166 #endif 167 #define S_SMP " SMP" 168 169 static int __die(const char *str, int err, struct pt_regs *regs) 170 { 171 static int die_counter; 172 int ret; 173 174 pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", 175 str, err, ++die_counter); 176 177 /* trap and error numbers are mostly meaningless on ARM */ 178 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); 179 if (ret == NOTIFY_STOP) 180 return ret; 181 182 print_modules(); 183 show_regs(regs); 184 185 if (!user_mode(regs)) 186 dump_instr(KERN_EMERG, regs); 187 188 return ret; 189 } 190 191 static DEFINE_RAW_SPINLOCK(die_lock); 192 193 /* 194 * This function is protected against re-entrancy. 195 */ 196 void die(const char *str, struct pt_regs *regs, int err) 197 { 198 int ret; 199 unsigned long flags; 200 201 raw_spin_lock_irqsave(&die_lock, flags); 202 203 oops_enter(); 204 205 console_verbose(); 206 bust_spinlocks(1); 207 ret = __die(str, err, regs); 208 209 if (regs && kexec_should_crash(current)) 210 crash_kexec(regs); 211 212 bust_spinlocks(0); 213 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 214 oops_exit(); 215 216 if (in_interrupt()) 217 panic("Fatal exception in interrupt"); 218 if (panic_on_oops) 219 panic("Fatal exception"); 220 221 raw_spin_unlock_irqrestore(&die_lock, flags); 222 223 if (ret != NOTIFY_STOP) 224 do_exit(SIGSEGV); 225 } 226 227 static void arm64_show_signal(int signo, const char *str) 228 { 229 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 230 DEFAULT_RATELIMIT_BURST); 231 struct task_struct *tsk = current; 232 unsigned int esr = tsk->thread.fault_code; 233 struct pt_regs *regs = task_pt_regs(tsk); 234 235 /* Leave if the signal won't be shown */ 236 if (!show_unhandled_signals || 237 !unhandled_signal(tsk, signo) || 238 !__ratelimit(&rs)) 239 return; 240 241 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); 242 if (esr) 243 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr); 244 245 pr_cont("%s", str); 246 print_vma_addr(KERN_CONT " in ", regs->pc); 247 pr_cont("\n"); 248 __show_regs(regs); 249 } 250 251 void arm64_force_sig_fault(int signo, int code, void __user *addr, 252 const char *str) 253 { 254 arm64_show_signal(signo, str); 255 force_sig_fault(signo, code, addr, current); 256 } 257 258 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb, 259 const char *str) 260 { 261 arm64_show_signal(SIGBUS, str); 262 force_sig_mceerr(code, addr, lsb, current); 263 } 264 265 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr, 266 const char *str) 267 { 268 arm64_show_signal(SIGTRAP, str); 269 force_sig_ptrace_errno_trap(errno, addr); 270 } 271 272 void arm64_notify_die(const char *str, struct pt_regs *regs, 273 int signo, int sicode, void __user *addr, 274 int err) 275 { 276 if (user_mode(regs)) { 277 WARN_ON(regs != current_pt_regs()); 278 current->thread.fault_address = 0; 279 current->thread.fault_code = err; 280 281 arm64_force_sig_fault(signo, sicode, addr, str); 282 } else { 283 die(str, regs, err); 284 } 285 } 286 287 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) 288 { 289 regs->pc += size; 290 291 /* 292 * If we were single stepping, we want to get the step exception after 293 * we return from the trap. 294 */ 295 if (user_mode(regs)) 296 user_fastforward_single_step(current); 297 } 298 299 static LIST_HEAD(undef_hook); 300 static DEFINE_RAW_SPINLOCK(undef_lock); 301 302 void register_undef_hook(struct undef_hook *hook) 303 { 304 unsigned long flags; 305 306 raw_spin_lock_irqsave(&undef_lock, flags); 307 list_add(&hook->node, &undef_hook); 308 raw_spin_unlock_irqrestore(&undef_lock, flags); 309 } 310 311 void unregister_undef_hook(struct undef_hook *hook) 312 { 313 unsigned long flags; 314 315 raw_spin_lock_irqsave(&undef_lock, flags); 316 list_del(&hook->node); 317 raw_spin_unlock_irqrestore(&undef_lock, flags); 318 } 319 320 static int call_undef_hook(struct pt_regs *regs) 321 { 322 struct undef_hook *hook; 323 unsigned long flags; 324 u32 instr; 325 int (*fn)(struct pt_regs *regs, u32 instr) = NULL; 326 void __user *pc = (void __user *)instruction_pointer(regs); 327 328 if (!user_mode(regs)) { 329 __le32 instr_le; 330 if (probe_kernel_address((__force __le32 *)pc, instr_le)) 331 goto exit; 332 instr = le32_to_cpu(instr_le); 333 } else if (compat_thumb_mode(regs)) { 334 /* 16-bit Thumb instruction */ 335 __le16 instr_le; 336 if (get_user(instr_le, (__le16 __user *)pc)) 337 goto exit; 338 instr = le16_to_cpu(instr_le); 339 if (aarch32_insn_is_wide(instr)) { 340 u32 instr2; 341 342 if (get_user(instr_le, (__le16 __user *)(pc + 2))) 343 goto exit; 344 instr2 = le16_to_cpu(instr_le); 345 instr = (instr << 16) | instr2; 346 } 347 } else { 348 /* 32-bit ARM instruction */ 349 __le32 instr_le; 350 if (get_user(instr_le, (__le32 __user *)pc)) 351 goto exit; 352 instr = le32_to_cpu(instr_le); 353 } 354 355 raw_spin_lock_irqsave(&undef_lock, flags); 356 list_for_each_entry(hook, &undef_hook, node) 357 if ((instr & hook->instr_mask) == hook->instr_val && 358 (regs->pstate & hook->pstate_mask) == hook->pstate_val) 359 fn = hook->fn; 360 361 raw_spin_unlock_irqrestore(&undef_lock, flags); 362 exit: 363 return fn ? fn(regs, instr) : 1; 364 } 365 366 void force_signal_inject(int signal, int code, unsigned long address) 367 { 368 const char *desc; 369 struct pt_regs *regs = current_pt_regs(); 370 371 if (WARN_ON(!user_mode(regs))) 372 return; 373 374 switch (signal) { 375 case SIGILL: 376 desc = "undefined instruction"; 377 break; 378 case SIGSEGV: 379 desc = "illegal memory access"; 380 break; 381 default: 382 desc = "unknown or unrecoverable error"; 383 break; 384 } 385 386 /* Force signals we don't understand to SIGKILL */ 387 if (WARN_ON(signal != SIGKILL && 388 siginfo_layout(signal, code) != SIL_FAULT)) { 389 signal = SIGKILL; 390 } 391 392 arm64_notify_die(desc, regs, signal, code, (void __user *)address, 0); 393 } 394 395 /* 396 * Set up process info to signal segmentation fault - called on access error. 397 */ 398 void arm64_notify_segfault(unsigned long addr) 399 { 400 int code; 401 402 down_read(¤t->mm->mmap_sem); 403 if (find_vma(current->mm, addr) == NULL) 404 code = SEGV_MAPERR; 405 else 406 code = SEGV_ACCERR; 407 up_read(¤t->mm->mmap_sem); 408 409 force_signal_inject(SIGSEGV, code, addr); 410 } 411 412 asmlinkage void __exception do_undefinstr(struct pt_regs *regs) 413 { 414 /* check for AArch32 breakpoint instructions */ 415 if (!aarch32_break_handler(regs)) 416 return; 417 418 if (call_undef_hook(regs) == 0) 419 return; 420 421 BUG_ON(!user_mode(regs)); 422 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 423 } 424 425 #define __user_cache_maint(insn, address, res) \ 426 if (address >= user_addr_max()) { \ 427 res = -EFAULT; \ 428 } else { \ 429 uaccess_ttbr0_enable(); \ 430 asm volatile ( \ 431 "1: " insn ", %1\n" \ 432 " mov %w0, #0\n" \ 433 "2:\n" \ 434 " .pushsection .fixup,\"ax\"\n" \ 435 " .align 2\n" \ 436 "3: mov %w0, %w2\n" \ 437 " b 2b\n" \ 438 " .popsection\n" \ 439 _ASM_EXTABLE(1b, 3b) \ 440 : "=r" (res) \ 441 : "r" (address), "i" (-EFAULT)); \ 442 uaccess_ttbr0_disable(); \ 443 } 444 445 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) 446 { 447 unsigned long address; 448 int rt = ESR_ELx_SYS64_ISS_RT(esr); 449 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 450 int ret = 0; 451 452 address = untagged_addr(pt_regs_read_reg(regs, rt)); 453 454 switch (crm) { 455 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ 456 __user_cache_maint("dc civac", address, ret); 457 break; 458 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ 459 __user_cache_maint("dc civac", address, ret); 460 break; 461 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ 462 __user_cache_maint("sys 3, c7, c13, 1", address, ret); 463 break; 464 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ 465 __user_cache_maint("sys 3, c7, c12, 1", address, ret); 466 break; 467 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ 468 __user_cache_maint("dc civac", address, ret); 469 break; 470 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ 471 __user_cache_maint("ic ivau", address, ret); 472 break; 473 default: 474 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 475 return; 476 } 477 478 if (ret) 479 arm64_notify_segfault(address); 480 else 481 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 482 } 483 484 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) 485 { 486 int rt = ESR_ELx_SYS64_ISS_RT(esr); 487 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); 488 489 pt_regs_write_reg(regs, rt, val); 490 491 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 492 } 493 494 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 495 { 496 int rt = ESR_ELx_SYS64_ISS_RT(esr); 497 498 pt_regs_write_reg(regs, rt, arch_timer_read_counter()); 499 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 500 } 501 502 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 503 { 504 int rt = ESR_ELx_SYS64_ISS_RT(esr); 505 506 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); 507 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 508 } 509 510 static void mrs_handler(unsigned int esr, struct pt_regs *regs) 511 { 512 u32 sysreg, rt; 513 514 rt = ESR_ELx_SYS64_ISS_RT(esr); 515 sysreg = esr_sys64_to_sysreg(esr); 516 517 if (do_emulate_mrs(regs, sysreg, rt) != 0) 518 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 519 } 520 521 static void wfi_handler(unsigned int esr, struct pt_regs *regs) 522 { 523 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 524 } 525 526 struct sys64_hook { 527 unsigned int esr_mask; 528 unsigned int esr_val; 529 void (*handler)(unsigned int esr, struct pt_regs *regs); 530 }; 531 532 static struct sys64_hook sys64_hooks[] = { 533 { 534 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, 535 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, 536 .handler = user_cache_maint_handler, 537 }, 538 { 539 /* Trap read access to CTR_EL0 */ 540 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 541 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, 542 .handler = ctr_read_handler, 543 }, 544 { 545 /* Trap read access to CNTVCT_EL0 */ 546 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 547 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, 548 .handler = cntvct_read_handler, 549 }, 550 { 551 /* Trap read access to CNTFRQ_EL0 */ 552 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 553 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, 554 .handler = cntfrq_read_handler, 555 }, 556 { 557 /* Trap read access to CPUID registers */ 558 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, 559 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, 560 .handler = mrs_handler, 561 }, 562 { 563 /* Trap WFI instructions executed in userspace */ 564 .esr_mask = ESR_ELx_WFx_MASK, 565 .esr_val = ESR_ELx_WFx_WFI_VAL, 566 .handler = wfi_handler, 567 }, 568 {}, 569 }; 570 571 572 #ifdef CONFIG_COMPAT 573 #define PSTATE_IT_1_0_SHIFT 25 574 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) 575 #define PSTATE_IT_7_2_SHIFT 10 576 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) 577 578 static u32 compat_get_it_state(struct pt_regs *regs) 579 { 580 u32 it, pstate = regs->pstate; 581 582 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; 583 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; 584 585 return it; 586 } 587 588 static void compat_set_it_state(struct pt_regs *regs, u32 it) 589 { 590 u32 pstate_it; 591 592 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; 593 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; 594 595 regs->pstate &= ~PSR_AA32_IT_MASK; 596 regs->pstate |= pstate_it; 597 } 598 599 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs) 600 { 601 int cond; 602 603 /* Only a T32 instruction can trap without CV being set */ 604 if (!(esr & ESR_ELx_CV)) { 605 u32 it; 606 607 it = compat_get_it_state(regs); 608 if (!it) 609 return true; 610 611 cond = it >> 4; 612 } else { 613 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 614 } 615 616 return aarch32_opcode_cond_checks[cond](regs->pstate); 617 } 618 619 static void advance_itstate(struct pt_regs *regs) 620 { 621 u32 it; 622 623 /* ARM mode */ 624 if (!(regs->pstate & PSR_AA32_T_BIT) || 625 !(regs->pstate & PSR_AA32_IT_MASK)) 626 return; 627 628 it = compat_get_it_state(regs); 629 630 /* 631 * If this is the last instruction of the block, wipe the IT 632 * state. Otherwise advance it. 633 */ 634 if (!(it & 7)) 635 it = 0; 636 else 637 it = (it & 0xe0) | ((it << 1) & 0x1f); 638 639 compat_set_it_state(regs, it); 640 } 641 642 static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs, 643 unsigned int sz) 644 { 645 advance_itstate(regs); 646 arm64_skip_faulting_instruction(regs, sz); 647 } 648 649 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 650 { 651 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; 652 653 pt_regs_write_reg(regs, reg, arch_timer_get_rate()); 654 arm64_compat_skip_faulting_instruction(regs, 4); 655 } 656 657 static struct sys64_hook cp15_32_hooks[] = { 658 { 659 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, 660 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, 661 .handler = compat_cntfrq_read_handler, 662 }, 663 {}, 664 }; 665 666 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 667 { 668 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; 669 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; 670 u64 val = arch_timer_read_counter(); 671 672 pt_regs_write_reg(regs, rt, lower_32_bits(val)); 673 pt_regs_write_reg(regs, rt2, upper_32_bits(val)); 674 arm64_compat_skip_faulting_instruction(regs, 4); 675 } 676 677 static struct sys64_hook cp15_64_hooks[] = { 678 { 679 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 680 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, 681 .handler = compat_cntvct_read_handler, 682 }, 683 {}, 684 }; 685 686 asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs) 687 { 688 struct sys64_hook *hook, *hook_base; 689 690 if (!cp15_cond_valid(esr, regs)) { 691 /* 692 * There is no T16 variant of a CP access, so we 693 * always advance PC by 4 bytes. 694 */ 695 arm64_compat_skip_faulting_instruction(regs, 4); 696 return; 697 } 698 699 switch (ESR_ELx_EC(esr)) { 700 case ESR_ELx_EC_CP15_32: 701 hook_base = cp15_32_hooks; 702 break; 703 case ESR_ELx_EC_CP15_64: 704 hook_base = cp15_64_hooks; 705 break; 706 default: 707 do_undefinstr(regs); 708 return; 709 } 710 711 for (hook = hook_base; hook->handler; hook++) 712 if ((hook->esr_mask & esr) == hook->esr_val) { 713 hook->handler(esr, regs); 714 return; 715 } 716 717 /* 718 * New cp15 instructions may previously have been undefined at 719 * EL0. Fall back to our usual undefined instruction handler 720 * so that we handle these consistently. 721 */ 722 do_undefinstr(regs); 723 } 724 #endif 725 726 asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs) 727 { 728 struct sys64_hook *hook; 729 730 for (hook = sys64_hooks; hook->handler; hook++) 731 if ((hook->esr_mask & esr) == hook->esr_val) { 732 hook->handler(esr, regs); 733 return; 734 } 735 736 /* 737 * New SYS instructions may previously have been undefined at EL0. Fall 738 * back to our usual undefined instruction handler so that we handle 739 * these consistently. 740 */ 741 do_undefinstr(regs); 742 } 743 744 static const char *esr_class_str[] = { 745 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", 746 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", 747 [ESR_ELx_EC_WFx] = "WFI/WFE", 748 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", 749 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", 750 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", 751 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", 752 [ESR_ELx_EC_FP_ASIMD] = "ASIMD", 753 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", 754 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", 755 [ESR_ELx_EC_ILL] = "PSTATE.IL", 756 [ESR_ELx_EC_SVC32] = "SVC (AArch32)", 757 [ESR_ELx_EC_HVC32] = "HVC (AArch32)", 758 [ESR_ELx_EC_SMC32] = "SMC (AArch32)", 759 [ESR_ELx_EC_SVC64] = "SVC (AArch64)", 760 [ESR_ELx_EC_HVC64] = "HVC (AArch64)", 761 [ESR_ELx_EC_SMC64] = "SMC (AArch64)", 762 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", 763 [ESR_ELx_EC_SVE] = "SVE", 764 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", 765 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", 766 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", 767 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment", 768 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", 769 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", 770 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment", 771 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", 772 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", 773 [ESR_ELx_EC_SERROR] = "SError", 774 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", 775 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", 776 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", 777 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", 778 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", 779 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", 780 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", 781 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", 782 [ESR_ELx_EC_BRK64] = "BRK (AArch64)", 783 }; 784 785 const char *esr_get_class_string(u32 esr) 786 { 787 return esr_class_str[ESR_ELx_EC(esr)]; 788 } 789 790 /* 791 * bad_mode handles the impossible case in the exception vector. This is always 792 * fatal. 793 */ 794 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr) 795 { 796 console_verbose(); 797 798 pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n", 799 handler[reason], smp_processor_id(), esr, 800 esr_get_class_string(esr)); 801 802 local_daif_mask(); 803 panic("bad mode"); 804 } 805 806 /* 807 * bad_el0_sync handles unexpected, but potentially recoverable synchronous 808 * exceptions taken from EL0. Unlike bad_mode, this returns. 809 */ 810 asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr) 811 { 812 void __user *pc = (void __user *)instruction_pointer(regs); 813 814 current->thread.fault_address = 0; 815 current->thread.fault_code = esr; 816 817 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, 818 "Bad EL0 synchronous exception"); 819 } 820 821 #ifdef CONFIG_VMAP_STACK 822 823 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) 824 __aligned(16); 825 826 asmlinkage void handle_bad_stack(struct pt_regs *regs) 827 { 828 unsigned long tsk_stk = (unsigned long)current->stack; 829 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); 830 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); 831 unsigned int esr = read_sysreg(esr_el1); 832 unsigned long far = read_sysreg(far_el1); 833 834 console_verbose(); 835 pr_emerg("Insufficient stack space to handle exception!"); 836 837 pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr)); 838 pr_emerg("FAR: 0x%016lx\n", far); 839 840 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", 841 tsk_stk, tsk_stk + THREAD_SIZE); 842 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", 843 irq_stk, irq_stk + THREAD_SIZE); 844 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", 845 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); 846 847 __show_regs(regs); 848 849 /* 850 * We use nmi_panic to limit the potential for recusive overflows, and 851 * to get a better stack trace. 852 */ 853 nmi_panic(NULL, "kernel stack overflow"); 854 cpu_park_loop(); 855 } 856 #endif 857 858 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr) 859 { 860 console_verbose(); 861 862 pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n", 863 smp_processor_id(), esr, esr_get_class_string(esr)); 864 if (regs) 865 __show_regs(regs); 866 867 nmi_panic(regs, "Asynchronous SError Interrupt"); 868 869 cpu_park_loop(); 870 unreachable(); 871 } 872 873 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr) 874 { 875 u32 aet = arm64_ras_serror_get_severity(esr); 876 877 switch (aet) { 878 case ESR_ELx_AET_CE: /* corrected error */ 879 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ 880 /* 881 * The CPU can make progress. We may take UEO again as 882 * a more severe error. 883 */ 884 return false; 885 886 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ 887 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ 888 /* 889 * The CPU can't make progress. The exception may have 890 * been imprecise. 891 */ 892 return true; 893 894 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ 895 default: 896 /* Error has been silently propagated */ 897 arm64_serror_panic(regs, esr); 898 } 899 } 900 901 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr) 902 { 903 const bool was_in_nmi = in_nmi(); 904 905 if (!was_in_nmi) 906 nmi_enter(); 907 908 /* non-RAS errors are not containable */ 909 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) 910 arm64_serror_panic(regs, esr); 911 912 if (!was_in_nmi) 913 nmi_exit(); 914 } 915 916 void __pte_error(const char *file, int line, unsigned long val) 917 { 918 pr_err("%s:%d: bad pte %016lx.\n", file, line, val); 919 } 920 921 void __pmd_error(const char *file, int line, unsigned long val) 922 { 923 pr_err("%s:%d: bad pmd %016lx.\n", file, line, val); 924 } 925 926 void __pud_error(const char *file, int line, unsigned long val) 927 { 928 pr_err("%s:%d: bad pud %016lx.\n", file, line, val); 929 } 930 931 void __pgd_error(const char *file, int line, unsigned long val) 932 { 933 pr_err("%s:%d: bad pgd %016lx.\n", file, line, val); 934 } 935 936 /* GENERIC_BUG traps */ 937 938 int is_valid_bugaddr(unsigned long addr) 939 { 940 /* 941 * bug_handler() only called for BRK #BUG_BRK_IMM. 942 * So the answer is trivial -- any spurious instances with no 943 * bug table entry will be rejected by report_bug() and passed 944 * back to the debug-monitors code and handled as a fatal 945 * unexpected debug exception. 946 */ 947 return 1; 948 } 949 950 static int bug_handler(struct pt_regs *regs, unsigned int esr) 951 { 952 switch (report_bug(regs->pc, regs)) { 953 case BUG_TRAP_TYPE_BUG: 954 die("Oops - BUG", regs, 0); 955 break; 956 957 case BUG_TRAP_TYPE_WARN: 958 break; 959 960 default: 961 /* unknown/unrecognised bug trap type */ 962 return DBG_HOOK_ERROR; 963 } 964 965 /* If thread survives, skip over the BUG instruction and continue: */ 966 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 967 return DBG_HOOK_HANDLED; 968 } 969 970 static struct break_hook bug_break_hook = { 971 .fn = bug_handler, 972 .imm = BUG_BRK_IMM, 973 }; 974 975 #ifdef CONFIG_KASAN_SW_TAGS 976 977 #define KASAN_ESR_RECOVER 0x20 978 #define KASAN_ESR_WRITE 0x10 979 #define KASAN_ESR_SIZE_MASK 0x0f 980 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) 981 982 static int kasan_handler(struct pt_regs *regs, unsigned int esr) 983 { 984 bool recover = esr & KASAN_ESR_RECOVER; 985 bool write = esr & KASAN_ESR_WRITE; 986 size_t size = KASAN_ESR_SIZE(esr); 987 u64 addr = regs->regs[0]; 988 u64 pc = regs->pc; 989 990 kasan_report(addr, size, write, pc); 991 992 /* 993 * The instrumentation allows to control whether we can proceed after 994 * a crash was detected. This is done by passing the -recover flag to 995 * the compiler. Disabling recovery allows to generate more compact 996 * code. 997 * 998 * Unfortunately disabling recovery doesn't work for the kernel right 999 * now. KASAN reporting is disabled in some contexts (for example when 1000 * the allocator accesses slab object metadata; this is controlled by 1001 * current->kasan_depth). All these accesses are detected by the tool, 1002 * even though the reports for them are not printed. 1003 * 1004 * This is something that might be fixed at some point in the future. 1005 */ 1006 if (!recover) 1007 die("Oops - KASAN", regs, 0); 1008 1009 /* If thread survives, skip over the brk instruction and continue: */ 1010 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1011 return DBG_HOOK_HANDLED; 1012 } 1013 1014 static struct break_hook kasan_break_hook = { 1015 .fn = kasan_handler, 1016 .imm = KASAN_BRK_IMM, 1017 .mask = KASAN_BRK_MASK, 1018 }; 1019 #endif 1020 1021 /* 1022 * Initial handler for AArch64 BRK exceptions 1023 * This handler only used until debug_traps_init(). 1024 */ 1025 int __init early_brk64(unsigned long addr, unsigned int esr, 1026 struct pt_regs *regs) 1027 { 1028 #ifdef CONFIG_KASAN_SW_TAGS 1029 unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; 1030 1031 if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM) 1032 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; 1033 #endif 1034 return bug_handler(regs, esr) != DBG_HOOK_HANDLED; 1035 } 1036 1037 /* This registration must happen early, before debug_traps_init(). */ 1038 void __init trap_init(void) 1039 { 1040 register_kernel_break_hook(&bug_break_hook); 1041 #ifdef CONFIG_KASAN_SW_TAGS 1042 register_kernel_break_hook(&kasan_break_hook); 1043 #endif 1044 } 1045