1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/traps.c 4 * 5 * Copyright (C) 1995-2009 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 9 #include <linux/bug.h> 10 #include <linux/context_tracking.h> 11 #include <linux/signal.h> 12 #include <linux/personality.h> 13 #include <linux/kallsyms.h> 14 #include <linux/kprobes.h> 15 #include <linux/spinlock.h> 16 #include <linux/uaccess.h> 17 #include <linux/hardirq.h> 18 #include <linux/kdebug.h> 19 #include <linux/module.h> 20 #include <linux/kexec.h> 21 #include <linux/delay.h> 22 #include <linux/init.h> 23 #include <linux/sched/signal.h> 24 #include <linux/sched/debug.h> 25 #include <linux/sched/task_stack.h> 26 #include <linux/sizes.h> 27 #include <linux/syscalls.h> 28 #include <linux/mm_types.h> 29 #include <linux/kasan.h> 30 31 #include <asm/atomic.h> 32 #include <asm/bug.h> 33 #include <asm/cpufeature.h> 34 #include <asm/daifflags.h> 35 #include <asm/debug-monitors.h> 36 #include <asm/esr.h> 37 #include <asm/insn.h> 38 #include <asm/kprobes.h> 39 #include <asm/traps.h> 40 #include <asm/smp.h> 41 #include <asm/stack_pointer.h> 42 #include <asm/stacktrace.h> 43 #include <asm/exception.h> 44 #include <asm/system_misc.h> 45 #include <asm/sysreg.h> 46 47 static const char *handler[]= { 48 "Synchronous Abort", 49 "IRQ", 50 "FIQ", 51 "Error" 52 }; 53 54 int show_unhandled_signals = 0; 55 56 static void dump_backtrace_entry(unsigned long where) 57 { 58 printk(" %pS\n", (void *)where); 59 } 60 61 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) 62 { 63 unsigned long addr = instruction_pointer(regs); 64 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 65 int i; 66 67 if (user_mode(regs)) 68 return; 69 70 for (i = -4; i < 1; i++) { 71 unsigned int val, bad; 72 73 bad = aarch64_insn_read(&((u32 *)addr)[i], &val); 74 75 if (!bad) 76 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); 77 else { 78 p += sprintf(p, "bad PC value"); 79 break; 80 } 81 } 82 83 printk("%sCode: %s\n", lvl, str); 84 } 85 86 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) 87 { 88 struct stackframe frame; 89 int skip = 0; 90 91 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); 92 93 if (regs) { 94 if (user_mode(regs)) 95 return; 96 skip = 1; 97 } 98 99 if (!tsk) 100 tsk = current; 101 102 if (!try_get_task_stack(tsk)) 103 return; 104 105 if (tsk == current) { 106 start_backtrace(&frame, 107 (unsigned long)__builtin_frame_address(0), 108 (unsigned long)dump_backtrace); 109 } else { 110 /* 111 * task blocked in __switch_to 112 */ 113 start_backtrace(&frame, 114 thread_saved_fp(tsk), 115 thread_saved_pc(tsk)); 116 } 117 118 printk("Call trace:\n"); 119 do { 120 /* skip until specified stack frame */ 121 if (!skip) { 122 dump_backtrace_entry(frame.pc); 123 } else if (frame.fp == regs->regs[29]) { 124 skip = 0; 125 /* 126 * Mostly, this is the case where this function is 127 * called in panic/abort. As exception handler's 128 * stack frame does not contain the corresponding pc 129 * at which an exception has taken place, use regs->pc 130 * instead. 131 */ 132 dump_backtrace_entry(regs->pc); 133 } 134 } while (!unwind_frame(tsk, &frame)); 135 136 put_task_stack(tsk); 137 } 138 139 void show_stack(struct task_struct *tsk, unsigned long *sp) 140 { 141 dump_backtrace(NULL, tsk); 142 barrier(); 143 } 144 145 #ifdef CONFIG_PREEMPT 146 #define S_PREEMPT " PREEMPT" 147 #else 148 #define S_PREEMPT "" 149 #endif 150 #define S_SMP " SMP" 151 152 static int __die(const char *str, int err, struct pt_regs *regs) 153 { 154 static int die_counter; 155 int ret; 156 157 pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", 158 str, err, ++die_counter); 159 160 /* trap and error numbers are mostly meaningless on ARM */ 161 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); 162 if (ret == NOTIFY_STOP) 163 return ret; 164 165 print_modules(); 166 show_regs(regs); 167 168 dump_kernel_instr(KERN_EMERG, regs); 169 170 return ret; 171 } 172 173 static DEFINE_RAW_SPINLOCK(die_lock); 174 175 /* 176 * This function is protected against re-entrancy. 177 */ 178 void die(const char *str, struct pt_regs *regs, int err) 179 { 180 int ret; 181 unsigned long flags; 182 183 raw_spin_lock_irqsave(&die_lock, flags); 184 185 oops_enter(); 186 187 console_verbose(); 188 bust_spinlocks(1); 189 ret = __die(str, err, regs); 190 191 if (regs && kexec_should_crash(current)) 192 crash_kexec(regs); 193 194 bust_spinlocks(0); 195 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 196 oops_exit(); 197 198 if (in_interrupt()) 199 panic("Fatal exception in interrupt"); 200 if (panic_on_oops) 201 panic("Fatal exception"); 202 203 raw_spin_unlock_irqrestore(&die_lock, flags); 204 205 if (ret != NOTIFY_STOP) 206 do_exit(SIGSEGV); 207 } 208 209 static void arm64_show_signal(int signo, const char *str) 210 { 211 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 212 DEFAULT_RATELIMIT_BURST); 213 struct task_struct *tsk = current; 214 unsigned int esr = tsk->thread.fault_code; 215 struct pt_regs *regs = task_pt_regs(tsk); 216 217 /* Leave if the signal won't be shown */ 218 if (!show_unhandled_signals || 219 !unhandled_signal(tsk, signo) || 220 !__ratelimit(&rs)) 221 return; 222 223 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); 224 if (esr) 225 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr); 226 227 pr_cont("%s", str); 228 print_vma_addr(KERN_CONT " in ", regs->pc); 229 pr_cont("\n"); 230 __show_regs(regs); 231 } 232 233 void arm64_force_sig_fault(int signo, int code, void __user *addr, 234 const char *str) 235 { 236 arm64_show_signal(signo, str); 237 if (signo == SIGKILL) 238 force_sig(SIGKILL); 239 else 240 force_sig_fault(signo, code, addr); 241 } 242 243 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb, 244 const char *str) 245 { 246 arm64_show_signal(SIGBUS, str); 247 force_sig_mceerr(code, addr, lsb); 248 } 249 250 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr, 251 const char *str) 252 { 253 arm64_show_signal(SIGTRAP, str); 254 force_sig_ptrace_errno_trap(errno, addr); 255 } 256 257 void arm64_notify_die(const char *str, struct pt_regs *regs, 258 int signo, int sicode, void __user *addr, 259 int err) 260 { 261 if (user_mode(regs)) { 262 WARN_ON(regs != current_pt_regs()); 263 current->thread.fault_address = 0; 264 current->thread.fault_code = err; 265 266 arm64_force_sig_fault(signo, sicode, addr, str); 267 } else { 268 die(str, regs, err); 269 } 270 } 271 272 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) 273 { 274 regs->pc += size; 275 276 /* 277 * If we were single stepping, we want to get the step exception after 278 * we return from the trap. 279 */ 280 if (user_mode(regs)) 281 user_fastforward_single_step(current); 282 } 283 284 static LIST_HEAD(undef_hook); 285 static DEFINE_RAW_SPINLOCK(undef_lock); 286 287 void register_undef_hook(struct undef_hook *hook) 288 { 289 unsigned long flags; 290 291 raw_spin_lock_irqsave(&undef_lock, flags); 292 list_add(&hook->node, &undef_hook); 293 raw_spin_unlock_irqrestore(&undef_lock, flags); 294 } 295 296 void unregister_undef_hook(struct undef_hook *hook) 297 { 298 unsigned long flags; 299 300 raw_spin_lock_irqsave(&undef_lock, flags); 301 list_del(&hook->node); 302 raw_spin_unlock_irqrestore(&undef_lock, flags); 303 } 304 305 static int call_undef_hook(struct pt_regs *regs) 306 { 307 struct undef_hook *hook; 308 unsigned long flags; 309 u32 instr; 310 int (*fn)(struct pt_regs *regs, u32 instr) = NULL; 311 void __user *pc = (void __user *)instruction_pointer(regs); 312 313 if (!user_mode(regs)) { 314 __le32 instr_le; 315 if (probe_kernel_address((__force __le32 *)pc, instr_le)) 316 goto exit; 317 instr = le32_to_cpu(instr_le); 318 } else if (compat_thumb_mode(regs)) { 319 /* 16-bit Thumb instruction */ 320 __le16 instr_le; 321 if (get_user(instr_le, (__le16 __user *)pc)) 322 goto exit; 323 instr = le16_to_cpu(instr_le); 324 if (aarch32_insn_is_wide(instr)) { 325 u32 instr2; 326 327 if (get_user(instr_le, (__le16 __user *)(pc + 2))) 328 goto exit; 329 instr2 = le16_to_cpu(instr_le); 330 instr = (instr << 16) | instr2; 331 } 332 } else { 333 /* 32-bit ARM instruction */ 334 __le32 instr_le; 335 if (get_user(instr_le, (__le32 __user *)pc)) 336 goto exit; 337 instr = le32_to_cpu(instr_le); 338 } 339 340 raw_spin_lock_irqsave(&undef_lock, flags); 341 list_for_each_entry(hook, &undef_hook, node) 342 if ((instr & hook->instr_mask) == hook->instr_val && 343 (regs->pstate & hook->pstate_mask) == hook->pstate_val) 344 fn = hook->fn; 345 346 raw_spin_unlock_irqrestore(&undef_lock, flags); 347 exit: 348 return fn ? fn(regs, instr) : 1; 349 } 350 351 void force_signal_inject(int signal, int code, unsigned long address) 352 { 353 const char *desc; 354 struct pt_regs *regs = current_pt_regs(); 355 356 if (WARN_ON(!user_mode(regs))) 357 return; 358 359 switch (signal) { 360 case SIGILL: 361 desc = "undefined instruction"; 362 break; 363 case SIGSEGV: 364 desc = "illegal memory access"; 365 break; 366 default: 367 desc = "unknown or unrecoverable error"; 368 break; 369 } 370 371 /* Force signals we don't understand to SIGKILL */ 372 if (WARN_ON(signal != SIGKILL && 373 siginfo_layout(signal, code) != SIL_FAULT)) { 374 signal = SIGKILL; 375 } 376 377 arm64_notify_die(desc, regs, signal, code, (void __user *)address, 0); 378 } 379 380 /* 381 * Set up process info to signal segmentation fault - called on access error. 382 */ 383 void arm64_notify_segfault(unsigned long addr) 384 { 385 int code; 386 387 down_read(¤t->mm->mmap_sem); 388 if (find_vma(current->mm, addr) == NULL) 389 code = SEGV_MAPERR; 390 else 391 code = SEGV_ACCERR; 392 up_read(¤t->mm->mmap_sem); 393 394 force_signal_inject(SIGSEGV, code, addr); 395 } 396 397 void do_undefinstr(struct pt_regs *regs) 398 { 399 /* check for AArch32 breakpoint instructions */ 400 if (!aarch32_break_handler(regs)) 401 return; 402 403 if (call_undef_hook(regs) == 0) 404 return; 405 406 BUG_ON(!user_mode(regs)); 407 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 408 } 409 NOKPROBE_SYMBOL(do_undefinstr); 410 411 #define __user_cache_maint(insn, address, res) \ 412 if (address >= user_addr_max()) { \ 413 res = -EFAULT; \ 414 } else { \ 415 uaccess_ttbr0_enable(); \ 416 asm volatile ( \ 417 "1: " insn ", %1\n" \ 418 " mov %w0, #0\n" \ 419 "2:\n" \ 420 " .pushsection .fixup,\"ax\"\n" \ 421 " .align 2\n" \ 422 "3: mov %w0, %w2\n" \ 423 " b 2b\n" \ 424 " .popsection\n" \ 425 _ASM_EXTABLE(1b, 3b) \ 426 : "=r" (res) \ 427 : "r" (address), "i" (-EFAULT)); \ 428 uaccess_ttbr0_disable(); \ 429 } 430 431 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) 432 { 433 unsigned long address; 434 int rt = ESR_ELx_SYS64_ISS_RT(esr); 435 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 436 int ret = 0; 437 438 address = untagged_addr(pt_regs_read_reg(regs, rt)); 439 440 switch (crm) { 441 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ 442 __user_cache_maint("dc civac", address, ret); 443 break; 444 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ 445 __user_cache_maint("dc civac", address, ret); 446 break; 447 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ 448 __user_cache_maint("sys 3, c7, c13, 1", address, ret); 449 break; 450 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ 451 __user_cache_maint("sys 3, c7, c12, 1", address, ret); 452 break; 453 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ 454 __user_cache_maint("dc civac", address, ret); 455 break; 456 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ 457 __user_cache_maint("ic ivau", address, ret); 458 break; 459 default: 460 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 461 return; 462 } 463 464 if (ret) 465 arm64_notify_segfault(address); 466 else 467 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 468 } 469 470 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) 471 { 472 int rt = ESR_ELx_SYS64_ISS_RT(esr); 473 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); 474 475 if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { 476 /* Hide DIC so that we can trap the unnecessary maintenance...*/ 477 val &= ~BIT(CTR_DIC_SHIFT); 478 479 /* ... and fake IminLine to reduce the number of traps. */ 480 val &= ~CTR_IMINLINE_MASK; 481 val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK; 482 } 483 484 pt_regs_write_reg(regs, rt, val); 485 486 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 487 } 488 489 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 490 { 491 int rt = ESR_ELx_SYS64_ISS_RT(esr); 492 493 pt_regs_write_reg(regs, rt, arch_timer_read_counter()); 494 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 495 } 496 497 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 498 { 499 int rt = ESR_ELx_SYS64_ISS_RT(esr); 500 501 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); 502 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 503 } 504 505 static void mrs_handler(unsigned int esr, struct pt_regs *regs) 506 { 507 u32 sysreg, rt; 508 509 rt = ESR_ELx_SYS64_ISS_RT(esr); 510 sysreg = esr_sys64_to_sysreg(esr); 511 512 if (do_emulate_mrs(regs, sysreg, rt) != 0) 513 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 514 } 515 516 static void wfi_handler(unsigned int esr, struct pt_regs *regs) 517 { 518 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 519 } 520 521 struct sys64_hook { 522 unsigned int esr_mask; 523 unsigned int esr_val; 524 void (*handler)(unsigned int esr, struct pt_regs *regs); 525 }; 526 527 static const struct sys64_hook sys64_hooks[] = { 528 { 529 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, 530 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, 531 .handler = user_cache_maint_handler, 532 }, 533 { 534 /* Trap read access to CTR_EL0 */ 535 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 536 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, 537 .handler = ctr_read_handler, 538 }, 539 { 540 /* Trap read access to CNTVCT_EL0 */ 541 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 542 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, 543 .handler = cntvct_read_handler, 544 }, 545 { 546 /* Trap read access to CNTFRQ_EL0 */ 547 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 548 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, 549 .handler = cntfrq_read_handler, 550 }, 551 { 552 /* Trap read access to CPUID registers */ 553 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, 554 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, 555 .handler = mrs_handler, 556 }, 557 { 558 /* Trap WFI instructions executed in userspace */ 559 .esr_mask = ESR_ELx_WFx_MASK, 560 .esr_val = ESR_ELx_WFx_WFI_VAL, 561 .handler = wfi_handler, 562 }, 563 {}, 564 }; 565 566 567 #ifdef CONFIG_COMPAT 568 #define PSTATE_IT_1_0_SHIFT 25 569 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) 570 #define PSTATE_IT_7_2_SHIFT 10 571 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) 572 573 static u32 compat_get_it_state(struct pt_regs *regs) 574 { 575 u32 it, pstate = regs->pstate; 576 577 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; 578 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; 579 580 return it; 581 } 582 583 static void compat_set_it_state(struct pt_regs *regs, u32 it) 584 { 585 u32 pstate_it; 586 587 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; 588 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; 589 590 regs->pstate &= ~PSR_AA32_IT_MASK; 591 regs->pstate |= pstate_it; 592 } 593 594 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs) 595 { 596 int cond; 597 598 /* Only a T32 instruction can trap without CV being set */ 599 if (!(esr & ESR_ELx_CV)) { 600 u32 it; 601 602 it = compat_get_it_state(regs); 603 if (!it) 604 return true; 605 606 cond = it >> 4; 607 } else { 608 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 609 } 610 611 return aarch32_opcode_cond_checks[cond](regs->pstate); 612 } 613 614 static void advance_itstate(struct pt_regs *regs) 615 { 616 u32 it; 617 618 /* ARM mode */ 619 if (!(regs->pstate & PSR_AA32_T_BIT) || 620 !(regs->pstate & PSR_AA32_IT_MASK)) 621 return; 622 623 it = compat_get_it_state(regs); 624 625 /* 626 * If this is the last instruction of the block, wipe the IT 627 * state. Otherwise advance it. 628 */ 629 if (!(it & 7)) 630 it = 0; 631 else 632 it = (it & 0xe0) | ((it << 1) & 0x1f); 633 634 compat_set_it_state(regs, it); 635 } 636 637 static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs, 638 unsigned int sz) 639 { 640 advance_itstate(regs); 641 arm64_skip_faulting_instruction(regs, sz); 642 } 643 644 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 645 { 646 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; 647 648 pt_regs_write_reg(regs, reg, arch_timer_get_rate()); 649 arm64_compat_skip_faulting_instruction(regs, 4); 650 } 651 652 static const struct sys64_hook cp15_32_hooks[] = { 653 { 654 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, 655 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, 656 .handler = compat_cntfrq_read_handler, 657 }, 658 {}, 659 }; 660 661 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 662 { 663 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; 664 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; 665 u64 val = arch_timer_read_counter(); 666 667 pt_regs_write_reg(regs, rt, lower_32_bits(val)); 668 pt_regs_write_reg(regs, rt2, upper_32_bits(val)); 669 arm64_compat_skip_faulting_instruction(regs, 4); 670 } 671 672 static const struct sys64_hook cp15_64_hooks[] = { 673 { 674 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 675 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, 676 .handler = compat_cntvct_read_handler, 677 }, 678 {}, 679 }; 680 681 void do_cp15instr(unsigned int esr, struct pt_regs *regs) 682 { 683 const struct sys64_hook *hook, *hook_base; 684 685 if (!cp15_cond_valid(esr, regs)) { 686 /* 687 * There is no T16 variant of a CP access, so we 688 * always advance PC by 4 bytes. 689 */ 690 arm64_compat_skip_faulting_instruction(regs, 4); 691 return; 692 } 693 694 switch (ESR_ELx_EC(esr)) { 695 case ESR_ELx_EC_CP15_32: 696 hook_base = cp15_32_hooks; 697 break; 698 case ESR_ELx_EC_CP15_64: 699 hook_base = cp15_64_hooks; 700 break; 701 default: 702 do_undefinstr(regs); 703 return; 704 } 705 706 for (hook = hook_base; hook->handler; hook++) 707 if ((hook->esr_mask & esr) == hook->esr_val) { 708 hook->handler(esr, regs); 709 return; 710 } 711 712 /* 713 * New cp15 instructions may previously have been undefined at 714 * EL0. Fall back to our usual undefined instruction handler 715 * so that we handle these consistently. 716 */ 717 do_undefinstr(regs); 718 } 719 NOKPROBE_SYMBOL(do_cp15instr); 720 #endif 721 722 void do_sysinstr(unsigned int esr, struct pt_regs *regs) 723 { 724 const struct sys64_hook *hook; 725 726 for (hook = sys64_hooks; hook->handler; hook++) 727 if ((hook->esr_mask & esr) == hook->esr_val) { 728 hook->handler(esr, regs); 729 return; 730 } 731 732 /* 733 * New SYS instructions may previously have been undefined at EL0. Fall 734 * back to our usual undefined instruction handler so that we handle 735 * these consistently. 736 */ 737 do_undefinstr(regs); 738 } 739 NOKPROBE_SYMBOL(do_sysinstr); 740 741 static const char *esr_class_str[] = { 742 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", 743 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", 744 [ESR_ELx_EC_WFx] = "WFI/WFE", 745 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", 746 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", 747 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", 748 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", 749 [ESR_ELx_EC_FP_ASIMD] = "ASIMD", 750 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", 751 [ESR_ELx_EC_PAC] = "PAC", 752 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", 753 [ESR_ELx_EC_ILL] = "PSTATE.IL", 754 [ESR_ELx_EC_SVC32] = "SVC (AArch32)", 755 [ESR_ELx_EC_HVC32] = "HVC (AArch32)", 756 [ESR_ELx_EC_SMC32] = "SMC (AArch32)", 757 [ESR_ELx_EC_SVC64] = "SVC (AArch64)", 758 [ESR_ELx_EC_HVC64] = "HVC (AArch64)", 759 [ESR_ELx_EC_SMC64] = "SMC (AArch64)", 760 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", 761 [ESR_ELx_EC_SVE] = "SVE", 762 [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", 763 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", 764 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", 765 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", 766 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment", 767 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", 768 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", 769 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment", 770 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", 771 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", 772 [ESR_ELx_EC_SERROR] = "SError", 773 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", 774 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", 775 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", 776 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", 777 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", 778 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", 779 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", 780 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", 781 [ESR_ELx_EC_BRK64] = "BRK (AArch64)", 782 }; 783 784 const char *esr_get_class_string(u32 esr) 785 { 786 return esr_class_str[ESR_ELx_EC(esr)]; 787 } 788 789 /* 790 * bad_mode handles the impossible case in the exception vector. This is always 791 * fatal. 792 */ 793 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr) 794 { 795 console_verbose(); 796 797 pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n", 798 handler[reason], smp_processor_id(), esr, 799 esr_get_class_string(esr)); 800 801 local_daif_mask(); 802 panic("bad mode"); 803 } 804 805 /* 806 * bad_el0_sync handles unexpected, but potentially recoverable synchronous 807 * exceptions taken from EL0. Unlike bad_mode, this returns. 808 */ 809 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr) 810 { 811 void __user *pc = (void __user *)instruction_pointer(regs); 812 813 current->thread.fault_address = 0; 814 current->thread.fault_code = esr; 815 816 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, 817 "Bad EL0 synchronous exception"); 818 } 819 820 #ifdef CONFIG_VMAP_STACK 821 822 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) 823 __aligned(16); 824 825 asmlinkage void handle_bad_stack(struct pt_regs *regs) 826 { 827 unsigned long tsk_stk = (unsigned long)current->stack; 828 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); 829 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); 830 unsigned int esr = read_sysreg(esr_el1); 831 unsigned long far = read_sysreg(far_el1); 832 833 console_verbose(); 834 pr_emerg("Insufficient stack space to handle exception!"); 835 836 pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr)); 837 pr_emerg("FAR: 0x%016lx\n", far); 838 839 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", 840 tsk_stk, tsk_stk + THREAD_SIZE); 841 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", 842 irq_stk, irq_stk + THREAD_SIZE); 843 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", 844 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); 845 846 __show_regs(regs); 847 848 /* 849 * We use nmi_panic to limit the potential for recusive overflows, and 850 * to get a better stack trace. 851 */ 852 nmi_panic(NULL, "kernel stack overflow"); 853 cpu_park_loop(); 854 } 855 #endif 856 857 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr) 858 { 859 console_verbose(); 860 861 pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n", 862 smp_processor_id(), esr, esr_get_class_string(esr)); 863 if (regs) 864 __show_regs(regs); 865 866 nmi_panic(regs, "Asynchronous SError Interrupt"); 867 868 cpu_park_loop(); 869 unreachable(); 870 } 871 872 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr) 873 { 874 u32 aet = arm64_ras_serror_get_severity(esr); 875 876 switch (aet) { 877 case ESR_ELx_AET_CE: /* corrected error */ 878 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ 879 /* 880 * The CPU can make progress. We may take UEO again as 881 * a more severe error. 882 */ 883 return false; 884 885 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ 886 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ 887 /* 888 * The CPU can't make progress. The exception may have 889 * been imprecise. 890 * 891 * Neoverse-N1 #1349291 means a non-KVM SError reported as 892 * Unrecoverable should be treated as Uncontainable. We 893 * call arm64_serror_panic() in both cases. 894 */ 895 return true; 896 897 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ 898 default: 899 /* Error has been silently propagated */ 900 arm64_serror_panic(regs, esr); 901 } 902 } 903 904 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr) 905 { 906 const bool was_in_nmi = in_nmi(); 907 908 if (!was_in_nmi) 909 nmi_enter(); 910 911 /* non-RAS errors are not containable */ 912 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) 913 arm64_serror_panic(regs, esr); 914 915 if (!was_in_nmi) 916 nmi_exit(); 917 } 918 919 asmlinkage void enter_from_user_mode(void) 920 { 921 CT_WARN_ON(ct_state() != CONTEXT_USER); 922 user_exit_irqoff(); 923 } 924 NOKPROBE_SYMBOL(enter_from_user_mode); 925 926 void __pte_error(const char *file, int line, unsigned long val) 927 { 928 pr_err("%s:%d: bad pte %016lx.\n", file, line, val); 929 } 930 931 void __pmd_error(const char *file, int line, unsigned long val) 932 { 933 pr_err("%s:%d: bad pmd %016lx.\n", file, line, val); 934 } 935 936 void __pud_error(const char *file, int line, unsigned long val) 937 { 938 pr_err("%s:%d: bad pud %016lx.\n", file, line, val); 939 } 940 941 void __pgd_error(const char *file, int line, unsigned long val) 942 { 943 pr_err("%s:%d: bad pgd %016lx.\n", file, line, val); 944 } 945 946 /* GENERIC_BUG traps */ 947 948 int is_valid_bugaddr(unsigned long addr) 949 { 950 /* 951 * bug_handler() only called for BRK #BUG_BRK_IMM. 952 * So the answer is trivial -- any spurious instances with no 953 * bug table entry will be rejected by report_bug() and passed 954 * back to the debug-monitors code and handled as a fatal 955 * unexpected debug exception. 956 */ 957 return 1; 958 } 959 960 static int bug_handler(struct pt_regs *regs, unsigned int esr) 961 { 962 switch (report_bug(regs->pc, regs)) { 963 case BUG_TRAP_TYPE_BUG: 964 die("Oops - BUG", regs, 0); 965 break; 966 967 case BUG_TRAP_TYPE_WARN: 968 break; 969 970 default: 971 /* unknown/unrecognised bug trap type */ 972 return DBG_HOOK_ERROR; 973 } 974 975 /* If thread survives, skip over the BUG instruction and continue: */ 976 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 977 return DBG_HOOK_HANDLED; 978 } 979 980 static struct break_hook bug_break_hook = { 981 .fn = bug_handler, 982 .imm = BUG_BRK_IMM, 983 }; 984 985 #ifdef CONFIG_KASAN_SW_TAGS 986 987 #define KASAN_ESR_RECOVER 0x20 988 #define KASAN_ESR_WRITE 0x10 989 #define KASAN_ESR_SIZE_MASK 0x0f 990 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) 991 992 static int kasan_handler(struct pt_regs *regs, unsigned int esr) 993 { 994 bool recover = esr & KASAN_ESR_RECOVER; 995 bool write = esr & KASAN_ESR_WRITE; 996 size_t size = KASAN_ESR_SIZE(esr); 997 u64 addr = regs->regs[0]; 998 u64 pc = regs->pc; 999 1000 kasan_report(addr, size, write, pc); 1001 1002 /* 1003 * The instrumentation allows to control whether we can proceed after 1004 * a crash was detected. This is done by passing the -recover flag to 1005 * the compiler. Disabling recovery allows to generate more compact 1006 * code. 1007 * 1008 * Unfortunately disabling recovery doesn't work for the kernel right 1009 * now. KASAN reporting is disabled in some contexts (for example when 1010 * the allocator accesses slab object metadata; this is controlled by 1011 * current->kasan_depth). All these accesses are detected by the tool, 1012 * even though the reports for them are not printed. 1013 * 1014 * This is something that might be fixed at some point in the future. 1015 */ 1016 if (!recover) 1017 die("Oops - KASAN", regs, 0); 1018 1019 /* If thread survives, skip over the brk instruction and continue: */ 1020 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1021 return DBG_HOOK_HANDLED; 1022 } 1023 1024 static struct break_hook kasan_break_hook = { 1025 .fn = kasan_handler, 1026 .imm = KASAN_BRK_IMM, 1027 .mask = KASAN_BRK_MASK, 1028 }; 1029 #endif 1030 1031 /* 1032 * Initial handler for AArch64 BRK exceptions 1033 * This handler only used until debug_traps_init(). 1034 */ 1035 int __init early_brk64(unsigned long addr, unsigned int esr, 1036 struct pt_regs *regs) 1037 { 1038 #ifdef CONFIG_KASAN_SW_TAGS 1039 unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; 1040 1041 if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM) 1042 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; 1043 #endif 1044 return bug_handler(regs, esr) != DBG_HOOK_HANDLED; 1045 } 1046 1047 /* This registration must happen early, before debug_traps_init(). */ 1048 void __init trap_init(void) 1049 { 1050 register_kernel_break_hook(&bug_break_hook); 1051 #ifdef CONFIG_KASAN_SW_TAGS 1052 register_kernel_break_hook(&kasan_break_hook); 1053 #endif 1054 } 1055