1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/traps.c 4 * 5 * Copyright (C) 1995-2009 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 9 #include <linux/bug.h> 10 #include <linux/context_tracking.h> 11 #include <linux/signal.h> 12 #include <linux/personality.h> 13 #include <linux/kallsyms.h> 14 #include <linux/kprobes.h> 15 #include <linux/spinlock.h> 16 #include <linux/uaccess.h> 17 #include <linux/hardirq.h> 18 #include <linux/kdebug.h> 19 #include <linux/module.h> 20 #include <linux/kexec.h> 21 #include <linux/delay.h> 22 #include <linux/init.h> 23 #include <linux/sched/signal.h> 24 #include <linux/sched/debug.h> 25 #include <linux/sched/task_stack.h> 26 #include <linux/sizes.h> 27 #include <linux/syscalls.h> 28 #include <linux/mm_types.h> 29 #include <linux/kasan.h> 30 31 #include <asm/atomic.h> 32 #include <asm/bug.h> 33 #include <asm/cpufeature.h> 34 #include <asm/daifflags.h> 35 #include <asm/debug-monitors.h> 36 #include <asm/esr.h> 37 #include <asm/exception.h> 38 #include <asm/extable.h> 39 #include <asm/insn.h> 40 #include <asm/kprobes.h> 41 #include <asm/patching.h> 42 #include <asm/traps.h> 43 #include <asm/smp.h> 44 #include <asm/stack_pointer.h> 45 #include <asm/stacktrace.h> 46 #include <asm/system_misc.h> 47 #include <asm/sysreg.h> 48 49 static bool __kprobes __check_eq(unsigned long pstate) 50 { 51 return (pstate & PSR_Z_BIT) != 0; 52 } 53 54 static bool __kprobes __check_ne(unsigned long pstate) 55 { 56 return (pstate & PSR_Z_BIT) == 0; 57 } 58 59 static bool __kprobes __check_cs(unsigned long pstate) 60 { 61 return (pstate & PSR_C_BIT) != 0; 62 } 63 64 static bool __kprobes __check_cc(unsigned long pstate) 65 { 66 return (pstate & PSR_C_BIT) == 0; 67 } 68 69 static bool __kprobes __check_mi(unsigned long pstate) 70 { 71 return (pstate & PSR_N_BIT) != 0; 72 } 73 74 static bool __kprobes __check_pl(unsigned long pstate) 75 { 76 return (pstate & PSR_N_BIT) == 0; 77 } 78 79 static bool __kprobes __check_vs(unsigned long pstate) 80 { 81 return (pstate & PSR_V_BIT) != 0; 82 } 83 84 static bool __kprobes __check_vc(unsigned long pstate) 85 { 86 return (pstate & PSR_V_BIT) == 0; 87 } 88 89 static bool __kprobes __check_hi(unsigned long pstate) 90 { 91 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 92 return (pstate & PSR_C_BIT) != 0; 93 } 94 95 static bool __kprobes __check_ls(unsigned long pstate) 96 { 97 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 98 return (pstate & PSR_C_BIT) == 0; 99 } 100 101 static bool __kprobes __check_ge(unsigned long pstate) 102 { 103 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 104 return (pstate & PSR_N_BIT) == 0; 105 } 106 107 static bool __kprobes __check_lt(unsigned long pstate) 108 { 109 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 110 return (pstate & PSR_N_BIT) != 0; 111 } 112 113 static bool __kprobes __check_gt(unsigned long pstate) 114 { 115 /*PSR_N_BIT ^= PSR_V_BIT */ 116 unsigned long temp = pstate ^ (pstate << 3); 117 118 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 119 return (temp & PSR_N_BIT) == 0; 120 } 121 122 static bool __kprobes __check_le(unsigned long pstate) 123 { 124 /*PSR_N_BIT ^= PSR_V_BIT */ 125 unsigned long temp = pstate ^ (pstate << 3); 126 127 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 128 return (temp & PSR_N_BIT) != 0; 129 } 130 131 static bool __kprobes __check_al(unsigned long pstate) 132 { 133 return true; 134 } 135 136 /* 137 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that 138 * it behaves identically to 0b1110 ("al"). 139 */ 140 pstate_check_t * const aarch32_opcode_cond_checks[16] = { 141 __check_eq, __check_ne, __check_cs, __check_cc, 142 __check_mi, __check_pl, __check_vs, __check_vc, 143 __check_hi, __check_ls, __check_ge, __check_lt, 144 __check_gt, __check_le, __check_al, __check_al 145 }; 146 147 int show_unhandled_signals = 0; 148 149 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) 150 { 151 unsigned long addr = instruction_pointer(regs); 152 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 153 int i; 154 155 if (user_mode(regs)) 156 return; 157 158 for (i = -4; i < 1; i++) { 159 unsigned int val, bad; 160 161 bad = aarch64_insn_read(&((u32 *)addr)[i], &val); 162 163 if (!bad) 164 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); 165 else { 166 p += sprintf(p, "bad PC value"); 167 break; 168 } 169 } 170 171 printk("%sCode: %s\n", lvl, str); 172 } 173 174 #ifdef CONFIG_PREEMPT 175 #define S_PREEMPT " PREEMPT" 176 #elif defined(CONFIG_PREEMPT_RT) 177 #define S_PREEMPT " PREEMPT_RT" 178 #else 179 #define S_PREEMPT "" 180 #endif 181 182 #define S_SMP " SMP" 183 184 static int __die(const char *str, int err, struct pt_regs *regs) 185 { 186 static int die_counter; 187 int ret; 188 189 pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", 190 str, err, ++die_counter); 191 192 /* trap and error numbers are mostly meaningless on ARM */ 193 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); 194 if (ret == NOTIFY_STOP) 195 return ret; 196 197 print_modules(); 198 show_regs(regs); 199 200 dump_kernel_instr(KERN_EMERG, regs); 201 202 return ret; 203 } 204 205 static DEFINE_RAW_SPINLOCK(die_lock); 206 207 /* 208 * This function is protected against re-entrancy. 209 */ 210 void die(const char *str, struct pt_regs *regs, int err) 211 { 212 int ret; 213 unsigned long flags; 214 215 raw_spin_lock_irqsave(&die_lock, flags); 216 217 oops_enter(); 218 219 console_verbose(); 220 bust_spinlocks(1); 221 ret = __die(str, err, regs); 222 223 if (regs && kexec_should_crash(current)) 224 crash_kexec(regs); 225 226 bust_spinlocks(0); 227 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 228 oops_exit(); 229 230 if (in_interrupt()) 231 panic("%s: Fatal exception in interrupt", str); 232 if (panic_on_oops) 233 panic("%s: Fatal exception", str); 234 235 raw_spin_unlock_irqrestore(&die_lock, flags); 236 237 if (ret != NOTIFY_STOP) 238 make_task_dead(SIGSEGV); 239 } 240 241 static void arm64_show_signal(int signo, const char *str) 242 { 243 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 244 DEFAULT_RATELIMIT_BURST); 245 struct task_struct *tsk = current; 246 unsigned int esr = tsk->thread.fault_code; 247 struct pt_regs *regs = task_pt_regs(tsk); 248 249 /* Leave if the signal won't be shown */ 250 if (!show_unhandled_signals || 251 !unhandled_signal(tsk, signo) || 252 !__ratelimit(&rs)) 253 return; 254 255 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); 256 if (esr) 257 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr); 258 259 pr_cont("%s", str); 260 print_vma_addr(KERN_CONT " in ", regs->pc); 261 pr_cont("\n"); 262 __show_regs(regs); 263 } 264 265 void arm64_force_sig_fault(int signo, int code, unsigned long far, 266 const char *str) 267 { 268 arm64_show_signal(signo, str); 269 if (signo == SIGKILL) 270 force_sig(SIGKILL); 271 else 272 force_sig_fault(signo, code, (void __user *)far); 273 } 274 275 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, 276 const char *str) 277 { 278 arm64_show_signal(SIGBUS, str); 279 force_sig_mceerr(code, (void __user *)far, lsb); 280 } 281 282 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, 283 const char *str) 284 { 285 arm64_show_signal(SIGTRAP, str); 286 force_sig_ptrace_errno_trap(errno, (void __user *)far); 287 } 288 289 void arm64_notify_die(const char *str, struct pt_regs *regs, 290 int signo, int sicode, unsigned long far, 291 int err) 292 { 293 if (user_mode(regs)) { 294 WARN_ON(regs != current_pt_regs()); 295 current->thread.fault_address = 0; 296 current->thread.fault_code = err; 297 298 arm64_force_sig_fault(signo, sicode, far, str); 299 } else { 300 die(str, regs, err); 301 } 302 } 303 304 #ifdef CONFIG_COMPAT 305 #define PSTATE_IT_1_0_SHIFT 25 306 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) 307 #define PSTATE_IT_7_2_SHIFT 10 308 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) 309 310 static u32 compat_get_it_state(struct pt_regs *regs) 311 { 312 u32 it, pstate = regs->pstate; 313 314 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; 315 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; 316 317 return it; 318 } 319 320 static void compat_set_it_state(struct pt_regs *regs, u32 it) 321 { 322 u32 pstate_it; 323 324 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; 325 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; 326 327 regs->pstate &= ~PSR_AA32_IT_MASK; 328 regs->pstate |= pstate_it; 329 } 330 331 static void advance_itstate(struct pt_regs *regs) 332 { 333 u32 it; 334 335 /* ARM mode */ 336 if (!(regs->pstate & PSR_AA32_T_BIT) || 337 !(regs->pstate & PSR_AA32_IT_MASK)) 338 return; 339 340 it = compat_get_it_state(regs); 341 342 /* 343 * If this is the last instruction of the block, wipe the IT 344 * state. Otherwise advance it. 345 */ 346 if (!(it & 7)) 347 it = 0; 348 else 349 it = (it & 0xe0) | ((it << 1) & 0x1f); 350 351 compat_set_it_state(regs, it); 352 } 353 #else 354 static void advance_itstate(struct pt_regs *regs) 355 { 356 } 357 #endif 358 359 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) 360 { 361 regs->pc += size; 362 363 /* 364 * If we were single stepping, we want to get the step exception after 365 * we return from the trap. 366 */ 367 if (user_mode(regs)) 368 user_fastforward_single_step(current); 369 370 if (compat_user_mode(regs)) 371 advance_itstate(regs); 372 else 373 regs->pstate &= ~PSR_BTYPE_MASK; 374 } 375 376 static LIST_HEAD(undef_hook); 377 static DEFINE_RAW_SPINLOCK(undef_lock); 378 379 void register_undef_hook(struct undef_hook *hook) 380 { 381 unsigned long flags; 382 383 raw_spin_lock_irqsave(&undef_lock, flags); 384 list_add(&hook->node, &undef_hook); 385 raw_spin_unlock_irqrestore(&undef_lock, flags); 386 } 387 388 void unregister_undef_hook(struct undef_hook *hook) 389 { 390 unsigned long flags; 391 392 raw_spin_lock_irqsave(&undef_lock, flags); 393 list_del(&hook->node); 394 raw_spin_unlock_irqrestore(&undef_lock, flags); 395 } 396 397 static int call_undef_hook(struct pt_regs *regs) 398 { 399 struct undef_hook *hook; 400 unsigned long flags; 401 u32 instr; 402 int (*fn)(struct pt_regs *regs, u32 instr) = NULL; 403 unsigned long pc = instruction_pointer(regs); 404 405 if (!user_mode(regs)) { 406 __le32 instr_le; 407 if (get_kernel_nofault(instr_le, (__le32 *)pc)) 408 goto exit; 409 instr = le32_to_cpu(instr_le); 410 } else if (compat_thumb_mode(regs)) { 411 /* 16-bit Thumb instruction */ 412 __le16 instr_le; 413 if (get_user(instr_le, (__le16 __user *)pc)) 414 goto exit; 415 instr = le16_to_cpu(instr_le); 416 if (aarch32_insn_is_wide(instr)) { 417 u32 instr2; 418 419 if (get_user(instr_le, (__le16 __user *)(pc + 2))) 420 goto exit; 421 instr2 = le16_to_cpu(instr_le); 422 instr = (instr << 16) | instr2; 423 } 424 } else { 425 /* 32-bit ARM instruction */ 426 __le32 instr_le; 427 if (get_user(instr_le, (__le32 __user *)pc)) 428 goto exit; 429 instr = le32_to_cpu(instr_le); 430 } 431 432 raw_spin_lock_irqsave(&undef_lock, flags); 433 list_for_each_entry(hook, &undef_hook, node) 434 if ((instr & hook->instr_mask) == hook->instr_val && 435 (regs->pstate & hook->pstate_mask) == hook->pstate_val) 436 fn = hook->fn; 437 438 raw_spin_unlock_irqrestore(&undef_lock, flags); 439 exit: 440 return fn ? fn(regs, instr) : 1; 441 } 442 443 void force_signal_inject(int signal, int code, unsigned long address, unsigned int err) 444 { 445 const char *desc; 446 struct pt_regs *regs = current_pt_regs(); 447 448 if (WARN_ON(!user_mode(regs))) 449 return; 450 451 switch (signal) { 452 case SIGILL: 453 desc = "undefined instruction"; 454 break; 455 case SIGSEGV: 456 desc = "illegal memory access"; 457 break; 458 default: 459 desc = "unknown or unrecoverable error"; 460 break; 461 } 462 463 /* Force signals we don't understand to SIGKILL */ 464 if (WARN_ON(signal != SIGKILL && 465 siginfo_layout(signal, code) != SIL_FAULT)) { 466 signal = SIGKILL; 467 } 468 469 arm64_notify_die(desc, regs, signal, code, address, err); 470 } 471 472 /* 473 * Set up process info to signal segmentation fault - called on access error. 474 */ 475 void arm64_notify_segfault(unsigned long addr) 476 { 477 int code; 478 479 mmap_read_lock(current->mm); 480 if (find_vma(current->mm, untagged_addr(addr)) == NULL) 481 code = SEGV_MAPERR; 482 else 483 code = SEGV_ACCERR; 484 mmap_read_unlock(current->mm); 485 486 force_signal_inject(SIGSEGV, code, addr, 0); 487 } 488 489 void do_undefinstr(struct pt_regs *regs) 490 { 491 /* check for AArch32 breakpoint instructions */ 492 if (!aarch32_break_handler(regs)) 493 return; 494 495 if (call_undef_hook(regs) == 0) 496 return; 497 498 BUG_ON(!user_mode(regs)); 499 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 500 } 501 NOKPROBE_SYMBOL(do_undefinstr); 502 503 void do_bti(struct pt_regs *regs) 504 { 505 BUG_ON(!user_mode(regs)); 506 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 507 } 508 NOKPROBE_SYMBOL(do_bti); 509 510 void do_ptrauth_fault(struct pt_regs *regs, unsigned int esr) 511 { 512 /* 513 * Unexpected FPAC exception or pointer authentication failure in 514 * the kernel: kill the task before it does any more harm. 515 */ 516 BUG_ON(!user_mode(regs)); 517 force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr); 518 } 519 NOKPROBE_SYMBOL(do_ptrauth_fault); 520 521 #define __user_cache_maint(insn, address, res) \ 522 if (address >= user_addr_max()) { \ 523 res = -EFAULT; \ 524 } else { \ 525 uaccess_ttbr0_enable(); \ 526 asm volatile ( \ 527 "1: " insn ", %1\n" \ 528 " mov %w0, #0\n" \ 529 "2:\n" \ 530 _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) \ 531 : "=r" (res) \ 532 : "r" (address)); \ 533 uaccess_ttbr0_disable(); \ 534 } 535 536 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) 537 { 538 unsigned long tagged_address, address; 539 int rt = ESR_ELx_SYS64_ISS_RT(esr); 540 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 541 int ret = 0; 542 543 tagged_address = pt_regs_read_reg(regs, rt); 544 address = untagged_addr(tagged_address); 545 546 switch (crm) { 547 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ 548 __user_cache_maint("dc civac", address, ret); 549 break; 550 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ 551 __user_cache_maint("dc civac", address, ret); 552 break; 553 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ 554 __user_cache_maint("sys 3, c7, c13, 1", address, ret); 555 break; 556 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ 557 __user_cache_maint("sys 3, c7, c12, 1", address, ret); 558 break; 559 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ 560 __user_cache_maint("dc civac", address, ret); 561 break; 562 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ 563 __user_cache_maint("ic ivau", address, ret); 564 break; 565 default: 566 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 567 return; 568 } 569 570 if (ret) 571 arm64_notify_segfault(tagged_address); 572 else 573 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 574 } 575 576 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) 577 { 578 int rt = ESR_ELx_SYS64_ISS_RT(esr); 579 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); 580 581 if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { 582 /* Hide DIC so that we can trap the unnecessary maintenance...*/ 583 val &= ~BIT(CTR_DIC_SHIFT); 584 585 /* ... and fake IminLine to reduce the number of traps. */ 586 val &= ~CTR_IMINLINE_MASK; 587 val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK; 588 } 589 590 pt_regs_write_reg(regs, rt, val); 591 592 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 593 } 594 595 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 596 { 597 int rt = ESR_ELx_SYS64_ISS_RT(esr); 598 599 pt_regs_write_reg(regs, rt, arch_timer_read_counter()); 600 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 601 } 602 603 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 604 { 605 int rt = ESR_ELx_SYS64_ISS_RT(esr); 606 607 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); 608 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 609 } 610 611 static void mrs_handler(unsigned int esr, struct pt_regs *regs) 612 { 613 u32 sysreg, rt; 614 615 rt = ESR_ELx_SYS64_ISS_RT(esr); 616 sysreg = esr_sys64_to_sysreg(esr); 617 618 if (do_emulate_mrs(regs, sysreg, rt) != 0) 619 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 620 } 621 622 static void wfi_handler(unsigned int esr, struct pt_regs *regs) 623 { 624 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 625 } 626 627 struct sys64_hook { 628 unsigned int esr_mask; 629 unsigned int esr_val; 630 void (*handler)(unsigned int esr, struct pt_regs *regs); 631 }; 632 633 static const struct sys64_hook sys64_hooks[] = { 634 { 635 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, 636 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, 637 .handler = user_cache_maint_handler, 638 }, 639 { 640 /* Trap read access to CTR_EL0 */ 641 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 642 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, 643 .handler = ctr_read_handler, 644 }, 645 { 646 /* Trap read access to CNTVCT_EL0 */ 647 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 648 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, 649 .handler = cntvct_read_handler, 650 }, 651 { 652 /* Trap read access to CNTVCTSS_EL0 */ 653 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 654 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS, 655 .handler = cntvct_read_handler, 656 }, 657 { 658 /* Trap read access to CNTFRQ_EL0 */ 659 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 660 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, 661 .handler = cntfrq_read_handler, 662 }, 663 { 664 /* Trap read access to CPUID registers */ 665 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, 666 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, 667 .handler = mrs_handler, 668 }, 669 { 670 /* Trap WFI instructions executed in userspace */ 671 .esr_mask = ESR_ELx_WFx_MASK, 672 .esr_val = ESR_ELx_WFx_WFI_VAL, 673 .handler = wfi_handler, 674 }, 675 {}, 676 }; 677 678 #ifdef CONFIG_COMPAT 679 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs) 680 { 681 int cond; 682 683 /* Only a T32 instruction can trap without CV being set */ 684 if (!(esr & ESR_ELx_CV)) { 685 u32 it; 686 687 it = compat_get_it_state(regs); 688 if (!it) 689 return true; 690 691 cond = it >> 4; 692 } else { 693 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 694 } 695 696 return aarch32_opcode_cond_checks[cond](regs->pstate); 697 } 698 699 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 700 { 701 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; 702 703 pt_regs_write_reg(regs, reg, arch_timer_get_rate()); 704 arm64_skip_faulting_instruction(regs, 4); 705 } 706 707 static const struct sys64_hook cp15_32_hooks[] = { 708 { 709 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, 710 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, 711 .handler = compat_cntfrq_read_handler, 712 }, 713 {}, 714 }; 715 716 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 717 { 718 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; 719 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; 720 u64 val = arch_timer_read_counter(); 721 722 pt_regs_write_reg(regs, rt, lower_32_bits(val)); 723 pt_regs_write_reg(regs, rt2, upper_32_bits(val)); 724 arm64_skip_faulting_instruction(regs, 4); 725 } 726 727 static const struct sys64_hook cp15_64_hooks[] = { 728 { 729 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 730 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, 731 .handler = compat_cntvct_read_handler, 732 }, 733 { 734 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 735 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS, 736 .handler = compat_cntvct_read_handler, 737 }, 738 {}, 739 }; 740 741 void do_cp15instr(unsigned int esr, struct pt_regs *regs) 742 { 743 const struct sys64_hook *hook, *hook_base; 744 745 if (!cp15_cond_valid(esr, regs)) { 746 /* 747 * There is no T16 variant of a CP access, so we 748 * always advance PC by 4 bytes. 749 */ 750 arm64_skip_faulting_instruction(regs, 4); 751 return; 752 } 753 754 switch (ESR_ELx_EC(esr)) { 755 case ESR_ELx_EC_CP15_32: 756 hook_base = cp15_32_hooks; 757 break; 758 case ESR_ELx_EC_CP15_64: 759 hook_base = cp15_64_hooks; 760 break; 761 default: 762 do_undefinstr(regs); 763 return; 764 } 765 766 for (hook = hook_base; hook->handler; hook++) 767 if ((hook->esr_mask & esr) == hook->esr_val) { 768 hook->handler(esr, regs); 769 return; 770 } 771 772 /* 773 * New cp15 instructions may previously have been undefined at 774 * EL0. Fall back to our usual undefined instruction handler 775 * so that we handle these consistently. 776 */ 777 do_undefinstr(regs); 778 } 779 NOKPROBE_SYMBOL(do_cp15instr); 780 #endif 781 782 void do_sysinstr(unsigned int esr, struct pt_regs *regs) 783 { 784 const struct sys64_hook *hook; 785 786 for (hook = sys64_hooks; hook->handler; hook++) 787 if ((hook->esr_mask & esr) == hook->esr_val) { 788 hook->handler(esr, regs); 789 return; 790 } 791 792 /* 793 * New SYS instructions may previously have been undefined at EL0. Fall 794 * back to our usual undefined instruction handler so that we handle 795 * these consistently. 796 */ 797 do_undefinstr(regs); 798 } 799 NOKPROBE_SYMBOL(do_sysinstr); 800 801 static const char *esr_class_str[] = { 802 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", 803 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", 804 [ESR_ELx_EC_WFx] = "WFI/WFE", 805 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", 806 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", 807 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", 808 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", 809 [ESR_ELx_EC_FP_ASIMD] = "ASIMD", 810 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", 811 [ESR_ELx_EC_PAC] = "PAC", 812 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", 813 [ESR_ELx_EC_BTI] = "BTI", 814 [ESR_ELx_EC_ILL] = "PSTATE.IL", 815 [ESR_ELx_EC_SVC32] = "SVC (AArch32)", 816 [ESR_ELx_EC_HVC32] = "HVC (AArch32)", 817 [ESR_ELx_EC_SMC32] = "SMC (AArch32)", 818 [ESR_ELx_EC_SVC64] = "SVC (AArch64)", 819 [ESR_ELx_EC_HVC64] = "HVC (AArch64)", 820 [ESR_ELx_EC_SMC64] = "SMC (AArch64)", 821 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", 822 [ESR_ELx_EC_SVE] = "SVE", 823 [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", 824 [ESR_ELx_EC_FPAC] = "FPAC", 825 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", 826 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", 827 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", 828 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment", 829 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", 830 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", 831 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment", 832 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", 833 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", 834 [ESR_ELx_EC_SERROR] = "SError", 835 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", 836 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", 837 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", 838 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", 839 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", 840 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", 841 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", 842 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", 843 [ESR_ELx_EC_BRK64] = "BRK (AArch64)", 844 }; 845 846 const char *esr_get_class_string(u32 esr) 847 { 848 return esr_class_str[ESR_ELx_EC(esr)]; 849 } 850 851 /* 852 * bad_el0_sync handles unexpected, but potentially recoverable synchronous 853 * exceptions taken from EL0. 854 */ 855 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr) 856 { 857 unsigned long pc = instruction_pointer(regs); 858 859 current->thread.fault_address = 0; 860 current->thread.fault_code = esr; 861 862 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, 863 "Bad EL0 synchronous exception"); 864 } 865 866 #ifdef CONFIG_VMAP_STACK 867 868 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) 869 __aligned(16); 870 871 void panic_bad_stack(struct pt_regs *regs, unsigned int esr, unsigned long far) 872 { 873 unsigned long tsk_stk = (unsigned long)current->stack; 874 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); 875 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); 876 877 console_verbose(); 878 pr_emerg("Insufficient stack space to handle exception!"); 879 880 pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr)); 881 pr_emerg("FAR: 0x%016lx\n", far); 882 883 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", 884 tsk_stk, tsk_stk + THREAD_SIZE); 885 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", 886 irq_stk, irq_stk + IRQ_STACK_SIZE); 887 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", 888 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); 889 890 __show_regs(regs); 891 892 /* 893 * We use nmi_panic to limit the potential for recusive overflows, and 894 * to get a better stack trace. 895 */ 896 nmi_panic(NULL, "kernel stack overflow"); 897 cpu_park_loop(); 898 } 899 #endif 900 901 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr) 902 { 903 console_verbose(); 904 905 pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n", 906 smp_processor_id(), esr, esr_get_class_string(esr)); 907 if (regs) 908 __show_regs(regs); 909 910 nmi_panic(regs, "Asynchronous SError Interrupt"); 911 912 cpu_park_loop(); 913 unreachable(); 914 } 915 916 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr) 917 { 918 u32 aet = arm64_ras_serror_get_severity(esr); 919 920 switch (aet) { 921 case ESR_ELx_AET_CE: /* corrected error */ 922 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ 923 /* 924 * The CPU can make progress. We may take UEO again as 925 * a more severe error. 926 */ 927 return false; 928 929 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ 930 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ 931 /* 932 * The CPU can't make progress. The exception may have 933 * been imprecise. 934 * 935 * Neoverse-N1 #1349291 means a non-KVM SError reported as 936 * Unrecoverable should be treated as Uncontainable. We 937 * call arm64_serror_panic() in both cases. 938 */ 939 return true; 940 941 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ 942 default: 943 /* Error has been silently propagated */ 944 arm64_serror_panic(regs, esr); 945 } 946 } 947 948 void do_serror(struct pt_regs *regs, unsigned int esr) 949 { 950 /* non-RAS errors are not containable */ 951 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) 952 arm64_serror_panic(regs, esr); 953 } 954 955 /* GENERIC_BUG traps */ 956 957 int is_valid_bugaddr(unsigned long addr) 958 { 959 /* 960 * bug_handler() only called for BRK #BUG_BRK_IMM. 961 * So the answer is trivial -- any spurious instances with no 962 * bug table entry will be rejected by report_bug() and passed 963 * back to the debug-monitors code and handled as a fatal 964 * unexpected debug exception. 965 */ 966 return 1; 967 } 968 969 static int bug_handler(struct pt_regs *regs, unsigned int esr) 970 { 971 switch (report_bug(regs->pc, regs)) { 972 case BUG_TRAP_TYPE_BUG: 973 die("Oops - BUG", regs, 0); 974 break; 975 976 case BUG_TRAP_TYPE_WARN: 977 break; 978 979 default: 980 /* unknown/unrecognised bug trap type */ 981 return DBG_HOOK_ERROR; 982 } 983 984 /* If thread survives, skip over the BUG instruction and continue: */ 985 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 986 return DBG_HOOK_HANDLED; 987 } 988 989 static struct break_hook bug_break_hook = { 990 .fn = bug_handler, 991 .imm = BUG_BRK_IMM, 992 }; 993 994 static int reserved_fault_handler(struct pt_regs *regs, unsigned int esr) 995 { 996 pr_err("%s generated an invalid instruction at %pS!\n", 997 "Kernel text patching", 998 (void *)instruction_pointer(regs)); 999 1000 /* We cannot handle this */ 1001 return DBG_HOOK_ERROR; 1002 } 1003 1004 static struct break_hook fault_break_hook = { 1005 .fn = reserved_fault_handler, 1006 .imm = FAULT_BRK_IMM, 1007 }; 1008 1009 #ifdef CONFIG_KASAN_SW_TAGS 1010 1011 #define KASAN_ESR_RECOVER 0x20 1012 #define KASAN_ESR_WRITE 0x10 1013 #define KASAN_ESR_SIZE_MASK 0x0f 1014 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) 1015 1016 static int kasan_handler(struct pt_regs *regs, unsigned int esr) 1017 { 1018 bool recover = esr & KASAN_ESR_RECOVER; 1019 bool write = esr & KASAN_ESR_WRITE; 1020 size_t size = KASAN_ESR_SIZE(esr); 1021 u64 addr = regs->regs[0]; 1022 u64 pc = regs->pc; 1023 1024 kasan_report(addr, size, write, pc); 1025 1026 /* 1027 * The instrumentation allows to control whether we can proceed after 1028 * a crash was detected. This is done by passing the -recover flag to 1029 * the compiler. Disabling recovery allows to generate more compact 1030 * code. 1031 * 1032 * Unfortunately disabling recovery doesn't work for the kernel right 1033 * now. KASAN reporting is disabled in some contexts (for example when 1034 * the allocator accesses slab object metadata; this is controlled by 1035 * current->kasan_depth). All these accesses are detected by the tool, 1036 * even though the reports for them are not printed. 1037 * 1038 * This is something that might be fixed at some point in the future. 1039 */ 1040 if (!recover) 1041 die("Oops - KASAN", regs, 0); 1042 1043 /* If thread survives, skip over the brk instruction and continue: */ 1044 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1045 return DBG_HOOK_HANDLED; 1046 } 1047 1048 static struct break_hook kasan_break_hook = { 1049 .fn = kasan_handler, 1050 .imm = KASAN_BRK_IMM, 1051 .mask = KASAN_BRK_MASK, 1052 }; 1053 #endif 1054 1055 /* 1056 * Initial handler for AArch64 BRK exceptions 1057 * This handler only used until debug_traps_init(). 1058 */ 1059 int __init early_brk64(unsigned long addr, unsigned int esr, 1060 struct pt_regs *regs) 1061 { 1062 #ifdef CONFIG_KASAN_SW_TAGS 1063 unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; 1064 1065 if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM) 1066 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; 1067 #endif 1068 return bug_handler(regs, esr) != DBG_HOOK_HANDLED; 1069 } 1070 1071 void __init trap_init(void) 1072 { 1073 register_kernel_break_hook(&bug_break_hook); 1074 register_kernel_break_hook(&fault_break_hook); 1075 #ifdef CONFIG_KASAN_SW_TAGS 1076 register_kernel_break_hook(&kasan_break_hook); 1077 #endif 1078 debug_traps_init(); 1079 } 1080