1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/sys_arm.c 4 * 5 * Copyright (C) People who wrote linux/arch/i386/kernel/sys_i386.c 6 * Copyright (C) 1995, 1996 Russell King. 7 * Copyright (C) 2012 ARM Ltd. 8 */ 9 10 #include <linux/compat.h> 11 #include <linux/cpufeature.h> 12 #include <linux/personality.h> 13 #include <linux/sched.h> 14 #include <linux/sched/signal.h> 15 #include <linux/slab.h> 16 #include <linux/syscalls.h> 17 #include <linux/uaccess.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/system_misc.h> 21 #include <asm/tlbflush.h> 22 #include <asm/unistd.h> 23 24 static long 25 __do_compat_cache_op(unsigned long start, unsigned long end) 26 { 27 long ret; 28 29 do { 30 unsigned long chunk = min(PAGE_SIZE, end - start); 31 32 if (fatal_signal_pending(current)) 33 return 0; 34 35 if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { 36 /* 37 * The workaround requires an inner-shareable tlbi. 38 * We pick the reserved-ASID to minimise the impact. 39 */ 40 __tlbi(aside1is, __TLBI_VADDR(0, 0)); 41 dsb(ish); 42 } 43 44 ret = caches_clean_inval_user_pou(start, start + chunk); 45 if (ret) 46 return ret; 47 48 cond_resched(); 49 start += chunk; 50 } while (start < end); 51 52 return 0; 53 } 54 55 static inline long 56 do_compat_cache_op(unsigned long start, unsigned long end, int flags) 57 { 58 if (end < start || flags) 59 return -EINVAL; 60 61 if (!access_ok((const void __user *)start, end - start)) 62 return -EFAULT; 63 64 return __do_compat_cache_op(start, end); 65 } 66 /* 67 * Handle all unrecognised system calls. 68 */ 69 long compat_arm_syscall(struct pt_regs *regs, int scno) 70 { 71 unsigned long addr; 72 73 switch (scno) { 74 /* 75 * Flush a region from virtual address 'r0' to virtual address 'r1' 76 * _exclusive_. There is no alignment requirement on either address; 77 * user space does not need to know the hardware cache layout. 78 * 79 * r2 contains flags. It should ALWAYS be passed as ZERO until it 80 * is defined to be something else. For now we ignore it, but may 81 * the fires of hell burn in your belly if you break this rule. ;) 82 * 83 * (at a later date, we may want to allow this call to not flush 84 * various aspects of the cache. Passing '0' will guarantee that 85 * everything necessary gets flushed to maintain consistency in 86 * the specified region). 87 */ 88 case __ARM_NR_compat_cacheflush: 89 return do_compat_cache_op(regs->regs[0], regs->regs[1], regs->regs[2]); 90 91 case __ARM_NR_compat_set_tls: 92 current->thread.uw.tp_value = regs->regs[0]; 93 94 /* 95 * Protect against register corruption from context switch. 96 * See comment in tls_thread_flush. 97 */ 98 barrier(); 99 write_sysreg(regs->regs[0], tpidrro_el0); 100 return 0; 101 102 default: 103 /* 104 * Calls 0xf0xxx..0xf07ff are defined to return -ENOSYS 105 * if not implemented, rather than raising SIGILL. This 106 * way the calling program can gracefully determine whether 107 * a feature is supported. 108 */ 109 if (scno < __ARM_NR_COMPAT_END) 110 return -ENOSYS; 111 break; 112 } 113 114 addr = instruction_pointer(regs) - (compat_thumb_mode(regs) ? 2 : 4); 115 116 arm64_notify_die("Oops - bad compat syscall(2)", regs, 117 SIGILL, ILL_ILLTRP, addr, scno); 118 return 0; 119 } 120