195322526SLorenzo Pieralisi#include <linux/errno.h> 295322526SLorenzo Pieralisi#include <linux/linkage.h> 395322526SLorenzo Pieralisi#include <asm/asm-offsets.h> 495322526SLorenzo Pieralisi#include <asm/assembler.h> 595322526SLorenzo Pieralisi 695322526SLorenzo Pieralisi .text 795322526SLorenzo Pieralisi/* 895322526SLorenzo Pieralisi * Implementation of MPIDR_EL1 hash algorithm through shifting 995322526SLorenzo Pieralisi * and OR'ing. 1095322526SLorenzo Pieralisi * 1195322526SLorenzo Pieralisi * @dst: register containing hash result 1295322526SLorenzo Pieralisi * @rs0: register containing affinity level 0 bit shift 1395322526SLorenzo Pieralisi * @rs1: register containing affinity level 1 bit shift 1495322526SLorenzo Pieralisi * @rs2: register containing affinity level 2 bit shift 1595322526SLorenzo Pieralisi * @rs3: register containing affinity level 3 bit shift 1695322526SLorenzo Pieralisi * @mpidr: register containing MPIDR_EL1 value 1795322526SLorenzo Pieralisi * @mask: register containing MPIDR mask 1895322526SLorenzo Pieralisi * 1995322526SLorenzo Pieralisi * Pseudo C-code: 2095322526SLorenzo Pieralisi * 2195322526SLorenzo Pieralisi *u32 dst; 2295322526SLorenzo Pieralisi * 2395322526SLorenzo Pieralisi *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) { 2495322526SLorenzo Pieralisi * u32 aff0, aff1, aff2, aff3; 2595322526SLorenzo Pieralisi * u64 mpidr_masked = mpidr & mask; 2695322526SLorenzo Pieralisi * aff0 = mpidr_masked & 0xff; 2795322526SLorenzo Pieralisi * aff1 = mpidr_masked & 0xff00; 2895322526SLorenzo Pieralisi * aff2 = mpidr_masked & 0xff0000; 2995322526SLorenzo Pieralisi * aff2 = mpidr_masked & 0xff00000000; 3095322526SLorenzo Pieralisi * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3); 3195322526SLorenzo Pieralisi *} 3295322526SLorenzo Pieralisi * Input registers: rs0, rs1, rs2, rs3, mpidr, mask 3395322526SLorenzo Pieralisi * Output register: dst 3495322526SLorenzo Pieralisi * Note: input and output registers must be disjoint register sets 3595322526SLorenzo Pieralisi (eg: a macro instance with mpidr = x1 and dst = x1 is invalid) 3695322526SLorenzo Pieralisi */ 3795322526SLorenzo Pieralisi .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask 3895322526SLorenzo Pieralisi and \mpidr, \mpidr, \mask // mask out MPIDR bits 3995322526SLorenzo Pieralisi and \dst, \mpidr, #0xff // mask=aff0 4095322526SLorenzo Pieralisi lsr \dst ,\dst, \rs0 // dst=aff0>>rs0 4195322526SLorenzo Pieralisi and \mask, \mpidr, #0xff00 // mask = aff1 4295322526SLorenzo Pieralisi lsr \mask ,\mask, \rs1 4395322526SLorenzo Pieralisi orr \dst, \dst, \mask // dst|=(aff1>>rs1) 4495322526SLorenzo Pieralisi and \mask, \mpidr, #0xff0000 // mask = aff2 4595322526SLorenzo Pieralisi lsr \mask ,\mask, \rs2 4695322526SLorenzo Pieralisi orr \dst, \dst, \mask // dst|=(aff2>>rs2) 4795322526SLorenzo Pieralisi and \mask, \mpidr, #0xff00000000 // mask = aff3 4895322526SLorenzo Pieralisi lsr \mask ,\mask, \rs3 4995322526SLorenzo Pieralisi orr \dst, \dst, \mask // dst|=(aff3>>rs3) 5095322526SLorenzo Pieralisi .endm 5195322526SLorenzo Pieralisi/* 52adc9b2dfSJames Morse * Save CPU state in the provided sleep_stack_data area, and publish its 53adc9b2dfSJames Morse * location for cpu_resume()'s use in sleep_save_stash. 5495322526SLorenzo Pieralisi * 55adc9b2dfSJames Morse * cpu_resume() will restore this saved state, and return. Because the 56adc9b2dfSJames Morse * link-register is saved and restored, it will appear to return from this 57adc9b2dfSJames Morse * function. So that the caller can tell the suspend/resume paths apart, 58adc9b2dfSJames Morse * __cpu_suspend_enter() will always return a non-zero value, whereas the 59adc9b2dfSJames Morse * path through cpu_resume() will return 0. 60adc9b2dfSJames Morse * 61adc9b2dfSJames Morse * x0 = struct sleep_stack_data area 6295322526SLorenzo Pieralisi */ 63714f5992SLorenzo PieralisiENTRY(__cpu_suspend_enter) 64adc9b2dfSJames Morse stp x29, lr, [x0, #SLEEP_STACK_DATA_CALLEE_REGS] 65adc9b2dfSJames Morse stp x19, x20, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+16] 66adc9b2dfSJames Morse stp x21, x22, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+32] 67adc9b2dfSJames Morse stp x23, x24, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+48] 68adc9b2dfSJames Morse stp x25, x26, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+64] 69adc9b2dfSJames Morse stp x27, x28, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+80] 70adc9b2dfSJames Morse 71adc9b2dfSJames Morse /* save the sp in cpu_suspend_ctx */ 7295322526SLorenzo Pieralisi mov x2, sp 73adc9b2dfSJames Morse str x2, [x0, #SLEEP_STACK_DATA_SYSTEM_REGS + CPU_CTX_SP] 74adc9b2dfSJames Morse 75adc9b2dfSJames Morse /* find the mpidr_hash */ 76b5fe2429SArd Biesheuvel ldr_l x1, sleep_save_stash 7795322526SLorenzo Pieralisi mrs x7, mpidr_el1 78b5fe2429SArd Biesheuvel adr_l x9, mpidr_hash 7995322526SLorenzo Pieralisi ldr x10, [x9, #MPIDR_HASH_MASK] 8095322526SLorenzo Pieralisi /* 8195322526SLorenzo Pieralisi * Following code relies on the struct mpidr_hash 8295322526SLorenzo Pieralisi * members size. 8395322526SLorenzo Pieralisi */ 8495322526SLorenzo Pieralisi ldp w3, w4, [x9, #MPIDR_HASH_SHIFTS] 8595322526SLorenzo Pieralisi ldp w5, w6, [x9, #(MPIDR_HASH_SHIFTS + 8)] 8695322526SLorenzo Pieralisi compute_mpidr_hash x8, x3, x4, x5, x6, x7, x10 87714f5992SLorenzo Pieralisi add x1, x1, x8, lsl #3 88adc9b2dfSJames Morse 89cabe1c81SJames Morse str x0, [x1] 90cabe1c81SJames Morse add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS 91adc9b2dfSJames Morse stp x29, lr, [sp, #-16]! 92cabe1c81SJames Morse bl cpu_do_suspend 93adc9b2dfSJames Morse ldp x29, lr, [sp], #16 94adc9b2dfSJames Morse mov x0, #1 9595322526SLorenzo Pieralisi ret 96714f5992SLorenzo PieralisiENDPROC(__cpu_suspend_enter) 9795322526SLorenzo Pieralisi 98b6113038SJames Morse .pushsection ".idmap.text", "ax" 9995322526SLorenzo PieralisiENTRY(cpu_resume) 10095322526SLorenzo Pieralisi bl el2_setup // if in EL2 drop to EL1 cleanly 101b5fe2429SArd Biesheuvel bl __cpu_setup 102cabe1c81SJames Morse /* enable the MMU early - so we can access sleep_save_stash by va */ 1039dcf7914SArd Biesheuvel bl __enable_mmu 104bc9f3d77SArd Biesheuvel ldr x8, =_cpu_resume 105bc9f3d77SArd Biesheuvel br x8 1069dcf7914SArd BiesheuvelENDPROC(cpu_resume) 107bc9f3d77SArd Biesheuvel .ltorg 108bc9f3d77SArd Biesheuvel .popsection 109bc9f3d77SArd Biesheuvel 110dc002475SArd BiesheuvelENTRY(_cpu_resume) 11195322526SLorenzo Pieralisi mrs x1, mpidr_el1 112b5fe2429SArd Biesheuvel adr_l x8, mpidr_hash // x8 = struct mpidr_hash virt address 113b5fe2429SArd Biesheuvel 11495322526SLorenzo Pieralisi /* retrieve mpidr_hash members to compute the hash */ 11595322526SLorenzo Pieralisi ldr x2, [x8, #MPIDR_HASH_MASK] 11695322526SLorenzo Pieralisi ldp w3, w4, [x8, #MPIDR_HASH_SHIFTS] 11795322526SLorenzo Pieralisi ldp w5, w6, [x8, #(MPIDR_HASH_SHIFTS + 8)] 11895322526SLorenzo Pieralisi compute_mpidr_hash x7, x3, x4, x5, x6, x1, x2 119b5fe2429SArd Biesheuvel 12095322526SLorenzo Pieralisi /* x7 contains hash index, let's use it to grab context pointer */ 121cabe1c81SJames Morse ldr_l x0, sleep_save_stash 12295322526SLorenzo Pieralisi ldr x0, [x0, x7, lsl #3] 123adc9b2dfSJames Morse add x29, x0, #SLEEP_STACK_DATA_CALLEE_REGS 124adc9b2dfSJames Morse add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS 12595322526SLorenzo Pieralisi /* load sp from context */ 12695322526SLorenzo Pieralisi ldr x2, [x0, #CPU_CTX_SP] 12795322526SLorenzo Pieralisi mov sp, x2 1286cdf9c7cSJungseok Lee /* save thread_info */ 1296cdf9c7cSJungseok Lee and x2, x2, #~(THREAD_SIZE - 1) 1306cdf9c7cSJungseok Lee msr sp_el0, x2 13195322526SLorenzo Pieralisi /* 132cabe1c81SJames Morse * cpu_do_resume expects x0 to contain context address pointer 13395322526SLorenzo Pieralisi */ 134cabe1c81SJames Morse bl cpu_do_resume 135cabe1c81SJames Morse 136cabe1c81SJames Morse#ifdef CONFIG_KASAN 137cabe1c81SJames Morse mov x0, sp 138cabe1c81SJames Morse bl kasan_unpoison_remaining_stack 139cabe1c81SJames Morse#endif 140cabe1c81SJames Morse 141adc9b2dfSJames Morse ldp x19, x20, [x29, #16] 142adc9b2dfSJames Morse ldp x21, x22, [x29, #32] 143adc9b2dfSJames Morse ldp x23, x24, [x29, #48] 144adc9b2dfSJames Morse ldp x25, x26, [x29, #64] 145adc9b2dfSJames Morse ldp x27, x28, [x29, #80] 146adc9b2dfSJames Morse ldp x29, lr, [x29] 147cabe1c81SJames Morse mov x0, #0 148cabe1c81SJames Morse ret 149cabe1c81SJames MorseENDPROC(_cpu_resume) 150