1d1e5ca64SVincenzo Frascino/* SPDX-License-Identifier: GPL-2.0 */ 2d1e5ca64SVincenzo Frascino/* 3d1e5ca64SVincenzo Frascino * AArch32 sigreturn code. 4d1e5ca64SVincenzo Frascino * Based on the kuser helpers in arch/arm/kernel/entry-armv.S. 5d1e5ca64SVincenzo Frascino * 6d1e5ca64SVincenzo Frascino * Copyright (C) 2005-2011 Nicolas Pitre <nico@fluxnic.net> 7d1e5ca64SVincenzo Frascino * Copyright (C) 2012-2018 ARM Ltd. 8d1e5ca64SVincenzo Frascino * 9d1e5ca64SVincenzo Frascino * For ARM syscalls, the syscall number has to be loaded into r7. 10d1e5ca64SVincenzo Frascino * We do not support an OABI userspace. 11d1e5ca64SVincenzo Frascino * 12d1e5ca64SVincenzo Frascino * For Thumb syscalls, we also pass the syscall number via r7. We therefore 13d1e5ca64SVincenzo Frascino * need two 16-bit instructions. 14d1e5ca64SVincenzo Frascino */ 15d1e5ca64SVincenzo Frascino 16d1e5ca64SVincenzo Frascino#include <asm/unistd.h> 17d1e5ca64SVincenzo Frascino 18*d9b728f8SChen Zhongjin .section .rodata 19d1e5ca64SVincenzo Frascino .globl __aarch32_sigret_code_start 20d1e5ca64SVincenzo Frascino__aarch32_sigret_code_start: 21d1e5ca64SVincenzo Frascino 22d1e5ca64SVincenzo Frascino /* 23d1e5ca64SVincenzo Frascino * ARM Code 24d1e5ca64SVincenzo Frascino */ 25d1e5ca64SVincenzo Frascino .byte __NR_compat_sigreturn, 0x70, 0xa0, 0xe3 // mov r7, #__NR_compat_sigreturn 26d1e5ca64SVincenzo Frascino .byte __NR_compat_sigreturn, 0x00, 0x00, 0xef // svc #__NR_compat_sigreturn 27d1e5ca64SVincenzo Frascino 28d1e5ca64SVincenzo Frascino /* 29d1e5ca64SVincenzo Frascino * Thumb code 30d1e5ca64SVincenzo Frascino */ 31d1e5ca64SVincenzo Frascino .byte __NR_compat_sigreturn, 0x27 // svc #__NR_compat_sigreturn 32d1e5ca64SVincenzo Frascino .byte __NR_compat_sigreturn, 0xdf // mov r7, #__NR_compat_sigreturn 33d1e5ca64SVincenzo Frascino 34d1e5ca64SVincenzo Frascino /* 35d1e5ca64SVincenzo Frascino * ARM code 36d1e5ca64SVincenzo Frascino */ 37d1e5ca64SVincenzo Frascino .byte __NR_compat_rt_sigreturn, 0x70, 0xa0, 0xe3 // mov r7, #__NR_compat_rt_sigreturn 38d1e5ca64SVincenzo Frascino .byte __NR_compat_rt_sigreturn, 0x00, 0x00, 0xef // svc #__NR_compat_rt_sigreturn 39d1e5ca64SVincenzo Frascino 40d1e5ca64SVincenzo Frascino /* 41d1e5ca64SVincenzo Frascino * Thumb code 42d1e5ca64SVincenzo Frascino */ 43d1e5ca64SVincenzo Frascino .byte __NR_compat_rt_sigreturn, 0x27 // svc #__NR_compat_rt_sigreturn 44d1e5ca64SVincenzo Frascino .byte __NR_compat_rt_sigreturn, 0xdf // mov r7, #__NR_compat_rt_sigreturn 45d1e5ca64SVincenzo Frascino 46d1e5ca64SVincenzo Frascino .globl __aarch32_sigret_code_end 47d1e5ca64SVincenzo Frascino__aarch32_sigret_code_end: 48