1 /* 2 * Based on arch/arm/kernel/setup.c 3 * 4 * Copyright (C) 1995-2001 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/acpi.h> 21 #include <linux/export.h> 22 #include <linux/kernel.h> 23 #include <linux/stddef.h> 24 #include <linux/ioport.h> 25 #include <linux/delay.h> 26 #include <linux/utsname.h> 27 #include <linux/initrd.h> 28 #include <linux/console.h> 29 #include <linux/cache.h> 30 #include <linux/bootmem.h> 31 #include <linux/screen_info.h> 32 #include <linux/init.h> 33 #include <linux/kexec.h> 34 #include <linux/root_dev.h> 35 #include <linux/cpu.h> 36 #include <linux/interrupt.h> 37 #include <linux/smp.h> 38 #include <linux/fs.h> 39 #include <linux/proc_fs.h> 40 #include <linux/memblock.h> 41 #include <linux/of_fdt.h> 42 #include <linux/efi.h> 43 #include <linux/psci.h> 44 #include <linux/sched/task.h> 45 #include <linux/mm.h> 46 47 #include <asm/acpi.h> 48 #include <asm/fixmap.h> 49 #include <asm/cpu.h> 50 #include <asm/cputype.h> 51 #include <asm/elf.h> 52 #include <asm/cpufeature.h> 53 #include <asm/cpu_ops.h> 54 #include <asm/kasan.h> 55 #include <asm/numa.h> 56 #include <asm/sections.h> 57 #include <asm/setup.h> 58 #include <asm/smp_plat.h> 59 #include <asm/cacheflush.h> 60 #include <asm/tlbflush.h> 61 #include <asm/traps.h> 62 #include <asm/memblock.h> 63 #include <asm/efi.h> 64 #include <asm/xen/hypervisor.h> 65 #include <asm/mmu_context.h> 66 67 phys_addr_t __fdt_pointer __initdata; 68 69 /* 70 * Standard memory resources 71 */ 72 static struct resource mem_res[] = { 73 { 74 .name = "Kernel code", 75 .start = 0, 76 .end = 0, 77 .flags = IORESOURCE_SYSTEM_RAM 78 }, 79 { 80 .name = "Kernel data", 81 .start = 0, 82 .end = 0, 83 .flags = IORESOURCE_SYSTEM_RAM 84 } 85 }; 86 87 #define kernel_code mem_res[0] 88 #define kernel_data mem_res[1] 89 90 /* 91 * The recorded values of x0 .. x3 upon kernel entry. 92 */ 93 u64 __cacheline_aligned boot_args[4]; 94 95 void __init smp_setup_processor_id(void) 96 { 97 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; 98 cpu_logical_map(0) = mpidr; 99 100 /* 101 * clear __my_cpu_offset on boot CPU to avoid hang caused by 102 * using percpu variable early, for example, lockdep will 103 * access percpu variable inside lock_release 104 */ 105 set_my_cpu_offset(0); 106 pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr); 107 } 108 109 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 110 { 111 return phys_id == cpu_logical_map(cpu); 112 } 113 114 struct mpidr_hash mpidr_hash; 115 /** 116 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity 117 * level in order to build a linear index from an 118 * MPIDR value. Resulting algorithm is a collision 119 * free hash carried out through shifting and ORing 120 */ 121 static void __init smp_build_mpidr_hash(void) 122 { 123 u32 i, affinity, fs[4], bits[4], ls; 124 u64 mask = 0; 125 /* 126 * Pre-scan the list of MPIDRS and filter out bits that do 127 * not contribute to affinity levels, ie they never toggle. 128 */ 129 for_each_possible_cpu(i) 130 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); 131 pr_debug("mask of set bits %#llx\n", mask); 132 /* 133 * Find and stash the last and first bit set at all affinity levels to 134 * check how many bits are required to represent them. 135 */ 136 for (i = 0; i < 4; i++) { 137 affinity = MPIDR_AFFINITY_LEVEL(mask, i); 138 /* 139 * Find the MSB bit and LSB bits position 140 * to determine how many bits are required 141 * to express the affinity level. 142 */ 143 ls = fls(affinity); 144 fs[i] = affinity ? ffs(affinity) - 1 : 0; 145 bits[i] = ls - fs[i]; 146 } 147 /* 148 * An index can be created from the MPIDR_EL1 by isolating the 149 * significant bits at each affinity level and by shifting 150 * them in order to compress the 32 bits values space to a 151 * compressed set of values. This is equivalent to hashing 152 * the MPIDR_EL1 through shifting and ORing. It is a collision free 153 * hash though not minimal since some levels might contain a number 154 * of CPUs that is not an exact power of 2 and their bit 155 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. 156 */ 157 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0]; 158 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; 159 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - 160 (bits[1] + bits[0]); 161 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) + 162 fs[3] - (bits[2] + bits[1] + bits[0]); 163 mpidr_hash.mask = mask; 164 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0]; 165 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", 166 mpidr_hash.shift_aff[0], 167 mpidr_hash.shift_aff[1], 168 mpidr_hash.shift_aff[2], 169 mpidr_hash.shift_aff[3], 170 mpidr_hash.mask, 171 mpidr_hash.bits); 172 /* 173 * 4x is an arbitrary value used to warn on a hash table much bigger 174 * than expected on most systems. 175 */ 176 if (mpidr_hash_size() > 4 * num_possible_cpus()) 177 pr_warn("Large number of MPIDR hash buckets detected\n"); 178 } 179 180 static void __init setup_machine_fdt(phys_addr_t dt_phys) 181 { 182 void *dt_virt = fixmap_remap_fdt(dt_phys); 183 const char *name; 184 185 if (!dt_virt || !early_init_dt_scan(dt_virt)) { 186 pr_crit("\n" 187 "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n" 188 "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n" 189 "\nPlease check your bootloader.", 190 &dt_phys, dt_virt); 191 192 while (true) 193 cpu_relax(); 194 } 195 196 name = of_flat_dt_get_machine_name(); 197 pr_info("Machine model: %s\n", name); 198 dump_stack_set_arch_desc("%s (DT)", name); 199 } 200 201 static void __init request_standard_resources(void) 202 { 203 struct memblock_region *region; 204 struct resource *res; 205 206 kernel_code.start = __pa_symbol(_text); 207 kernel_code.end = __pa_symbol(__init_begin - 1); 208 kernel_data.start = __pa_symbol(_sdata); 209 kernel_data.end = __pa_symbol(_end - 1); 210 211 for_each_memblock(memory, region) { 212 res = alloc_bootmem_low(sizeof(*res)); 213 if (memblock_is_nomap(region)) { 214 res->name = "reserved"; 215 res->flags = IORESOURCE_MEM; 216 } else { 217 res->name = "System RAM"; 218 res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY; 219 } 220 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); 221 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; 222 223 request_resource(&iomem_resource, res); 224 225 if (kernel_code.start >= res->start && 226 kernel_code.end <= res->end) 227 request_resource(res, &kernel_code); 228 if (kernel_data.start >= res->start && 229 kernel_data.end <= res->end) 230 request_resource(res, &kernel_data); 231 #ifdef CONFIG_KEXEC_CORE 232 /* Userspace will find "Crash kernel" region in /proc/iomem. */ 233 if (crashk_res.end && crashk_res.start >= res->start && 234 crashk_res.end <= res->end) 235 request_resource(res, &crashk_res); 236 #endif 237 } 238 } 239 240 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; 241 242 void __init setup_arch(char **cmdline_p) 243 { 244 pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id()); 245 246 sprintf(init_utsname()->machine, UTS_MACHINE); 247 init_mm.start_code = (unsigned long) _text; 248 init_mm.end_code = (unsigned long) _etext; 249 init_mm.end_data = (unsigned long) _edata; 250 init_mm.brk = (unsigned long) _end; 251 252 *cmdline_p = boot_command_line; 253 254 early_fixmap_init(); 255 early_ioremap_init(); 256 257 setup_machine_fdt(__fdt_pointer); 258 259 parse_early_param(); 260 261 /* 262 * Unmask asynchronous aborts after bringing up possible earlycon. 263 * (Report possible System Errors once we can report this occurred) 264 */ 265 local_async_enable(); 266 267 /* 268 * TTBR0 is only used for the identity mapping at this stage. Make it 269 * point to zero page to avoid speculatively fetching new entries. 270 */ 271 cpu_uninstall_idmap(); 272 273 xen_early_init(); 274 efi_init(); 275 arm64_memblock_init(); 276 277 paging_init(); 278 279 acpi_table_upgrade(); 280 281 /* Parse the ACPI tables for possible boot-time configuration */ 282 acpi_boot_table_init(); 283 284 if (acpi_disabled) 285 unflatten_device_tree(); 286 287 bootmem_init(); 288 289 kasan_init(); 290 291 request_standard_resources(); 292 293 early_ioremap_reset(); 294 295 if (acpi_disabled) 296 psci_dt_init(); 297 else 298 psci_acpi_init(); 299 300 cpu_read_bootcpu_ops(); 301 smp_init_cpus(); 302 smp_build_mpidr_hash(); 303 304 #ifdef CONFIG_ARM64_SW_TTBR0_PAN 305 /* 306 * Make sure init_thread_info.ttbr0 always generates translation 307 * faults in case uaccess_enable() is inadvertently called by the init 308 * thread. 309 */ 310 init_task.thread_info.ttbr0 = __pa_symbol(empty_zero_page); 311 #endif 312 313 #ifdef CONFIG_VT 314 #if defined(CONFIG_VGA_CONSOLE) 315 conswitchp = &vga_con; 316 #elif defined(CONFIG_DUMMY_CONSOLE) 317 conswitchp = &dummy_con; 318 #endif 319 #endif 320 if (boot_args[1] || boot_args[2] || boot_args[3]) { 321 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n" 322 "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n" 323 "This indicates a broken bootloader or old kernel\n", 324 boot_args[1], boot_args[2], boot_args[3]); 325 } 326 } 327 328 static int __init topology_init(void) 329 { 330 int i; 331 332 for_each_online_node(i) 333 register_one_node(i); 334 335 for_each_possible_cpu(i) { 336 struct cpu *cpu = &per_cpu(cpu_data.cpu, i); 337 cpu->hotpluggable = 1; 338 register_cpu(cpu, i); 339 } 340 341 return 0; 342 } 343 subsys_initcall(topology_init); 344 345 /* 346 * Dump out kernel offset information on panic. 347 */ 348 static int dump_kernel_offset(struct notifier_block *self, unsigned long v, 349 void *p) 350 { 351 const unsigned long offset = kaslr_offset(); 352 353 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) { 354 pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n", 355 offset, KIMAGE_VADDR); 356 } else { 357 pr_emerg("Kernel Offset: disabled\n"); 358 } 359 return 0; 360 } 361 362 static struct notifier_block kernel_offset_notifier = { 363 .notifier_call = dump_kernel_offset 364 }; 365 366 static int __init register_kernel_offset_dumper(void) 367 { 368 atomic_notifier_chain_register(&panic_notifier_list, 369 &kernel_offset_notifier); 370 return 0; 371 } 372 __initcall(register_kernel_offset_dumper); 373