1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/setup.c 4 * 5 * Copyright (C) 1995-2001 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/export.h> 11 #include <linux/kernel.h> 12 #include <linux/stddef.h> 13 #include <linux/ioport.h> 14 #include <linux/delay.h> 15 #include <linux/initrd.h> 16 #include <linux/console.h> 17 #include <linux/cache.h> 18 #include <linux/screen_info.h> 19 #include <linux/init.h> 20 #include <linux/kexec.h> 21 #include <linux/root_dev.h> 22 #include <linux/cpu.h> 23 #include <linux/interrupt.h> 24 #include <linux/smp.h> 25 #include <linux/fs.h> 26 #include <linux/proc_fs.h> 27 #include <linux/memblock.h> 28 #include <linux/of_fdt.h> 29 #include <linux/efi.h> 30 #include <linux/psci.h> 31 #include <linux/sched/task.h> 32 #include <linux/mm.h> 33 34 #include <asm/acpi.h> 35 #include <asm/fixmap.h> 36 #include <asm/cpu.h> 37 #include <asm/cputype.h> 38 #include <asm/daifflags.h> 39 #include <asm/elf.h> 40 #include <asm/cpufeature.h> 41 #include <asm/cpu_ops.h> 42 #include <asm/kasan.h> 43 #include <asm/numa.h> 44 #include <asm/sections.h> 45 #include <asm/setup.h> 46 #include <asm/smp_plat.h> 47 #include <asm/cacheflush.h> 48 #include <asm/tlbflush.h> 49 #include <asm/traps.h> 50 #include <asm/efi.h> 51 #include <asm/xen/hypervisor.h> 52 #include <asm/mmu_context.h> 53 54 static int num_standard_resources; 55 static struct resource *standard_resources; 56 57 phys_addr_t __fdt_pointer __initdata; 58 59 /* 60 * Standard memory resources 61 */ 62 static struct resource mem_res[] = { 63 { 64 .name = "Kernel code", 65 .start = 0, 66 .end = 0, 67 .flags = IORESOURCE_SYSTEM_RAM 68 }, 69 { 70 .name = "Kernel data", 71 .start = 0, 72 .end = 0, 73 .flags = IORESOURCE_SYSTEM_RAM 74 } 75 }; 76 77 #define kernel_code mem_res[0] 78 #define kernel_data mem_res[1] 79 80 /* 81 * The recorded values of x0 .. x3 upon kernel entry. 82 */ 83 u64 __cacheline_aligned boot_args[4]; 84 85 void __init smp_setup_processor_id(void) 86 { 87 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; 88 set_cpu_logical_map(0, mpidr); 89 90 pr_info("Booting Linux on physical CPU 0x%010lx [0x%08x]\n", 91 (unsigned long)mpidr, read_cpuid_id()); 92 } 93 94 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 95 { 96 return phys_id == cpu_logical_map(cpu); 97 } 98 99 struct mpidr_hash mpidr_hash; 100 /** 101 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity 102 * level in order to build a linear index from an 103 * MPIDR value. Resulting algorithm is a collision 104 * free hash carried out through shifting and ORing 105 */ 106 static void __init smp_build_mpidr_hash(void) 107 { 108 u32 i, affinity, fs[4], bits[4], ls; 109 u64 mask = 0; 110 /* 111 * Pre-scan the list of MPIDRS and filter out bits that do 112 * not contribute to affinity levels, ie they never toggle. 113 */ 114 for_each_possible_cpu(i) 115 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); 116 pr_debug("mask of set bits %#llx\n", mask); 117 /* 118 * Find and stash the last and first bit set at all affinity levels to 119 * check how many bits are required to represent them. 120 */ 121 for (i = 0; i < 4; i++) { 122 affinity = MPIDR_AFFINITY_LEVEL(mask, i); 123 /* 124 * Find the MSB bit and LSB bits position 125 * to determine how many bits are required 126 * to express the affinity level. 127 */ 128 ls = fls(affinity); 129 fs[i] = affinity ? ffs(affinity) - 1 : 0; 130 bits[i] = ls - fs[i]; 131 } 132 /* 133 * An index can be created from the MPIDR_EL1 by isolating the 134 * significant bits at each affinity level and by shifting 135 * them in order to compress the 32 bits values space to a 136 * compressed set of values. This is equivalent to hashing 137 * the MPIDR_EL1 through shifting and ORing. It is a collision free 138 * hash though not minimal since some levels might contain a number 139 * of CPUs that is not an exact power of 2 and their bit 140 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. 141 */ 142 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0]; 143 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; 144 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - 145 (bits[1] + bits[0]); 146 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) + 147 fs[3] - (bits[2] + bits[1] + bits[0]); 148 mpidr_hash.mask = mask; 149 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0]; 150 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", 151 mpidr_hash.shift_aff[0], 152 mpidr_hash.shift_aff[1], 153 mpidr_hash.shift_aff[2], 154 mpidr_hash.shift_aff[3], 155 mpidr_hash.mask, 156 mpidr_hash.bits); 157 /* 158 * 4x is an arbitrary value used to warn on a hash table much bigger 159 * than expected on most systems. 160 */ 161 if (mpidr_hash_size() > 4 * num_possible_cpus()) 162 pr_warn("Large number of MPIDR hash buckets detected\n"); 163 } 164 165 static void *early_fdt_ptr __initdata; 166 167 void __init *get_early_fdt_ptr(void) 168 { 169 return early_fdt_ptr; 170 } 171 172 asmlinkage void __init early_fdt_map(u64 dt_phys) 173 { 174 int fdt_size; 175 176 early_fixmap_init(); 177 early_fdt_ptr = fixmap_remap_fdt(dt_phys, &fdt_size, PAGE_KERNEL); 178 } 179 180 static void __init setup_machine_fdt(phys_addr_t dt_phys) 181 { 182 int size; 183 void *dt_virt = fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL); 184 const char *name; 185 186 if (dt_virt) 187 memblock_reserve(dt_phys, size); 188 189 if (!dt_virt || !early_init_dt_scan(dt_virt)) { 190 pr_crit("\n" 191 "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n" 192 "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n" 193 "\nPlease check your bootloader.", 194 &dt_phys, dt_virt); 195 196 while (true) 197 cpu_relax(); 198 } 199 200 /* Early fixups are done, map the FDT as read-only now */ 201 fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL_RO); 202 203 name = of_flat_dt_get_machine_name(); 204 if (!name) 205 return; 206 207 pr_info("Machine model: %s\n", name); 208 dump_stack_set_arch_desc("%s (DT)", name); 209 } 210 211 static void __init request_standard_resources(void) 212 { 213 struct memblock_region *region; 214 struct resource *res; 215 unsigned long i = 0; 216 size_t res_size; 217 218 kernel_code.start = __pa_symbol(_stext); 219 kernel_code.end = __pa_symbol(__init_begin - 1); 220 kernel_data.start = __pa_symbol(_sdata); 221 kernel_data.end = __pa_symbol(_end - 1); 222 223 num_standard_resources = memblock.memory.cnt; 224 res_size = num_standard_resources * sizeof(*standard_resources); 225 standard_resources = memblock_alloc(res_size, SMP_CACHE_BYTES); 226 if (!standard_resources) 227 panic("%s: Failed to allocate %zu bytes\n", __func__, res_size); 228 229 for_each_mem_region(region) { 230 res = &standard_resources[i++]; 231 if (memblock_is_nomap(region)) { 232 res->name = "reserved"; 233 res->flags = IORESOURCE_MEM; 234 } else { 235 res->name = "System RAM"; 236 res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY; 237 } 238 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); 239 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; 240 241 request_resource(&iomem_resource, res); 242 243 if (kernel_code.start >= res->start && 244 kernel_code.end <= res->end) 245 request_resource(res, &kernel_code); 246 if (kernel_data.start >= res->start && 247 kernel_data.end <= res->end) 248 request_resource(res, &kernel_data); 249 #ifdef CONFIG_KEXEC_CORE 250 /* Userspace will find "Crash kernel" region in /proc/iomem. */ 251 if (crashk_res.end && crashk_res.start >= res->start && 252 crashk_res.end <= res->end) 253 request_resource(res, &crashk_res); 254 #endif 255 } 256 } 257 258 static int __init reserve_memblock_reserved_regions(void) 259 { 260 u64 i, j; 261 262 for (i = 0; i < num_standard_resources; ++i) { 263 struct resource *mem = &standard_resources[i]; 264 phys_addr_t r_start, r_end, mem_size = resource_size(mem); 265 266 if (!memblock_is_region_reserved(mem->start, mem_size)) 267 continue; 268 269 for_each_reserved_mem_range(j, &r_start, &r_end) { 270 resource_size_t start, end; 271 272 start = max(PFN_PHYS(PFN_DOWN(r_start)), mem->start); 273 end = min(PFN_PHYS(PFN_UP(r_end)) - 1, mem->end); 274 275 if (start > mem->end || end < mem->start) 276 continue; 277 278 reserve_region_with_split(mem, start, end, "reserved"); 279 } 280 } 281 282 return 0; 283 } 284 arch_initcall(reserve_memblock_reserved_regions); 285 286 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; 287 288 u64 cpu_logical_map(unsigned int cpu) 289 { 290 return __cpu_logical_map[cpu]; 291 } 292 293 void __init __no_sanitize_address setup_arch(char **cmdline_p) 294 { 295 init_mm.start_code = (unsigned long) _stext; 296 init_mm.end_code = (unsigned long) _etext; 297 init_mm.end_data = (unsigned long) _edata; 298 init_mm.brk = (unsigned long) _end; 299 300 *cmdline_p = boot_command_line; 301 302 /* 303 * If know now we are going to need KPTI then use non-global 304 * mappings from the start, avoiding the cost of rewriting 305 * everything later. 306 */ 307 arm64_use_ng_mappings = kaslr_requires_kpti(); 308 309 early_fixmap_init(); 310 early_ioremap_init(); 311 312 setup_machine_fdt(__fdt_pointer); 313 314 /* 315 * Initialise the static keys early as they may be enabled by the 316 * cpufeature code and early parameters. 317 */ 318 jump_label_init(); 319 parse_early_param(); 320 321 /* 322 * Unmask asynchronous aborts and fiq after bringing up possible 323 * earlycon. (Report possible System Errors once we can report this 324 * occurred). 325 */ 326 local_daif_restore(DAIF_PROCCTX_NOIRQ); 327 328 /* 329 * TTBR0 is only used for the identity mapping at this stage. Make it 330 * point to zero page to avoid speculatively fetching new entries. 331 */ 332 cpu_uninstall_idmap(); 333 334 xen_early_init(); 335 efi_init(); 336 337 if (!efi_enabled(EFI_BOOT) && ((u64)_text % MIN_KIMG_ALIGN) != 0) 338 pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!"); 339 340 arm64_memblock_init(); 341 342 paging_init(); 343 344 acpi_table_upgrade(); 345 346 /* Parse the ACPI tables for possible boot-time configuration */ 347 acpi_boot_table_init(); 348 349 if (acpi_disabled) 350 unflatten_device_tree(); 351 352 bootmem_init(); 353 354 kasan_init(); 355 356 request_standard_resources(); 357 358 early_ioremap_reset(); 359 360 if (acpi_disabled) 361 psci_dt_init(); 362 else 363 psci_acpi_init(); 364 365 init_bootcpu_ops(); 366 smp_init_cpus(); 367 smp_build_mpidr_hash(); 368 369 /* Init percpu seeds for random tags after cpus are set up. */ 370 kasan_init_sw_tags(); 371 372 #ifdef CONFIG_ARM64_SW_TTBR0_PAN 373 /* 374 * Make sure init_thread_info.ttbr0 always generates translation 375 * faults in case uaccess_enable() is inadvertently called by the init 376 * thread. 377 */ 378 init_task.thread_info.ttbr0 = __pa_symbol(reserved_pg_dir); 379 #endif 380 381 if (boot_args[1] || boot_args[2] || boot_args[3]) { 382 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n" 383 "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n" 384 "This indicates a broken bootloader or old kernel\n", 385 boot_args[1], boot_args[2], boot_args[3]); 386 } 387 } 388 389 static inline bool cpu_can_disable(unsigned int cpu) 390 { 391 #ifdef CONFIG_HOTPLUG_CPU 392 const struct cpu_operations *ops = get_cpu_ops(cpu); 393 394 if (ops && ops->cpu_can_disable) 395 return ops->cpu_can_disable(cpu); 396 #endif 397 return false; 398 } 399 400 static int __init topology_init(void) 401 { 402 int i; 403 404 for_each_online_node(i) 405 register_one_node(i); 406 407 for_each_possible_cpu(i) { 408 struct cpu *cpu = &per_cpu(cpu_data.cpu, i); 409 cpu->hotpluggable = cpu_can_disable(i); 410 register_cpu(cpu, i); 411 } 412 413 return 0; 414 } 415 subsys_initcall(topology_init); 416 417 static void dump_kernel_offset(void) 418 { 419 const unsigned long offset = kaslr_offset(); 420 421 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) { 422 pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n", 423 offset, KIMAGE_VADDR); 424 pr_emerg("PHYS_OFFSET: 0x%llx\n", PHYS_OFFSET); 425 } else { 426 pr_emerg("Kernel Offset: disabled\n"); 427 } 428 } 429 430 static int arm64_panic_block_dump(struct notifier_block *self, 431 unsigned long v, void *p) 432 { 433 dump_kernel_offset(); 434 dump_cpu_features(); 435 dump_mem_limit(); 436 return 0; 437 } 438 439 static struct notifier_block arm64_panic_block = { 440 .notifier_call = arm64_panic_block_dump 441 }; 442 443 static int __init register_arm64_panic_block(void) 444 { 445 atomic_notifier_chain_register(&panic_notifier_list, 446 &arm64_panic_block); 447 return 0; 448 } 449 device_initcall(register_arm64_panic_block); 450