xref: /openbmc/linux/arch/arm64/kernel/setup.c (revision 206a81c1) 
1 /*
2  * Based on arch/arm/kernel/setup.c
3  *
4  * Copyright (C) 1995-2001 Russell King
5  * Copyright (C) 2012 ARM Ltd.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include <linux/export.h>
21 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/ioport.h>
24 #include <linux/delay.h>
25 #include <linux/utsname.h>
26 #include <linux/initrd.h>
27 #include <linux/console.h>
28 #include <linux/cache.h>
29 #include <linux/bootmem.h>
30 #include <linux/seq_file.h>
31 #include <linux/screen_info.h>
32 #include <linux/init.h>
33 #include <linux/kexec.h>
34 #include <linux/crash_dump.h>
35 #include <linux/root_dev.h>
36 #include <linux/clk-provider.h>
37 #include <linux/cpu.h>
38 #include <linux/interrupt.h>
39 #include <linux/smp.h>
40 #include <linux/fs.h>
41 #include <linux/proc_fs.h>
42 #include <linux/memblock.h>
43 #include <linux/of_fdt.h>
44 #include <linux/of_platform.h>
45 #include <linux/efi.h>
46 
47 #include <asm/fixmap.h>
48 #include <asm/cputype.h>
49 #include <asm/elf.h>
50 #include <asm/cputable.h>
51 #include <asm/cpu_ops.h>
52 #include <asm/sections.h>
53 #include <asm/setup.h>
54 #include <asm/smp_plat.h>
55 #include <asm/cacheflush.h>
56 #include <asm/tlbflush.h>
57 #include <asm/traps.h>
58 #include <asm/memblock.h>
59 #include <asm/psci.h>
60 #include <asm/efi.h>
61 
62 unsigned int processor_id;
63 EXPORT_SYMBOL(processor_id);
64 
65 unsigned long elf_hwcap __read_mostly;
66 EXPORT_SYMBOL_GPL(elf_hwcap);
67 
68 #ifdef CONFIG_COMPAT
69 #define COMPAT_ELF_HWCAP_DEFAULT	\
70 				(COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
71 				 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
72 				 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
73 				 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
74 				 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
75 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
76 unsigned int compat_elf_hwcap2 __read_mostly;
77 #endif
78 
79 static const char *cpu_name;
80 static const char *machine_name;
81 phys_addr_t __fdt_pointer __initdata;
82 
83 /*
84  * Standard memory resources
85  */
86 static struct resource mem_res[] = {
87 	{
88 		.name = "Kernel code",
89 		.start = 0,
90 		.end = 0,
91 		.flags = IORESOURCE_MEM
92 	},
93 	{
94 		.name = "Kernel data",
95 		.start = 0,
96 		.end = 0,
97 		.flags = IORESOURCE_MEM
98 	}
99 };
100 
101 #define kernel_code mem_res[0]
102 #define kernel_data mem_res[1]
103 
104 void __init early_print(const char *str, ...)
105 {
106 	char buf[256];
107 	va_list ap;
108 
109 	va_start(ap, str);
110 	vsnprintf(buf, sizeof(buf), str, ap);
111 	va_end(ap);
112 
113 	printk("%s", buf);
114 }
115 
116 void __init smp_setup_processor_id(void)
117 {
118 	/*
119 	 * clear __my_cpu_offset on boot CPU to avoid hang caused by
120 	 * using percpu variable early, for example, lockdep will
121 	 * access percpu variable inside lock_release
122 	 */
123 	set_my_cpu_offset(0);
124 }
125 
126 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
127 {
128 	return phys_id == cpu_logical_map(cpu);
129 }
130 
131 struct mpidr_hash mpidr_hash;
132 #ifdef CONFIG_SMP
133 /**
134  * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
135  *			  level in order to build a linear index from an
136  *			  MPIDR value. Resulting algorithm is a collision
137  *			  free hash carried out through shifting and ORing
138  */
139 static void __init smp_build_mpidr_hash(void)
140 {
141 	u32 i, affinity, fs[4], bits[4], ls;
142 	u64 mask = 0;
143 	/*
144 	 * Pre-scan the list of MPIDRS and filter out bits that do
145 	 * not contribute to affinity levels, ie they never toggle.
146 	 */
147 	for_each_possible_cpu(i)
148 		mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
149 	pr_debug("mask of set bits %#llx\n", mask);
150 	/*
151 	 * Find and stash the last and first bit set at all affinity levels to
152 	 * check how many bits are required to represent them.
153 	 */
154 	for (i = 0; i < 4; i++) {
155 		affinity = MPIDR_AFFINITY_LEVEL(mask, i);
156 		/*
157 		 * Find the MSB bit and LSB bits position
158 		 * to determine how many bits are required
159 		 * to express the affinity level.
160 		 */
161 		ls = fls(affinity);
162 		fs[i] = affinity ? ffs(affinity) - 1 : 0;
163 		bits[i] = ls - fs[i];
164 	}
165 	/*
166 	 * An index can be created from the MPIDR_EL1 by isolating the
167 	 * significant bits at each affinity level and by shifting
168 	 * them in order to compress the 32 bits values space to a
169 	 * compressed set of values. This is equivalent to hashing
170 	 * the MPIDR_EL1 through shifting and ORing. It is a collision free
171 	 * hash though not minimal since some levels might contain a number
172 	 * of CPUs that is not an exact power of 2 and their bit
173 	 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
174 	 */
175 	mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
176 	mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
177 	mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
178 						(bits[1] + bits[0]);
179 	mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
180 				  fs[3] - (bits[2] + bits[1] + bits[0]);
181 	mpidr_hash.mask = mask;
182 	mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
183 	pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
184 		mpidr_hash.shift_aff[0],
185 		mpidr_hash.shift_aff[1],
186 		mpidr_hash.shift_aff[2],
187 		mpidr_hash.shift_aff[3],
188 		mpidr_hash.mask,
189 		mpidr_hash.bits);
190 	/*
191 	 * 4x is an arbitrary value used to warn on a hash table much bigger
192 	 * than expected on most systems.
193 	 */
194 	if (mpidr_hash_size() > 4 * num_possible_cpus())
195 		pr_warn("Large number of MPIDR hash buckets detected\n");
196 	__flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
197 }
198 #endif
199 
200 static void __init setup_processor(void)
201 {
202 	struct cpu_info *cpu_info;
203 	u64 features, block;
204 	u32 cwg;
205 	int cls;
206 
207 	cpu_info = lookup_processor_type(read_cpuid_id());
208 	if (!cpu_info) {
209 		printk("CPU configuration botched (ID %08x), unable to continue.\n",
210 		       read_cpuid_id());
211 		while (1);
212 	}
213 
214 	cpu_name = cpu_info->cpu_name;
215 
216 	printk("CPU: %s [%08x] revision %d\n",
217 	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
218 
219 	sprintf(init_utsname()->machine, ELF_PLATFORM);
220 	elf_hwcap = 0;
221 
222 	/*
223 	 * Check for sane CTR_EL0.CWG value.
224 	 */
225 	cwg = cache_type_cwg();
226 	cls = cache_line_size();
227 	if (!cwg)
228 		pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
229 			cls);
230 	if (L1_CACHE_BYTES < cls)
231 		pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
232 			L1_CACHE_BYTES, cls);
233 
234 	/*
235 	 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
236 	 * The blocks we test below represent incremental functionality
237 	 * for non-negative values. Negative values are reserved.
238 	 */
239 	features = read_cpuid(ID_AA64ISAR0_EL1);
240 	block = (features >> 4) & 0xf;
241 	if (!(block & 0x8)) {
242 		switch (block) {
243 		default:
244 		case 2:
245 			elf_hwcap |= HWCAP_PMULL;
246 		case 1:
247 			elf_hwcap |= HWCAP_AES;
248 		case 0:
249 			break;
250 		}
251 	}
252 
253 	block = (features >> 8) & 0xf;
254 	if (block && !(block & 0x8))
255 		elf_hwcap |= HWCAP_SHA1;
256 
257 	block = (features >> 12) & 0xf;
258 	if (block && !(block & 0x8))
259 		elf_hwcap |= HWCAP_SHA2;
260 
261 	block = (features >> 16) & 0xf;
262 	if (block && !(block & 0x8))
263 		elf_hwcap |= HWCAP_CRC32;
264 
265 #ifdef CONFIG_COMPAT
266 	/*
267 	 * ID_ISAR5_EL1 carries similar information as above, but pertaining to
268 	 * the Aarch32 32-bit execution state.
269 	 */
270 	features = read_cpuid(ID_ISAR5_EL1);
271 	block = (features >> 4) & 0xf;
272 	if (!(block & 0x8)) {
273 		switch (block) {
274 		default:
275 		case 2:
276 			compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
277 		case 1:
278 			compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
279 		case 0:
280 			break;
281 		}
282 	}
283 
284 	block = (features >> 8) & 0xf;
285 	if (block && !(block & 0x8))
286 		compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
287 
288 	block = (features >> 12) & 0xf;
289 	if (block && !(block & 0x8))
290 		compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
291 
292 	block = (features >> 16) & 0xf;
293 	if (block && !(block & 0x8))
294 		compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
295 #endif
296 }
297 
298 static void __init setup_machine_fdt(phys_addr_t dt_phys)
299 {
300 	if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
301 		early_print("\n"
302 			"Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
303 			"The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
304 			"\nPlease check your bootloader.\n",
305 			dt_phys, phys_to_virt(dt_phys));
306 
307 		while (true)
308 			cpu_relax();
309 	}
310 
311 	machine_name = of_flat_dt_get_machine_name();
312 }
313 
314 /*
315  * Limit the memory size that was specified via FDT.
316  */
317 static int __init early_mem(char *p)
318 {
319 	phys_addr_t limit;
320 
321 	if (!p)
322 		return 1;
323 
324 	limit = memparse(p, &p) & PAGE_MASK;
325 	pr_notice("Memory limited to %lldMB\n", limit >> 20);
326 
327 	memblock_enforce_memory_limit(limit);
328 
329 	return 0;
330 }
331 early_param("mem", early_mem);
332 
333 static void __init request_standard_resources(void)
334 {
335 	struct memblock_region *region;
336 	struct resource *res;
337 
338 	kernel_code.start   = virt_to_phys(_text);
339 	kernel_code.end     = virt_to_phys(_etext - 1);
340 	kernel_data.start   = virt_to_phys(_sdata);
341 	kernel_data.end     = virt_to_phys(_end - 1);
342 
343 	for_each_memblock(memory, region) {
344 		res = alloc_bootmem_low(sizeof(*res));
345 		res->name  = "System RAM";
346 		res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
347 		res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
348 		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
349 
350 		request_resource(&iomem_resource, res);
351 
352 		if (kernel_code.start >= res->start &&
353 		    kernel_code.end <= res->end)
354 			request_resource(res, &kernel_code);
355 		if (kernel_data.start >= res->start &&
356 		    kernel_data.end <= res->end)
357 			request_resource(res, &kernel_data);
358 	}
359 }
360 
361 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
362 
363 void __init setup_arch(char **cmdline_p)
364 {
365 	/*
366 	 * Unmask asynchronous aborts early to catch possible system errors.
367 	 */
368 	local_async_enable();
369 
370 	setup_processor();
371 
372 	setup_machine_fdt(__fdt_pointer);
373 
374 	init_mm.start_code = (unsigned long) _text;
375 	init_mm.end_code   = (unsigned long) _etext;
376 	init_mm.end_data   = (unsigned long) _edata;
377 	init_mm.brk	   = (unsigned long) _end;
378 
379 	*cmdline_p = boot_command_line;
380 
381 	early_ioremap_init();
382 
383 	parse_early_param();
384 
385 	efi_init();
386 	arm64_memblock_init();
387 
388 	paging_init();
389 	request_standard_resources();
390 
391 	efi_idmap_init();
392 
393 	unflatten_device_tree();
394 
395 	psci_init();
396 
397 	cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
398 	cpu_read_bootcpu_ops();
399 #ifdef CONFIG_SMP
400 	smp_init_cpus();
401 	smp_build_mpidr_hash();
402 #endif
403 
404 #ifdef CONFIG_VT
405 #if defined(CONFIG_VGA_CONSOLE)
406 	conswitchp = &vga_con;
407 #elif defined(CONFIG_DUMMY_CONSOLE)
408 	conswitchp = &dummy_con;
409 #endif
410 #endif
411 }
412 
413 static int __init arm64_device_init(void)
414 {
415 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
416 	return 0;
417 }
418 arch_initcall_sync(arm64_device_init);
419 
420 static DEFINE_PER_CPU(struct cpu, cpu_data);
421 
422 static int __init topology_init(void)
423 {
424 	int i;
425 
426 	for_each_possible_cpu(i) {
427 		struct cpu *cpu = &per_cpu(cpu_data, i);
428 		cpu->hotpluggable = 1;
429 		register_cpu(cpu, i);
430 	}
431 
432 	return 0;
433 }
434 subsys_initcall(topology_init);
435 
436 static const char *hwcap_str[] = {
437 	"fp",
438 	"asimd",
439 	"evtstrm",
440 	"aes",
441 	"pmull",
442 	"sha1",
443 	"sha2",
444 	"crc32",
445 	NULL
446 };
447 
448 static int c_show(struct seq_file *m, void *v)
449 {
450 	int i;
451 
452 	seq_printf(m, "Processor\t: %s rev %d (%s)\n",
453 		   cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
454 
455 	for_each_online_cpu(i) {
456 		/*
457 		 * glibc reads /proc/cpuinfo to determine the number of
458 		 * online processors, looking for lines beginning with
459 		 * "processor".  Give glibc what it expects.
460 		 */
461 #ifdef CONFIG_SMP
462 		seq_printf(m, "processor\t: %d\n", i);
463 #endif
464 	}
465 
466 	/* dump out the processor features */
467 	seq_puts(m, "Features\t: ");
468 
469 	for (i = 0; hwcap_str[i]; i++)
470 		if (elf_hwcap & (1 << i))
471 			seq_printf(m, "%s ", hwcap_str[i]);
472 
473 	seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
474 	seq_printf(m, "CPU architecture: AArch64\n");
475 	seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
476 	seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
477 	seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
478 
479 	seq_puts(m, "\n");
480 
481 	seq_printf(m, "Hardware\t: %s\n", machine_name);
482 
483 	return 0;
484 }
485 
486 static void *c_start(struct seq_file *m, loff_t *pos)
487 {
488 	return *pos < 1 ? (void *)1 : NULL;
489 }
490 
491 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
492 {
493 	++*pos;
494 	return NULL;
495 }
496 
497 static void c_stop(struct seq_file *m, void *v)
498 {
499 }
500 
501 const struct seq_operations cpuinfo_op = {
502 	.start	= c_start,
503 	.next	= c_next,
504 	.stop	= c_stop,
505 	.show	= c_show
506 };
507